Coaxial Through-Package-Vias (TPVs) for ... - Semantic Scholar
Coaxial Through-Package-Vias (TPVs) for Enhancing Power Integrity in 3D Double-side Glass Interposers Gokul Kumar, P. Markondeya Raj, Jounghyun Cho*, Saumya Gandhi, Parthasarathi Chakraborti, Venky Sundaram, Joungho Kim* and Rao Tummala 3D Systems Packaging Research Center, Georgia Institute of Technology * Terahertz Laboratory, KAIST, Daejeon, South Korea Email: [email protected] ABSTRACT Double-sided 3D glass interposers and packages, with through package vias (TPV) at the same pitch as TSVs in Si, have been proposed to achieve high bandwidth between logic and memory with benefits in cost, process complexity, testability and thermal over 3D IC stacks with TSV. However, such a 3D interposer introduces power distribution network (PDN) challenges due to increased power delivery path length and plane resonances. This paper investigates the use of coaxial through-package-vias (TPVs) with high dielectric constant liners as an effective method to deliver clean power within a 3D glass package, and provides design and fabrication guidelines to achieve the PDN target impedance. The Coaxial TPV structure is simulated using electromagnetic (EM) solvers and a simplified equivalent circuit model to study via impedance and parasitics. Test vehicles with anodized tantalum oxide capacitors were fabricated in ultra-thin, 100µm thick glass interposers to demonstrate process feasibility, with a capacitance density of 5 nF/mm2. Self-impedance (Z11) of a 3D glass interposer containing the coaxial TPVs was analyzed with variations in (a) Via location, (b) Number of coaxial vias, and (c) Via capacitance and stack-up, to provide optimal PDN design guidelines. Based on the above parameters, the added decoupling vias achieved more than 30% impedance suppression over multiple resonance frequencies between 0.56 GHz, providing an effective and flexible PDN design method for double-side 3D glass interposers. I. INTRODUCTION Logic and memory stacking with through silicon vias (TSV) to form 3D ICs, with much higher interconnect density than the current package-on-package (PoP) stacking, has been proposed and is being developed to meet ultra-high bandwidth (25-100GB/s) demands of smart mobile systems with lower power consumption and miniaturization. However, the adoption of these 3D ICs has been delayed by many challenges that include thermal issues, testability and high cost. A simpler approach to achieve this high bandwidth using ultra-thin 3D glass packages has been proposed and fabricated by Georgia Tech [1] [2], which results in elimination of complex and costly TSVs in the logic die, as shown in Figure 1. Such a 3D glass approach uses an ultra-thin, 30-50µm glass interposer with stacked memory on one side and logic IC on the other side, interconnected by through package vias (TPVs) at the same pitch as TSVs in Si, and SMT mounted onto the printed wiring board (PWB) through solder ball interconnections [3]. While this technology offers cost, testability and thermal advantages over 3D IC stacking, it introduces a new challenge in power delivery, directly attributable to the long PDN path through lateral power-ground (P/G) planes. In addition, multi-mode plane resonances in glass interposers, that are common to high-
978-1-4799-2407-3/14/$31.00 ©2014 IEEE
resistivity substrates including organic packages, require careful PDN design. Memory
TSV
Memory
Memory
Memory
Memory
Memory
Memory
TSV
Logic
Memory
Silicon Interposer or Org. Pkg
Glass interposer
BGA
BGA
PCB
TPV
Logic
PCB 3D ICs with TSVs
3D Glass Interposers with TPVs
Figure 1 : Approaches for high bandwidth 3D-integration
Distributed Coaxial P/G TPVs as Decap
Memory Stack Lateral PDN Path
P/G planes P/G BGA
Logic
PCB
Figure 2 : 3D Glass interposer PDN with coaxial Vias as distributed decoupling capacitors This paper, for the first time, integrates high-dielectric constant materials into TPVs in ultra-thin glass interposers to improve the PDN performance of double sided 3D interposers, and the techniques presented here can also be applied to singlechip 2D packages and multi-chip 2.5D interposers. Figure 2 illustrates the major power delivery challenges in 3D glass interposers and the proposed structure with coaxial TPVs to address some of these challenges. The coaxial TPVs with high dielectric constant thin films between the power and ground via conductors form ultra-miniaturized decoupling capacitors along the package power path. This distributed capacitance, placed very close to the active die, acts as charge reservoirs and presents an improved power delivery solution without ESL limitations or additional space requirements. The authors previously reported the PDN characteristics of 3D double-side interposers with reduced power/ground ball
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2014 Electronic Components & Technology Conference
grid arrays (BGAs) due to the placement of logic die at the bottom of the substrate [4]. The effects of noise coupling between signal nets and power/ground planes at resonant frequencies , including the impact of signal return path discontinuity were studied [5]. Recent literature compared the effects of simultaneous switching noise and signal discontinuity in silicon and glass interposers using M-FDM methods [6, 7]. Embedded and die-integrated decoupling schemes have been proposed with glass and silicon interposers to improve their power delivery profile [8-10]. Recent studies employed three-dimensional P/G coaxial vias (TSVs) in 3DIC stacks for added coupling capacitance [11]. However, effect of via placement and physical geometry in the power and signal integrity of double-sided flip-chip interposers has not been investigated. This paper goes beyond published literature to present a detailed study of the PDN impedance profile in 3D glass interposers including the effects of via interconnection capacitances. In addition, it explores and demonstrates the use of coaxial through-package-vias as an effective design technique to improve power delivery networks.
tantalum oxide and barium titanate between the inner conductor and outer shell of coaxial TPVs in an ultra-thin glass substrate is studied provide up to 50x higher via decoupling capacitance. Figure 3 shows the electrical block diagram of the 3D interposer PDN including coaxial TPVs.
VRM
Board Decap
PCB P/G Planes
3µm
17.5µm
22.5µm
17.5µm 30µm
17.5 µm
Polymer
60µm
Polymer 10 µm
22.5µm
3µm
Tantalum 40 nm
Tantalum 40 nm
17.5µm
19.92µm 71µm
60µm
100µm
17.5µm
II. ELECTRICAL DESIGN OF COAXIAL THROUGH PACKAGE VIAS This section examines via parasitics for different coaxial TPV process methods and stack-up technologies, and presents a simplified circuit model to analyze coaxial via interconnects. The parasitic properties of the coaxial vias that are most critical for PDN design, including the inductance, capacitance and total via impedance are analyzed first. Both analytical equations and an electromagnetic solver (Q3D) is used for this study for parametric analysis. Since the overall resistance of thick coaxial vias are extremely small, they are not focused in this section. Integration of high-k thinfilm materials such as
L o On-chip a Decap d
(c)
(b)
(a)
3µm
Following this introduction, Section II describes the modeling and design of coaxial vias. Parasitics for different technologies are examined and extracted using full-wave electromagnetic (EM) solvers, forming building blocks for the subsequent analysis. An equivalent circuit model is proposed to identify the key parameters contributing to the capacitance, and the results are tabulated. Section III deals with a discussion of various dielectric options, selection of the front-up materials, and an initial process demonstration for the TPV with capacitors in 3D glass interposers. Section IV studies the benefit of the proposed coaxial vias to address PDN challenge by modeling the PDN response with and without decoupling vias from the previous sections. Based on this investigation, design guidelines for an optimal P/G TPV physical design and dimensions are provided. Section V summarizes the results from this study.
Coaxial Cap
Interposer P/G Planes
On-Chip Mesh
Figure 3: Schematic Diagram of 3D interposer PDN
30µm
30-60 µm 40nm 30-100µm 17mm x17mm 25mm x25mm 400 µm
Package Decap
C4
Embedded Decap
Table 1: 3D interposer system dimensions Coaxial TPV Diameter Tantalum Liner Thickness Ultra-thin Core Thickness Interposer/Package size PWB size BGA pitch
Package Lateral PCB BGA P/GTrace Trace Vias Balls Length Length
PCB Traces
30µm 3µm
Glass
Polymer
17.5µm 30 µm
49.92µm 71µm
180µm
Figure 4: Co-axial Via Dimensions considered in this Study - 40nm tantalum oxide liner with (a) 30m Glass thickness (b) 100m thickness, 15m polymer liner with (c) 30m glass thickness Table 2: Summary of coaxial via capacitance Liner Glass Theoretical Q3D (pF) 𝜀 Thickness material Value (pF) (µm) 12.7 30 12.4 Tantalum 25 Oxide 120 100 117 Polymer
3.01
30
0.0117
0.018
Table 3: Summary of coaxial via loop inductance Glass Outer Inner Q3D Theoretical Thickness Radius Radius Value (pH) (pH) (µm) (µm) (µm) 30 10 9.96 0.028 0.022 100 25 24.96 0.042 0.032 30 25 15 3.63 4.7 (polymer) Considering current technology and future miniaturization, three coaxial TPV physical configurations are chosen as shown in Figure 4. Two variations of total TPV height (71 µm and 180 µm) in ultra-thin glass substrates (including dielectric and glass sections) is considered with both moderate-K(Tantalum oxide) and polymer liner configurations. The target metallization thickness was defined to be 5 µm.
542
From literature, simplified analytical expressions for capacitance and loop inductance per unit length of a coaxial via can be given as 2𝜋𝜀0 𝜀𝑟
μ
𝐷 𝑙𝑛( ) 𝑑
𝐿𝐿 = 2π ln(𝐷/𝑑)
(c) 25µm Polymer TPV
F/m H/m
Mag (Z11)
𝐶𝐿 =
decoupling at lower frequencies, enabling selective tuning to meet target impedance.
𝐷 is the outer via radius 𝑑 is the radius of the inner via 𝜀0 , 𝜀𝑟 is the permittivity of free space and TPV liner
P G
(a) 30µm TPV
(b) 100µm TPV
µ is the permeability
Table 2 presents a summary of various capacitance values that are extracted for coaxial vias. As expected, it can be seen that the maximum value of capacitance is achieved with the 100m glass via having the tantalum liner due to the highest capacitance density and surface area. Table 3 details the loop inductance of coaxial TPVs. It can be seen that the loop inductance of the p/g via is extremely small due to the thin coaxial liner, when compared with the loop inductance of a polymer based coaxial TPV. These results indicate useful PDN applications with the proposed P/G TPV configurations. Based on the extracted values, a simplified equivalent circuit model for glass TPVs was constructed as shown in Figure 5. It can be seen that the dominant capacitance is from the thin high-K liner material that is separated by the power and ground conductors, and has a theoretical value in several tens of pico farads. Power Top
Frequency (Hz)
Figure 6: Self-Impedance profile of single P/G coaxial via III. POWER-GROUND TPV: MATERIALS AND PROCESSES 3D interposers need to support low impedance powerground coaxial TPVs for efficient power supply. Based on the simulations shown in the previous section, the power-ground needs a capacitance in the order of 50-100 pF per via. This section deals with a discussion on various dielectric options, selection of the front-up materials, and an initial process demonstration for the TPV capacitors in 3D glass interposers. Table 4: Dielectric options for TPV capacitors in 3D interposers, and their merits and demerits
Ground Top C
Dielectric
GDielectric R
Outer
L
R C G
Outer
Film properties
Oxides Oxynitrides
7 t = 20 nm 2.5 nF/mm2
Moderate K paraelectrics -Tantalum oxide High K super paraelectrics - BST
t = 40 nm 5 nF/mm2
Inner
Liner
Liner
L
Inner
C
Dielectric
GDielectric Power Bottom
Dielectrics
Ground Bottom
Figure 5: Circuit model for Coaxial P/G Glass TPVs The impedance profile between the power and ground vias of a single coaxial TPV from different configurations was simulated using a full wave EM solver (HFSS) as shown in Figure 6. The self-impedance is measured between via pads of the top two metal layers as shown. It was seen that lowest impedance was observed with 100µm coaxial TPV due to its large surface area and length of the capacitor, followed by the ultra-thin 30 µm TPV. The impedance of polymer based coaxial vias were several orders higher than the other configurations, with smaller capacitive values due to larger separation between the metal plates. The effective capacitance of coaxial vias can be increased by connecting a number of the coaxial P/G vias in parallel, similar to the configuration present in interposer applications. The higher capacitance vias exhibit
High K ferroelectrics - Barium titanate
t = 150 nm 15-20 nF/mm2 t = 1 µm 30 nF/mm2
Merits High BDV allows 30 nm films Standard semiconduct or tools Simpler processing compared to high K films Dielectric constant low but stable with lower loss High density
Demerits Expensive semiconductor tools, Lower capacitance densities;
Moderate capacitance densities
Conformal dielectric is a challenge with standard processes
Higher temperature processing, Lower reliability and leakage, Conformal dielectric is a challenge with standard processes
Dielectric options Low k films: In silicon trench and TSV capacitors, oxides, nitrides and oxynitrides of silicon with permittivies of 5-7 are widely used. The Breakdown Voltages (BDVs) of these films range from 0.8-1 V/nm which represent the highest BDV of all materials. Even a 20 nm film can stand voltage of 15 V.
543
Furthermore, these materials present minimal reliability concerns because of their intrinsic structure and properties. This leads to a planar capacitance density of about 2-3 nF/mm2. Moreover, these technologies are dependent on very standard front-end semiconductor tools such as Plasma Enhanced Chemical Vapor Deposition (PECVD), Liquid Phase Chemical Vapor Deposition (LPCVD). The deposition temperatures are less than 300 C, and no issues of adhesion and thermomechanical compatibility arise because of their strong covalent bonding to the electrode and good CTE match with glass. However, higher capacitance densities with low-cost panel processes are sought for 3D glass interposers. Moderate k films: Oxides of tantalum, hafnium, zirconia, titania etc. show permittivities of 15-80. Some of these have breakdown strengths of 500-800 V/micron. They can be deposited thinner down to 30-50 nm showing capacitance densities approaching 5-10 nF/mm2. Moderate k films represent 2-3 X improvement in capacitance density compared to traditional oxides and nitrides. The most common technique for depositing these thin films in trenches is Atomic Layer Deposition (ALD), which also has cost and through-put limitations. High k films: Ferroelectrics show permittivities of 10005000 in 1-3 micron thickness, with a capacitance density of about 30 nF/mm2. Films with these properties require extremely high temperature processes (~1000 oC). The permittivity reduces dramatically for thinner films, and therefore the capacitance density does not improve much. With glass TPV-compatible processes (
978-1-4799-2407-3/14/$31.00 ©2014 IEEE
resistivity substrates including organic packages, require careful PDN design. Memory
TSV
Memory
Memory
Memory
Memory
Memory
Memory
TSV
Logic
Memory
Silicon Interposer or Org. Pkg
Glass interposer
BGA
BGA
PCB
TPV
Logic
PCB 3D ICs with TSVs
3D Glass Interposers with TPVs
Figure 1 : Approaches for high bandwidth 3D-integration
Distributed Coaxial P/G TPVs as Decap
Memory Stack Lateral PDN Path
P/G planes P/G BGA
Logic
PCB
Figure 2 : 3D Glass interposer PDN with coaxial Vias as distributed decoupling capacitors This paper, for the first time, integrates high-dielectric constant materials into TPVs in ultra-thin glass interposers to improve the PDN performance of double sided 3D interposers, and the techniques presented here can also be applied to singlechip 2D packages and multi-chip 2.5D interposers. Figure 2 illustrates the major power delivery challenges in 3D glass interposers and the proposed structure with coaxial TPVs to address some of these challenges. The coaxial TPVs with high dielectric constant thin films between the power and ground via conductors form ultra-miniaturized decoupling capacitors along the package power path. This distributed capacitance, placed very close to the active die, acts as charge reservoirs and presents an improved power delivery solution without ESL limitations or additional space requirements. The authors previously reported the PDN characteristics of 3D double-side interposers with reduced power/ground ball
541
2014 Electronic Components & Technology Conference
grid arrays (BGAs) due to the placement of logic die at the bottom of the substrate [4]. The effects of noise coupling between signal nets and power/ground planes at resonant frequencies , including the impact of signal return path discontinuity were studied [5]. Recent literature compared the effects of simultaneous switching noise and signal discontinuity in silicon and glass interposers using M-FDM methods [6, 7]. Embedded and die-integrated decoupling schemes have been proposed with glass and silicon interposers to improve their power delivery profile [8-10]. Recent studies employed three-dimensional P/G coaxial vias (TSVs) in 3DIC stacks for added coupling capacitance [11]. However, effect of via placement and physical geometry in the power and signal integrity of double-sided flip-chip interposers has not been investigated. This paper goes beyond published literature to present a detailed study of the PDN impedance profile in 3D glass interposers including the effects of via interconnection capacitances. In addition, it explores and demonstrates the use of coaxial through-package-vias as an effective design technique to improve power delivery networks.
tantalum oxide and barium titanate between the inner conductor and outer shell of coaxial TPVs in an ultra-thin glass substrate is studied provide up to 50x higher via decoupling capacitance. Figure 3 shows the electrical block diagram of the 3D interposer PDN including coaxial TPVs.
VRM
Board Decap
PCB P/G Planes
3µm
17.5µm
22.5µm
17.5µm 30µm
17.5 µm
Polymer
60µm
Polymer 10 µm
22.5µm
3µm
Tantalum 40 nm
Tantalum 40 nm
17.5µm
19.92µm 71µm
60µm
100µm
17.5µm
II. ELECTRICAL DESIGN OF COAXIAL THROUGH PACKAGE VIAS This section examines via parasitics for different coaxial TPV process methods and stack-up technologies, and presents a simplified circuit model to analyze coaxial via interconnects. The parasitic properties of the coaxial vias that are most critical for PDN design, including the inductance, capacitance and total via impedance are analyzed first. Both analytical equations and an electromagnetic solver (Q3D) is used for this study for parametric analysis. Since the overall resistance of thick coaxial vias are extremely small, they are not focused in this section. Integration of high-k thinfilm materials such as
L o On-chip a Decap d
(c)
(b)
(a)
3µm
Following this introduction, Section II describes the modeling and design of coaxial vias. Parasitics for different technologies are examined and extracted using full-wave electromagnetic (EM) solvers, forming building blocks for the subsequent analysis. An equivalent circuit model is proposed to identify the key parameters contributing to the capacitance, and the results are tabulated. Section III deals with a discussion of various dielectric options, selection of the front-up materials, and an initial process demonstration for the TPV with capacitors in 3D glass interposers. Section IV studies the benefit of the proposed coaxial vias to address PDN challenge by modeling the PDN response with and without decoupling vias from the previous sections. Based on this investigation, design guidelines for an optimal P/G TPV physical design and dimensions are provided. Section V summarizes the results from this study.
Coaxial Cap
Interposer P/G Planes
On-Chip Mesh
Figure 3: Schematic Diagram of 3D interposer PDN
30µm
30-60 µm 40nm 30-100µm 17mm x17mm 25mm x25mm 400 µm
Package Decap
C4
Embedded Decap
Table 1: 3D interposer system dimensions Coaxial TPV Diameter Tantalum Liner Thickness Ultra-thin Core Thickness Interposer/Package size PWB size BGA pitch
Package Lateral PCB BGA P/GTrace Trace Vias Balls Length Length
PCB Traces
30µm 3µm
Glass
Polymer
17.5µm 30 µm
49.92µm 71µm
180µm
Figure 4: Co-axial Via Dimensions considered in this Study - 40nm tantalum oxide liner with (a) 30m Glass thickness (b) 100m thickness, 15m polymer liner with (c) 30m glass thickness Table 2: Summary of coaxial via capacitance Liner Glass Theoretical Q3D (pF) 𝜀 Thickness material Value (pF) (µm) 12.7 30 12.4 Tantalum 25 Oxide 120 100 117 Polymer
3.01
30
0.0117
0.018
Table 3: Summary of coaxial via loop inductance Glass Outer Inner Q3D Theoretical Thickness Radius Radius Value (pH) (pH) (µm) (µm) (µm) 30 10 9.96 0.028 0.022 100 25 24.96 0.042 0.032 30 25 15 3.63 4.7 (polymer) Considering current technology and future miniaturization, three coaxial TPV physical configurations are chosen as shown in Figure 4. Two variations of total TPV height (71 µm and 180 µm) in ultra-thin glass substrates (including dielectric and glass sections) is considered with both moderate-K(Tantalum oxide) and polymer liner configurations. The target metallization thickness was defined to be 5 µm.
542
From literature, simplified analytical expressions for capacitance and loop inductance per unit length of a coaxial via can be given as 2𝜋𝜀0 𝜀𝑟
μ
𝐷 𝑙𝑛( ) 𝑑
𝐿𝐿 = 2π ln(𝐷/𝑑)
(c) 25µm Polymer TPV
F/m H/m
Mag (Z11)
𝐶𝐿 =
decoupling at lower frequencies, enabling selective tuning to meet target impedance.
𝐷 is the outer via radius 𝑑 is the radius of the inner via 𝜀0 , 𝜀𝑟 is the permittivity of free space and TPV liner
P G
(a) 30µm TPV
(b) 100µm TPV
µ is the permeability
Table 2 presents a summary of various capacitance values that are extracted for coaxial vias. As expected, it can be seen that the maximum value of capacitance is achieved with the 100m glass via having the tantalum liner due to the highest capacitance density and surface area. Table 3 details the loop inductance of coaxial TPVs. It can be seen that the loop inductance of the p/g via is extremely small due to the thin coaxial liner, when compared with the loop inductance of a polymer based coaxial TPV. These results indicate useful PDN applications with the proposed P/G TPV configurations. Based on the extracted values, a simplified equivalent circuit model for glass TPVs was constructed as shown in Figure 5. It can be seen that the dominant capacitance is from the thin high-K liner material that is separated by the power and ground conductors, and has a theoretical value in several tens of pico farads. Power Top
Frequency (Hz)
Figure 6: Self-Impedance profile of single P/G coaxial via III. POWER-GROUND TPV: MATERIALS AND PROCESSES 3D interposers need to support low impedance powerground coaxial TPVs for efficient power supply. Based on the simulations shown in the previous section, the power-ground needs a capacitance in the order of 50-100 pF per via. This section deals with a discussion on various dielectric options, selection of the front-up materials, and an initial process demonstration for the TPV capacitors in 3D glass interposers. Table 4: Dielectric options for TPV capacitors in 3D interposers, and their merits and demerits
Ground Top C
Dielectric
GDielectric R
Outer
L
R C G
Outer
Film properties
Oxides Oxynitrides
7 t = 20 nm 2.5 nF/mm2
Moderate K paraelectrics -Tantalum oxide High K super paraelectrics - BST
t = 40 nm 5 nF/mm2
Inner
Liner
Liner
L
Inner
C
Dielectric
GDielectric Power Bottom
Dielectrics
Ground Bottom
Figure 5: Circuit model for Coaxial P/G Glass TPVs The impedance profile between the power and ground vias of a single coaxial TPV from different configurations was simulated using a full wave EM solver (HFSS) as shown in Figure 6. The self-impedance is measured between via pads of the top two metal layers as shown. It was seen that lowest impedance was observed with 100µm coaxial TPV due to its large surface area and length of the capacitor, followed by the ultra-thin 30 µm TPV. The impedance of polymer based coaxial vias were several orders higher than the other configurations, with smaller capacitive values due to larger separation between the metal plates. The effective capacitance of coaxial vias can be increased by connecting a number of the coaxial P/G vias in parallel, similar to the configuration present in interposer applications. The higher capacitance vias exhibit
High K ferroelectrics - Barium titanate
t = 150 nm 15-20 nF/mm2 t = 1 µm 30 nF/mm2
Merits High BDV allows 30 nm films Standard semiconduct or tools Simpler processing compared to high K films Dielectric constant low but stable with lower loss High density
Demerits Expensive semiconductor tools, Lower capacitance densities;
Moderate capacitance densities
Conformal dielectric is a challenge with standard processes
Higher temperature processing, Lower reliability and leakage, Conformal dielectric is a challenge with standard processes
Dielectric options Low k films: In silicon trench and TSV capacitors, oxides, nitrides and oxynitrides of silicon with permittivies of 5-7 are widely used. The Breakdown Voltages (BDVs) of these films range from 0.8-1 V/nm which represent the highest BDV of all materials. Even a 20 nm film can stand voltage of 15 V.
543
Furthermore, these materials present minimal reliability concerns because of their intrinsic structure and properties. This leads to a planar capacitance density of about 2-3 nF/mm2. Moreover, these technologies are dependent on very standard front-end semiconductor tools such as Plasma Enhanced Chemical Vapor Deposition (PECVD), Liquid Phase Chemical Vapor Deposition (LPCVD). The deposition temperatures are less than 300 C, and no issues of adhesion and thermomechanical compatibility arise because of their strong covalent bonding to the electrode and good CTE match with glass. However, higher capacitance densities with low-cost panel processes are sought for 3D glass interposers. Moderate k films: Oxides of tantalum, hafnium, zirconia, titania etc. show permittivities of 15-80. Some of these have breakdown strengths of 500-800 V/micron. They can be deposited thinner down to 30-50 nm showing capacitance densities approaching 5-10 nF/mm2. Moderate k films represent 2-3 X improvement in capacitance density compared to traditional oxides and nitrides. The most common technique for depositing these thin films in trenches is Atomic Layer Deposition (ALD), which also has cost and through-put limitations. High k films: Ferroelectrics show permittivities of 10005000 in 1-3 micron thickness, with a capacitance density of about 30 nF/mm2. Films with these properties require extremely high temperature processes (~1000 oC). The permittivity reduces dramatically for thinner films, and therefore the capacitance density does not improve much. With glass TPV-compatible processes (
