Conduction instability of amorphous InGaZnO thin ... - Semantic Scholar
Microelectronics Reliability 54 (2014) 2164–2166
Contents lists available at ScienceDirect
Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel
Conduction instability of amorphous InGaZnO thin-film transistors under constant drain current stress Jung Han Kang, Edward Namkyu Cho, Ilgu Yun ⇑ School of Electrical and Electronic Engineering, Yonsei University, Seoul 120-749, Republic of Korea
a r t i c l e
i n f o
Article history: Received 28 June 2014 Accepted 8 July 2014 Available online 10 August 2014 Keywords: InGaZnO Thin-film transistors Current stress Off current
a b s t r a c t Conduction characteristics of amorphous InGaZnO thin-film transistors were investigated by applying constant drain current with gate bias (VGS) modulation. Constant drain current in the off-current (Ioff) level from the transfer characteristic was applied to the drain electrode and the measured drain voltage with the gate bias sweep. The normalized channel conductance (Gd) characteristics were extracted from transfer characteristics and the gate bias modulated drain voltage characteristics with constant drain current stress were compared with the characteristics. The drain voltage induced by the constant drain current stress showed simultaneous transition from off-state with generation current dominant region with increasing drain bias (VDS) to the turn-on state. The high electric field at the drain electrode edge was observed at the threshold voltage (VTH), which can affect the instability characteristics of TFTs. Ó 2014 Elsevier Ltd. All rights reserved.
1. Introduction Amorphous InGaZnO (a-IGZO) thin-film transistor (TFT) is one of the prospective alternatives for future displays due to its high mobility (>10 cm2/Vs), low-temperature processing capability, and large area uniformity [1]. Recently, the research concerning a-IGZO TFTs is focused on the practical issues of TFTs, such as positive and negative bias-temperature instability (PBTI/NBTI), light illumination, and constant current stress or characteristic improvement [2–4]. However, constant current instability issues were rarely reported [5–7]. Unlike the studies made extensively on the constant current as a stress condition, very little attention was given to the role of a constant current stress dependent instability characteristic, especially the off-current (Ioff) injection with a variation of the channel states. The purpose of this study is to investigate the conduction characteristics of constant drain current stress. The gate bias dependent channel conductance (Gd) characteristic under constant drain current stress is analyzed and compared with the typical transfer characteristic. By applying the constant drain current to the drain electrode in the range of Ioff level, the gate bias (VGS) induced drain voltage (VDS) is measured. Based on the measurement data, the metal–semiconductor-metal (MSM) structure based analysis is performed on the TFT conduction characteristics [8]. Especially, the large electric field at the ⇑ Corresponding author. Address: A225, Eng. Bldg A, Yonsei University, Seoul 120-749, Republic of Korea. Tel.: +82 (2) 2123 4619; fax: +82 (2) 313 2879. E-mail address: [email protected] (I. Yun). http://dx.doi.org/10.1016/j.microrel.2014.07.066 0026-2714/Ó 2014 Elsevier Ltd. All rights reserved.
drain electrode edge with IDS_inj of Ioff level is observed. From the result, the instability of a-IGZO TFTs can be examined by using the induced Ioff to the drain electrode. 2. Fabrication and measurements In this work, a-IGZO TFTs of a conventional inverted staggered bottom gate structure with etch-stop layer (ESL) was fabricated on a glass substrate [9]. The 500-nm-thick SiNx insulator was deposited on a 250-nm Mo bottom gate using plasma enhanced chemical vapor deposition (PECVD) technique. The 50 nm-thick a-IGZO channel was then sputtered on the insulator using a polycrystalline In2Ga2ZnO7 (In2O3:Ga2O3:ZnO = 1:1:1 mol%) target. Finally, Mo source/drain electrodes were formed on the ESL by photolithography and wet etching. The channel width (W) and length (L) of test structure was 100 lm and 50 lm, respectively (see Fig. 1). The current–voltage (I–V) characteristic of a typical transfer curve was measured to extract electrical properties of test structure, such as the off-current (Ioff), the threshold voltage (VTH), the field-effect mobility (lFE), the subthreshold swing (SS), and the density of states (DOS) parameters. The parameters used in the modeling of the transfer characteristics were extracted using Silvaco ATLAS device simulator [10]. The drain voltage (VDS) was then measured by applying a constant stress current to the drain electrode (IDS_inj) with source grounded in the range of Ioff ( VGS–VTH). The
J.H. Kang et al. / Microelectronics Reliability 54 (2014) 2164–2166
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where kT/q is a thermal voltage, Nbulk and Nit are the density of deep bulk state and defects at the insulator and channel interface, respectively. The carrier concentration (Nch) of the IGZO channel was calculated as 5.24 1016 cm3 using the Eq. (4) [14]:
Nch ¼ C ins V ON =q t ch
ð4Þ
where tch and VON are the channel thickness and turn-on voltage, respectively. In order to characterize VGS dependent band structure characteristics, DOS characteristics of transfer curve at VDS = 0.1 V was modeled by using the Eq. (5) [15]:
" 2 # ðEC EÞ E0 E þ NGA exp gðEÞ ¼ NTA exp W TA W GA
Fig. 1. Schematic diagram of the test structure.
compliance voltage of VDS was set to 80 V to avoid IDS_inj induced hard breakdown (HBD) [11]. The electrical characteristics were measured at room temperature using Keithley 236 source measurement units (SMUs). 3. Results and discussion Fig. 2 shows transfer characteristics of the test structure with the VDS variation. The figure-of-merits or characteristics parameters, such as VTH, lFE, and SS, of transfer curve with VDS = 0.1 V assuming low field operation regime (VDS (VGS–VTH)) were extracted for the initial values of the TCAD simulation parameters. Here, VTH was extracted using linear extrapolation technique as 3.45 V [12]. lFE was calculated as 12.52 cm2/Vs using the Eq. (1) [12]:
lFE ¼
gm C ins W=L V DS
ð1Þ
where Cins, gm, and W/L are insulator unit area capacitance, transconductance, and channel aspect ratio, respectively. SS was also extracted as 0.46 V/dec from the Eq. (2) [12]:
SS ¼ ðd logðIDS Þ=dV GS Þ
1
ð2Þ
Thus, the estimated total density of the interface trap states of bulk/insulator interface was estimated to be 3.31 1011 eV1 cm2 from the Eq. (3) [12,13]:
Nt ¼ Nbulk þ N it ¼
S logðeÞ C ins 1 kT=q q
ð3Þ
Fig. 2. Linear and log scale transfer characteristics of a-IGZO TFT with VDS variation and the simulation result of VDS = 0.1 V (W/L = 100/50 lm).
ð5Þ
where NTA, EC, WTA, E0, NGA, and WGA are the trap energy, the conduction band (CB) intercept density, the CB energy, the characteristic decay energy of the tail states, the central energy, the density at the central energy of Gaussian distribution (GD), and the characteristic decay energy of GD, respectively. The extracted DOS parameters, NTA, WTA, NGA, and WGA, of transfer characteristics were 5.12 1017 cm3 eV1, 0.18, 1 1015 cm3 eV1, and 3.61, respectively. Fig. 3 shows VDS–VGS characteristics with varying IDS_inj = 225, 400, and 500 pA. It is observed that VDS showed transition from the VGS dependent increasing region (region I) to the decreasing in low drain voltage region (region II) as shown in the Fig. 3 at VGS = 3 V. Here, VDS increases in the low VGS region due to the IDS_inj induced depletion voltage at the drain electrode. Thus, the level of VDS was positively dependent on the IDS_inj. Based on the source–channel–drain region as MSM structure, [IDS_inj – sqrt(VDS)] below VGS = 3.2 V in the Fig. 4 can be linearly fitted to the trapassisted thermal generation current (Jgen) versus Schottky diode reverse bias (VR,Schottky), which has the relationship of the Eq. (6) as discussed in [16]:
J gen
sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi V R;Schottky 1þ / V bi
ð6Þ
Thus, based on the results, the conduction mechanism in this region can be characterized as the trap-assisted thermal generation current [17]. To compare conduction characteristics of VDS–VGS in the Fig. 3 with transfer characteristics, the normalized conductance (Gd) of transfer and VDS–VGS with IDS_inj characteristics were extracted by the Eq. (7) [12]:
Fig. 3. VDS vs. VGS characteristics with constant IDS_inj variation.
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Fig. 4. VDS vs. IDS_inj characteristics with VGS variation. Fig. 6. Electric field profiles at the drain electrode with the lateral (left) and depth (right) direction. (Here, VDS at VGS VTH from Fig. 3 was used.)
Gd ¼
ID ¼ lFE C ins ðV GS V TH Þ V DS W=L
ð7Þ
The Gd characteristics of VGS–VDS with IDS_inj showed the switching characteristics at VGS VTH, which were extracted from the transfer characteristics with VDS = 0.1 V as shown in the Fig. 5. The VDS at the VGS = 3 V in the Fig. 3 was raised from 21.39 V to 36.86 V as IDS_inj increased. The electric field with the peak VDS values in the Fig. 3 showed considerably high at the drain electrode edge as shown in the Fig. 6. Thus, the electron concentration near the drain electrode was increased. In addition, the filled states were increased and the carriers were accumulated at the bulk/insulator interface, the channel began to start forming a current path as the gate bias increased to the VGS VTH. As a result, the incident channel conduction through the channel to the drain electrode edge with high electric field at the drain electrode showed simultaneous switching characteristics. Therefore, VTH was observed at the location of the switching voltage (VGS = 3 V). The switching voltage showed an insignificant change with IDS_inj variation and Gd of VDS–VGS with IDS_inj showed similar characteristics and converged to the Gd of transfer curves as VGS was increased. It was indicated that the transport of IDS_inj at the high VGS converges to the conduction characteristics of the typical transfer curves [18]. The switching voltage dependence on IDS_inj and the difference of Gd characteristics at VGS > VTH can be originated from
Fig. 5. Linear and log scale channel conductance (Gd) characteristics extracted from the transfer and IDS_inj–VDS curves.
the charge injection associated with the electric field build-up for the current path generation, which will be further investigated in near future. 4. Conclusion In this paper, the channel conductance characteristics with constant drain current stress (IDS_inj) in the range of off-current (Ioff) level has been investigated. The gate bias dependent IDS_inj-VDS characteristics with IDS_inj variation (IDS_inj = 225, 400, and 500 pA) were measured. VDS was increased with raised VGS below VTH according to the depletion voltage at the interface of a-IGZO bulk and the drain electrode. The conduction current under VTH region showed the trap-assisted thermal generation current (Jgen) characteristics. In addition, the simultaneous switching characteristics were observed at the threshold voltage due to the high electric field induced current path through the drain electrode edge. Therefore, it can be concluded that Ioff can be a reason for TFT instability and verified from the constant drain current of Ioff level induced VDS characteristics around VTH. References [1] Kamiya T, Nomura K, Hosono H. Sci Technol Adv Mater 2010;11:044305. [2] Kwon JY, Lee DJ, Kim KB. Electron Mater Lett 2011;7:1–11. [3] Hoshino K, Hong D, Chiang H, Wager J. IEEE Trans Electron Dev 2009;56:1365–70. [4] Moon YK, Lee S, Kim WS, Kang BW, Jeong CO, Lee DH, et al. Appl Phys Lett 2009;95:013507. [5] Cheong WS, Shin JH, Chung SM, Hwang CS, Lee JM, Lee JH. J Nanosci Nanotechnol 2012;12:3421–4. [6] Nomura K, Kamiya T, Kikuchi Y, Hirano M, Hosono H. Thin Solid Films 2009;518:3012–6. [7] Kang JH, Cho EN, Yun I. SSDM 2010, Tokyo, Japan; 2010. [8] Takagi A, Nomura K, Ohta H, Yanagi H, Kamiya T, Hirano M, et al. Thin Solid Films 2005;486:38–41. [9] Kim M, Jeong JH, Lee HJ, Ahn TK, Shin HS, Park JS, et al. Appl Phys Lett 2007;90:212114. [10] ATLAS user’s manual. Santa Clara, CA: Silvaco International; 2008. [11] Pompl T, Engel C, Wurzer H, Kerber M. Microelectro Reliab 2001;41:543–51. [12] Kagan CR, Andry P. Thin-film transistors 2003. New York: Marcel Dekker Inc.; 2003. [13] Jeong JK, Jeong JH, Yang HW, Park JS, Mo YG, Kim HD. Appl Phys Lett 2007;91:113505. [14] Sze SM. Physics of semiconductor devices 1981. New York: Wiley; 1981. [15] Hsieh HH, Kamiya T, Nomura K, Hosono H, Wu CC. Appl Phys Lett 2008;92. [16] Lee S, Park JH, Jeon K, Kim S, Jeon Y, Kim DH, et al. Appl Phys Lett 2010;96:113506. [17] Bae M, Kim Y, Kim S, Kim DM, Kim DH. IEEE Elec Dev Lett 2011;32:1248–50. [18] Nomura K, Kamiya T, Ohta H, Ueda K, Hirano M, Hosono H. Appl Phys Lett 2004;85:1993.
Contents lists available at ScienceDirect
Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel
Conduction instability of amorphous InGaZnO thin-film transistors under constant drain current stress Jung Han Kang, Edward Namkyu Cho, Ilgu Yun ⇑ School of Electrical and Electronic Engineering, Yonsei University, Seoul 120-749, Republic of Korea
a r t i c l e
i n f o
Article history: Received 28 June 2014 Accepted 8 July 2014 Available online 10 August 2014 Keywords: InGaZnO Thin-film transistors Current stress Off current
a b s t r a c t Conduction characteristics of amorphous InGaZnO thin-film transistors were investigated by applying constant drain current with gate bias (VGS) modulation. Constant drain current in the off-current (Ioff) level from the transfer characteristic was applied to the drain electrode and the measured drain voltage with the gate bias sweep. The normalized channel conductance (Gd) characteristics were extracted from transfer characteristics and the gate bias modulated drain voltage characteristics with constant drain current stress were compared with the characteristics. The drain voltage induced by the constant drain current stress showed simultaneous transition from off-state with generation current dominant region with increasing drain bias (VDS) to the turn-on state. The high electric field at the drain electrode edge was observed at the threshold voltage (VTH), which can affect the instability characteristics of TFTs. Ó 2014 Elsevier Ltd. All rights reserved.
1. Introduction Amorphous InGaZnO (a-IGZO) thin-film transistor (TFT) is one of the prospective alternatives for future displays due to its high mobility (>10 cm2/Vs), low-temperature processing capability, and large area uniformity [1]. Recently, the research concerning a-IGZO TFTs is focused on the practical issues of TFTs, such as positive and negative bias-temperature instability (PBTI/NBTI), light illumination, and constant current stress or characteristic improvement [2–4]. However, constant current instability issues were rarely reported [5–7]. Unlike the studies made extensively on the constant current as a stress condition, very little attention was given to the role of a constant current stress dependent instability characteristic, especially the off-current (Ioff) injection with a variation of the channel states. The purpose of this study is to investigate the conduction characteristics of constant drain current stress. The gate bias dependent channel conductance (Gd) characteristic under constant drain current stress is analyzed and compared with the typical transfer characteristic. By applying the constant drain current to the drain electrode in the range of Ioff level, the gate bias (VGS) induced drain voltage (VDS) is measured. Based on the measurement data, the metal–semiconductor-metal (MSM) structure based analysis is performed on the TFT conduction characteristics [8]. Especially, the large electric field at the ⇑ Corresponding author. Address: A225, Eng. Bldg A, Yonsei University, Seoul 120-749, Republic of Korea. Tel.: +82 (2) 2123 4619; fax: +82 (2) 313 2879. E-mail address: [email protected] (I. Yun). http://dx.doi.org/10.1016/j.microrel.2014.07.066 0026-2714/Ó 2014 Elsevier Ltd. All rights reserved.
drain electrode edge with IDS_inj of Ioff level is observed. From the result, the instability of a-IGZO TFTs can be examined by using the induced Ioff to the drain electrode. 2. Fabrication and measurements In this work, a-IGZO TFTs of a conventional inverted staggered bottom gate structure with etch-stop layer (ESL) was fabricated on a glass substrate [9]. The 500-nm-thick SiNx insulator was deposited on a 250-nm Mo bottom gate using plasma enhanced chemical vapor deposition (PECVD) technique. The 50 nm-thick a-IGZO channel was then sputtered on the insulator using a polycrystalline In2Ga2ZnO7 (In2O3:Ga2O3:ZnO = 1:1:1 mol%) target. Finally, Mo source/drain electrodes were formed on the ESL by photolithography and wet etching. The channel width (W) and length (L) of test structure was 100 lm and 50 lm, respectively (see Fig. 1). The current–voltage (I–V) characteristic of a typical transfer curve was measured to extract electrical properties of test structure, such as the off-current (Ioff), the threshold voltage (VTH), the field-effect mobility (lFE), the subthreshold swing (SS), and the density of states (DOS) parameters. The parameters used in the modeling of the transfer characteristics were extracted using Silvaco ATLAS device simulator [10]. The drain voltage (VDS) was then measured by applying a constant stress current to the drain electrode (IDS_inj) with source grounded in the range of Ioff ( VGS–VTH). The
J.H. Kang et al. / Microelectronics Reliability 54 (2014) 2164–2166
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where kT/q is a thermal voltage, Nbulk and Nit are the density of deep bulk state and defects at the insulator and channel interface, respectively. The carrier concentration (Nch) of the IGZO channel was calculated as 5.24 1016 cm3 using the Eq. (4) [14]:
Nch ¼ C ins V ON =q t ch
ð4Þ
where tch and VON are the channel thickness and turn-on voltage, respectively. In order to characterize VGS dependent band structure characteristics, DOS characteristics of transfer curve at VDS = 0.1 V was modeled by using the Eq. (5) [15]:
" 2 # ðEC EÞ E0 E þ NGA exp gðEÞ ¼ NTA exp W TA W GA
Fig. 1. Schematic diagram of the test structure.
compliance voltage of VDS was set to 80 V to avoid IDS_inj induced hard breakdown (HBD) [11]. The electrical characteristics were measured at room temperature using Keithley 236 source measurement units (SMUs). 3. Results and discussion Fig. 2 shows transfer characteristics of the test structure with the VDS variation. The figure-of-merits or characteristics parameters, such as VTH, lFE, and SS, of transfer curve with VDS = 0.1 V assuming low field operation regime (VDS (VGS–VTH)) were extracted for the initial values of the TCAD simulation parameters. Here, VTH was extracted using linear extrapolation technique as 3.45 V [12]. lFE was calculated as 12.52 cm2/Vs using the Eq. (1) [12]:
lFE ¼
gm C ins W=L V DS
ð1Þ
where Cins, gm, and W/L are insulator unit area capacitance, transconductance, and channel aspect ratio, respectively. SS was also extracted as 0.46 V/dec from the Eq. (2) [12]:
SS ¼ ðd logðIDS Þ=dV GS Þ
1
ð2Þ
Thus, the estimated total density of the interface trap states of bulk/insulator interface was estimated to be 3.31 1011 eV1 cm2 from the Eq. (3) [12,13]:
Nt ¼ Nbulk þ N it ¼
S logðeÞ C ins 1 kT=q q
ð3Þ
Fig. 2. Linear and log scale transfer characteristics of a-IGZO TFT with VDS variation and the simulation result of VDS = 0.1 V (W/L = 100/50 lm).
ð5Þ
where NTA, EC, WTA, E0, NGA, and WGA are the trap energy, the conduction band (CB) intercept density, the CB energy, the characteristic decay energy of the tail states, the central energy, the density at the central energy of Gaussian distribution (GD), and the characteristic decay energy of GD, respectively. The extracted DOS parameters, NTA, WTA, NGA, and WGA, of transfer characteristics were 5.12 1017 cm3 eV1, 0.18, 1 1015 cm3 eV1, and 3.61, respectively. Fig. 3 shows VDS–VGS characteristics with varying IDS_inj = 225, 400, and 500 pA. It is observed that VDS showed transition from the VGS dependent increasing region (region I) to the decreasing in low drain voltage region (region II) as shown in the Fig. 3 at VGS = 3 V. Here, VDS increases in the low VGS region due to the IDS_inj induced depletion voltage at the drain electrode. Thus, the level of VDS was positively dependent on the IDS_inj. Based on the source–channel–drain region as MSM structure, [IDS_inj – sqrt(VDS)] below VGS = 3.2 V in the Fig. 4 can be linearly fitted to the trapassisted thermal generation current (Jgen) versus Schottky diode reverse bias (VR,Schottky), which has the relationship of the Eq. (6) as discussed in [16]:
J gen
sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi V R;Schottky 1þ / V bi
ð6Þ
Thus, based on the results, the conduction mechanism in this region can be characterized as the trap-assisted thermal generation current [17]. To compare conduction characteristics of VDS–VGS in the Fig. 3 with transfer characteristics, the normalized conductance (Gd) of transfer and VDS–VGS with IDS_inj characteristics were extracted by the Eq. (7) [12]:
Fig. 3. VDS vs. VGS characteristics with constant IDS_inj variation.
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Fig. 4. VDS vs. IDS_inj characteristics with VGS variation. Fig. 6. Electric field profiles at the drain electrode with the lateral (left) and depth (right) direction. (Here, VDS at VGS VTH from Fig. 3 was used.)
Gd ¼
ID ¼ lFE C ins ðV GS V TH Þ V DS W=L
ð7Þ
The Gd characteristics of VGS–VDS with IDS_inj showed the switching characteristics at VGS VTH, which were extracted from the transfer characteristics with VDS = 0.1 V as shown in the Fig. 5. The VDS at the VGS = 3 V in the Fig. 3 was raised from 21.39 V to 36.86 V as IDS_inj increased. The electric field with the peak VDS values in the Fig. 3 showed considerably high at the drain electrode edge as shown in the Fig. 6. Thus, the electron concentration near the drain electrode was increased. In addition, the filled states were increased and the carriers were accumulated at the bulk/insulator interface, the channel began to start forming a current path as the gate bias increased to the VGS VTH. As a result, the incident channel conduction through the channel to the drain electrode edge with high electric field at the drain electrode showed simultaneous switching characteristics. Therefore, VTH was observed at the location of the switching voltage (VGS = 3 V). The switching voltage showed an insignificant change with IDS_inj variation and Gd of VDS–VGS with IDS_inj showed similar characteristics and converged to the Gd of transfer curves as VGS was increased. It was indicated that the transport of IDS_inj at the high VGS converges to the conduction characteristics of the typical transfer curves [18]. The switching voltage dependence on IDS_inj and the difference of Gd characteristics at VGS > VTH can be originated from
Fig. 5. Linear and log scale channel conductance (Gd) characteristics extracted from the transfer and IDS_inj–VDS curves.
the charge injection associated with the electric field build-up for the current path generation, which will be further investigated in near future. 4. Conclusion In this paper, the channel conductance characteristics with constant drain current stress (IDS_inj) in the range of off-current (Ioff) level has been investigated. The gate bias dependent IDS_inj-VDS characteristics with IDS_inj variation (IDS_inj = 225, 400, and 500 pA) were measured. VDS was increased with raised VGS below VTH according to the depletion voltage at the interface of a-IGZO bulk and the drain electrode. The conduction current under VTH region showed the trap-assisted thermal generation current (Jgen) characteristics. In addition, the simultaneous switching characteristics were observed at the threshold voltage due to the high electric field induced current path through the drain electrode edge. Therefore, it can be concluded that Ioff can be a reason for TFT instability and verified from the constant drain current of Ioff level induced VDS characteristics around VTH. References [1] Kamiya T, Nomura K, Hosono H. Sci Technol Adv Mater 2010;11:044305. [2] Kwon JY, Lee DJ, Kim KB. Electron Mater Lett 2011;7:1–11. [3] Hoshino K, Hong D, Chiang H, Wager J. IEEE Trans Electron Dev 2009;56:1365–70. [4] Moon YK, Lee S, Kim WS, Kang BW, Jeong CO, Lee DH, et al. Appl Phys Lett 2009;95:013507. [5] Cheong WS, Shin JH, Chung SM, Hwang CS, Lee JM, Lee JH. J Nanosci Nanotechnol 2012;12:3421–4. [6] Nomura K, Kamiya T, Kikuchi Y, Hirano M, Hosono H. Thin Solid Films 2009;518:3012–6. [7] Kang JH, Cho EN, Yun I. SSDM 2010, Tokyo, Japan; 2010. [8] Takagi A, Nomura K, Ohta H, Yanagi H, Kamiya T, Hirano M, et al. Thin Solid Films 2005;486:38–41. [9] Kim M, Jeong JH, Lee HJ, Ahn TK, Shin HS, Park JS, et al. Appl Phys Lett 2007;90:212114. [10] ATLAS user’s manual. Santa Clara, CA: Silvaco International; 2008. [11] Pompl T, Engel C, Wurzer H, Kerber M. Microelectro Reliab 2001;41:543–51. [12] Kagan CR, Andry P. Thin-film transistors 2003. New York: Marcel Dekker Inc.; 2003. [13] Jeong JK, Jeong JH, Yang HW, Park JS, Mo YG, Kim HD. Appl Phys Lett 2007;91:113505. [14] Sze SM. Physics of semiconductor devices 1981. New York: Wiley; 1981. [15] Hsieh HH, Kamiya T, Nomura K, Hosono H, Wu CC. Appl Phys Lett 2008;92. [16] Lee S, Park JH, Jeon K, Kim S, Jeon Y, Kim DH, et al. Appl Phys Lett 2010;96:113506. [17] Bae M, Kim Y, Kim S, Kim DM, Kim DH. IEEE Elec Dev Lett 2011;32:1248–50. [18] Nomura K, Kamiya T, Ohta H, Ueda K, Hirano M, Hosono H. Appl Phys Lett 2004;85:1993.
