Equivalent design representations and transformations ... - IEEE Xplore
Equivalent Design Representations and Transformations for Interactive Scheduling Nikil D. Dutt
Roger P. Ang
Department of Information and Computer Science University of California, Irvine, CA 92717 Abstract
or make assumptions about design characteristics that are dealt with by other tools. Without information sharing, automatic tools are limited in their effectiveness and an experienced designer is at an advantage. The incompatibility of representations is also an obstacle in creating an interactive HLS environment that will allow a designer to manually guide synthesis tools and see their impact on the design. To overcome this problem, equivalent representations are needed that facilitate the various HLS tasks and have consistent semantics. Also, behavior-preserving transformations are needed to perform the various HLS tasks with well-defined mappings from one representation to another. For this paper, we view the HLS task of scheduling as the mapping of a CDFG model of a design to an FSM model that has clocked states. For interactive scheduling, we need a model that captures the control/data flow of the design as defined by the CDFG, and the temporal ordering defined by the FSM. We present a finite state machine model, the SFSM, for representing a scheduled CDFG. This model facilitates the use of primitive, behavior-preserving transformations for scheduling, as well as the construction of equivalent CDFG and FSM models. This model will enable use of various analysis techniques and optimizations used with either flow graphs or FSMs, such as variable lifetime analysis and state minimization. This paper is organized as follows: Section 2 describes the design models used for scheduling, Section 3 outlines the rescheduling transformations, Section 4 relates our work to similar efforts, Section 5 describes the status of this work, and Section 6 concludes with a summary.
High-level synthesis (HLS) requires more designer interaction to better meet the needs of experienced designers. However, attempts to create a highly interactive synthesis process are hampered by incompatibility of various representations used during synthesis. To overcome this problem, equivalent representations are needed, as well as equivalence-preserving synthesis transformations. W e present the Structured Finite State Machine (SFSM) design model for scheduled behavior, show its equivalence to the Control/Data Flow Graph (CDFG) model, and define primitive behavior-preserving transformations for scheduling. W e have integrated this model and these transjormations into the BIF interactive environment to enable manual rescheduling of a design.
1 Introduction Traditionally, high-level synthesis (HLS) has been an automatic process over which the user has had little or no control [8]. While automatic synthesis tools have shown great promise, these tools cannot produce designs of the same quality as those of an experienced designer. An automatic tool often only deals with a single synthesis task or a particular architectural style, which limits the effectiveness of a single tool when compared to the global view and design knowledge of an experienced designer. Further, automatic tools typically are each based on different, non-equivalent design models, thus preventing feedback between a wide variety of synthesis tools. To improve the quality of designs produced using HLS, more interactivity between the designer and tools is needed. A problem in information exchange between synthesis tools is that each tool often works on a design representation that is different from that used by other tools. For example, a Control/Data Flow Graph (CDFG) model is often chosen for the initial compilation of a design specification written in a hardware description language (HDL), while a finite state machine (FSM) model is favored for control logic generation and optimization. Intrinsically, an FSM has more expressive power than a CDFG since the FSM is not limited to the well-structured constructs required of a CDFG. Therefore, given an FSM, there may not be a corresponding CDFG. Because of this incompatibility, different synthesis tools are prevented from sharing information in an interactive manner. Thus, each tool must either ignore
2
2.1
Control Data Flow Graph (CDFG)
A behavioral description in a HDL is typically compiled into a variant of a CDFG [12], a representation that encapsulates information about the control flow through a design description as well as the data flow for assignments. We define CDFG (C, E, t, D, I, 0,0 ) to be a directed graph, where: C is a set of control flow nodes, E is a set of directed edges, t: C x D x I I+ E is a transition function, D is a set of data flow graphs, I is a set of design inputs,
332 0-81863010-8/92SCY3.00 0 1992 IEEE
Design Models
0 is a set of design outputs, and o : C x D x I I+ 0 is an output function. A control flow node c E C can be one of four types: Block: corresponds to a “basic block” of code. The data flow graphs associated with this node describe actions to be performed. Test: describes conditional branching. The data flow graph associated with this node describes a conditional branching expression. For our purposes, a conditional expression can only represent a logical expression or specify a variable which is tested for particular values. Join: complements the Test node. Loop: a special form of a conditional branching node indicating the entry/exit point of a cycle in the control flow graph. Exceptions to the above are the designated start node and an optional stop node. The start node may have no incoming edges, and the stop node has no outgoing edges. CDFGs possess important properties of well-structuredness that make various kinds of global data analyses practical:
Condition
(4 (b) Figure 1: (a) Scheduled CDFG (b) Corresponding SFSM. 2.3
Construction of an SFSM
An SFSM can be constructed from a scheduled CDFG in the following manner: For each Test, Join or Loop node in the CDFG, construct a corresponding state in the SFSM. For each Block node in the CDFG, construct a series of states in the SFSM. That is, for each state a CDFG Block is scheduled into, construct a corresponding SFSM state. In Figure 1, Block B 2 in the CDFG has been scheduled across three states and maps to three nodes in the SFSM. For each edge in the CDFG, a corresponding transition is constructed in the SFSM. Edges to and from CDFG Block nodes are special cases. An edge to a Block node is modeled as a transition to the first state of a series of Action states. An edge from a Block node is modeled as a transition from the last state of a series of Action states. From this construction, it is clear that the wellstructuredness properties for control flow nodes of a CDFG also apply to the states of an SFSM. A reverse construction can derive a CDFG from an SFSM description. These constructions demonstrate the equivalence of the scheduled CDFG and SFSM models. Note that while a scheduled CDFG can be modeled by an SFSM, a SFSM state is not semantically the same as a control step in the scheduled CDFG. In a scheduled CDFG, several control flow nodes can be assigned to the same control step. For example, it is possible in a CDFG that a Test node and portions of successor Block nodes are assigned to the same state. However, from an SFSM model, we can derive an FSMD with states that correspond to the states in the scheduled CDFG. The steps used for this construction are similar to rules used in scheduling a CDFG. The construction of an FSMD from an SFSM consists of two steps:
- Every Test node has a corresponding Join successor. - Test-Join pairs are properly nested. - A Loop node is the only entry and exit point for a cycle.
2.2
L--f----tt, L
/Test\
Structured FSM (SFSM)
We can represent a scheduled design by a FSM. FSMs are practical for logic and register-transfer synthesis, since well established synthesis techniques exist for them [4] [ll]. We use a form of FSM, the Structured Finite State Machine (SFSM), to bridge differences between the CDFG and finite state machine models. The SFSM model maintains the control flow structure of a scheduled CDFG within a finite state machine model. SFSMs are a subset of finite state machines with datapath (FSMD) [8]. FSMs can become unmanageable in size and complexity if the binary/Boolean encoding and transformation of data is explicitly described, e.g., describing the logical steps for performing multiplication of two 2’s complement 8-bit numbers. We can use data abstraction to elevate the level of description from the Boolean level to abstract data types such as integers. Briefly, FSMDs are finite state machines defined on the semantics of abstract variables to describe conditions for transitions, and transformations of inputs to outputs. We define FSMD (S, I U STAT,0 U A,f , h) , where S is a set of states, I is a set of inputs, STAT is a set of status signals, each a logical/relational expression, 0 is a set of outputs, A is a set of assignments, f : S x I U STAT I+ S is a transition function, and h : S x I U STAT I+ 0U A is an output function.
1. Merge Condition/Loop Test and A c t i o n states: Condition (or Loop Test) states with immediate successors that are Action states can be merged into a single state. 2. Eliminate Join s t a t u : Join states are artifacts of the original CDFG description. They can be eliminated by “skipping” them in the FSMD model.
An SFSM is astructured form of the FSMD (Figure lb). An SFSM can have four types of states: Action, Condition, Join, and Loop Test. The semantics and usage of SFSM constructs are best described in terms of the CDFG.
Consequently, given a SFSM model, a designer can derive both a CDFG and an FSMD model that are closely
333
related and behaviorally identical. It should be noted that translation t o an FSMD can constitute a “point of no return”, since further optimization of the FSMD may make it impossible t o generate an equivalent SFSM or CDFG. Several advantages arise from using both the CDFG and SFSM models. First, any changes made t o the SFSM can be correlated to the CDFG for further analysis. Second, since a scheduled CDFG and SFSM are behaviorally equivalent, we can translate between the two representations for tasks appropriate t o each model. Third, by using a hybrid of flow graphs and FSMs, we are able t o use both flow graph and FSM analysis techniques on the model.
3
there must be no intervening states between the Condition states or their corresponding Join states. The action movement transformations allow the re-ordering of actions t o alter design characteristics, e.g., so that fewer functional units are required. For action movement across a Condition/Join state, Action states must immediately precede and succeed the Condition/Join state.
4
The application of similar compiler optimizations to HLS has been done [15] [3] [5], but differ from this work in the design models and approach. Interactive use of similar transformations for retiming have been done by Potkonjak and Rabaey, and Malik et. al [13] [lo]. However, retiming differs from scheduling in the underlying data being transformed. While retiming tools allow changing the usage and number of registers in a circuit, they will not change the usage or number of operational units. Scheduling, in contrast, influences the usage and number of registers and operational units for a circuit synthesized from a transformed behavioral description. Leeser and Wolf describe transformations on an FSM model with similar effects as the transformations described here [9]. However, their system is based entirely on FSM models (BFSM and RTFSM). The structures in these models do not directly correspond t o one another or to the control flow of the original HDL description. Consequently, these models are not amenable to the interactive approach we are suggesting, where being able to represent a given change in all the models is highly desirable. Walker and Thomas have explored interactive transformation of behavioral descriptions similar to this work [16]. They have developed a system t o manipulate value trace (VT) representations derived from ISPS. Their system performs code motion and condition merging transformations similar to the transformations described in this paper. However, the V T representation is a data flow graph model variant. Unfortunately, data flow graphs are not amenable to some tasks such as state minimization or control analysis for resource sharing. For our work, we use a CDFG and have formulated the SFSM for the very reason that these models facilitate a wide range of synthesis tasks.
Transformations
Only a small set of transformations is needed to enable the rescheduling of a description while maintaining the behavior of the design. T h e transformations described here are targeted for the SFSM model. These transformation were chosen since they do not alter the well-structuredness of the design model. To preserve the functionality of the design, datadependencies between actions in the description must be maintained. For a data carrier, such as a variable, the functionality of that data carrier is preserved if the order in which its data is assigned and used is not altered. The concept of definition-use chaining (du-chaining) is used to maintain this ordering [l]. A transformation preserves the behavior of the design only if the result does not violate the ordering defined by the du-chains.
5
(c) Mwemell betwen M b n 8latm
Related Work
Status
The transformations described in this paper have been implemented in C on Sun workstations, and are currently working within the BIF design environment [7]. A graphical user interface, XBIF [6], allows the designer to interactively apply these transformations to a scheduled behavior represented as a BIF Operations-Based State Table. Figure 3 shows the application of a movement transformation t o the Fifth Order Digital Elliptic Filter benchmark. The initial schedule for this example was derived without considering register sharing. This design was manually rescheduled by the application of two movement transformations, and resulted in a decrease of 2 in the minimal number of registers required. Within the environment, an attempt t o apply a transformation incorrectly is aborted, and the user is notified via a message on the screen. Since different layout architectures may require different sched-
(d)kwemenl w x c a Condkim‘.bh state
Figure 2: Transformations These transformations are illustrated in Figure 2. The addition of an empty Action state allows flexibility in reordering the existing actions, while deletion of an empty Action state reduces the number of states with the goal of improving the design’s performance. The merging of conditions changes the control of the design such that the two condition tests are considered together in a single state rather than in two separate states. To merge conditions,
334
Figure 3: Transformation application via XBIF
T. Hadley, L. Ramachandran and E. Rundensteiner for
ules and allocations, the user can manually experiment with the rescheduling of operations to search for optimal implementations tuned to particular physical design models. We have also developed tools that translate between the CDFG and SFSM models. Thus far, this has enabled the use of an external tool, VSS [14], t o produce a scheduled CDFG from which an SFSM model is constructed in BIF. Our technical report contains detailed discussions of the transformations and models presented in this paper [2].
6
their help and input.
References [l] A. Aho, R. Sethi, J. Ullman, Compilers: Principles, Techniques and Tools, Addison-Wesley, 1986. [2] R. Ang and N. Dutt, “Transformations Supporting Interactive Rescheduling for High-Level Synthesis”, Tech. Report 92-20, University of California a t Irvine, Feb. 1992. [3] J. Bhasker and H. Lee, “An Optimizer for Hardware Synthesis,” IEEE Design and Test of Computers, pp. 20-36, Oct. 1990. [4] R. Brayton, et. al., “Multi-level Logic Synthesis,” Proceedings of the IEEE, Feb. 1990. [5] R. Camposano, “Behavior-Preserving Transformations for High-Level Synthesis”, LNCS 408, pp. 106-128, Springer Verlag, 1990. [SI N. Dutt, J. Cho, and T. Hadley, “A User Interfacefor VHDL Behavioral Modeling,” Proceedings of CHDL, 1991. [7] N. Dutt, T. Hadley and D. Gajski, “An Intermediate R e p resentation for Behavioral Synthesis,” Proceedings of DA C , pp.14-19, 1990. [8] D. Gajski, N. Dutt, A. Wu, S. Lin, High-Level Synthesis: Introduction t o Chip and System Design, Kluwer, 1992. [9] M. Leeser and W. Wolf, “Behavior FSMs for High-Level Verification and Synthesis,” A C M International Workshop on Formal Methods in VLSI Design, Jan., 1991. [lo] S. Malik et. al, “Retiming and Resynthesis: Optimizing Sequential Networks with Combinational Techniques.”, IEEE Trans. on C A D , pp. 74-84, Jan. 1991. [ll] P. Michel, U. Lauther and P. Duzy, The Synthesis Approach l o Digital System Design, Kluwer, 1992. [12] A. Orailoglu and D. Gajski, “Flow Graph Representation,” Proceedings of D A C , pp. 503-509, 1986. [13] M. Potkonjak and J. Rabaey, “Optimizing Resource Utilization using Transformations”, Proceedings of I C C A D , pp. 88-91, 1991. [14] L. Ramachandran and D. Gajski, “An Algorithm for Component Selection in Performance Optimized Scheduling,” Proceedings of I C C A D , pp. 92-96, 1991. [15] R. Walker and D.Thomas, “Behavioral Level Transformations in the CMU-DA System”, Proceedings of D A C , 1983. [16] R. Walker and D. Thomas, “Behavioral Transformation for Algorithmic Level IC Design”, IEEE Trans. on CAD, pp. 1115-1128, Oct., 1989.
Summary
Automatic schedulers may be limited in their effectiveness since they do not have information generated by subsequent synthesis tasks, or may not have knowledge of the target architecture. Also, they may not make intelligent decisions due t o the limitations of the design representation they use. To alleviate these shortcomings, a manual rescheduling capability is needed to permit designers to incorporate additional knowledge, such as floorplanning and layout information, early in the design process. In this paper, we defined a CDFG to represent behavior described in an imperative HDL. We then defined the SFSM, a well-structured, abstract FSM that is appropriate for capturing the scheduled behavior of a design. The SFSM was defined in terms of the CDFG by describing construction rules to go between these design models, thus showing the equivalence of the models. We explained the advantages of maintaining both design models, and showed that the SFSM, and hence the scheduled CDFG, is a subset of the FSMD design model used in high-level synthesis. We then outlined behavior preserving transformations suitable for scheduling in high-level synthesis. We have integrated these transformations into an interactive environment to allow manual rescheduling of a design compiled into an SFSM model. This is the first step towards an interactive HLS environment where a designer can perform various synthesis tasks simultaneously. Our current work has not dealt with timing specifications in the input behavior. Our future work will address these issues as well as focus on developing metrics to help designers apply these transformations effectively.
Acknowledgments This work was partially supported by NSF grant MIP9009239 and SRC contract 91-DJ-146. We also thank
335
Roger P. Ang
Department of Information and Computer Science University of California, Irvine, CA 92717 Abstract
or make assumptions about design characteristics that are dealt with by other tools. Without information sharing, automatic tools are limited in their effectiveness and an experienced designer is at an advantage. The incompatibility of representations is also an obstacle in creating an interactive HLS environment that will allow a designer to manually guide synthesis tools and see their impact on the design. To overcome this problem, equivalent representations are needed that facilitate the various HLS tasks and have consistent semantics. Also, behavior-preserving transformations are needed to perform the various HLS tasks with well-defined mappings from one representation to another. For this paper, we view the HLS task of scheduling as the mapping of a CDFG model of a design to an FSM model that has clocked states. For interactive scheduling, we need a model that captures the control/data flow of the design as defined by the CDFG, and the temporal ordering defined by the FSM. We present a finite state machine model, the SFSM, for representing a scheduled CDFG. This model facilitates the use of primitive, behavior-preserving transformations for scheduling, as well as the construction of equivalent CDFG and FSM models. This model will enable use of various analysis techniques and optimizations used with either flow graphs or FSMs, such as variable lifetime analysis and state minimization. This paper is organized as follows: Section 2 describes the design models used for scheduling, Section 3 outlines the rescheduling transformations, Section 4 relates our work to similar efforts, Section 5 describes the status of this work, and Section 6 concludes with a summary.
High-level synthesis (HLS) requires more designer interaction to better meet the needs of experienced designers. However, attempts to create a highly interactive synthesis process are hampered by incompatibility of various representations used during synthesis. To overcome this problem, equivalent representations are needed, as well as equivalence-preserving synthesis transformations. W e present the Structured Finite State Machine (SFSM) design model for scheduled behavior, show its equivalence to the Control/Data Flow Graph (CDFG) model, and define primitive behavior-preserving transformations for scheduling. W e have integrated this model and these transjormations into the BIF interactive environment to enable manual rescheduling of a design.
1 Introduction Traditionally, high-level synthesis (HLS) has been an automatic process over which the user has had little or no control [8]. While automatic synthesis tools have shown great promise, these tools cannot produce designs of the same quality as those of an experienced designer. An automatic tool often only deals with a single synthesis task or a particular architectural style, which limits the effectiveness of a single tool when compared to the global view and design knowledge of an experienced designer. Further, automatic tools typically are each based on different, non-equivalent design models, thus preventing feedback between a wide variety of synthesis tools. To improve the quality of designs produced using HLS, more interactivity between the designer and tools is needed. A problem in information exchange between synthesis tools is that each tool often works on a design representation that is different from that used by other tools. For example, a Control/Data Flow Graph (CDFG) model is often chosen for the initial compilation of a design specification written in a hardware description language (HDL), while a finite state machine (FSM) model is favored for control logic generation and optimization. Intrinsically, an FSM has more expressive power than a CDFG since the FSM is not limited to the well-structured constructs required of a CDFG. Therefore, given an FSM, there may not be a corresponding CDFG. Because of this incompatibility, different synthesis tools are prevented from sharing information in an interactive manner. Thus, each tool must either ignore
2
2.1
Control Data Flow Graph (CDFG)
A behavioral description in a HDL is typically compiled into a variant of a CDFG [12], a representation that encapsulates information about the control flow through a design description as well as the data flow for assignments. We define CDFG (C, E, t, D, I, 0,0 ) to be a directed graph, where: C is a set of control flow nodes, E is a set of directed edges, t: C x D x I I+ E is a transition function, D is a set of data flow graphs, I is a set of design inputs,
332 0-81863010-8/92SCY3.00 0 1992 IEEE
Design Models
0 is a set of design outputs, and o : C x D x I I+ 0 is an output function. A control flow node c E C can be one of four types: Block: corresponds to a “basic block” of code. The data flow graphs associated with this node describe actions to be performed. Test: describes conditional branching. The data flow graph associated with this node describes a conditional branching expression. For our purposes, a conditional expression can only represent a logical expression or specify a variable which is tested for particular values. Join: complements the Test node. Loop: a special form of a conditional branching node indicating the entry/exit point of a cycle in the control flow graph. Exceptions to the above are the designated start node and an optional stop node. The start node may have no incoming edges, and the stop node has no outgoing edges. CDFGs possess important properties of well-structuredness that make various kinds of global data analyses practical:
Condition
(4 (b) Figure 1: (a) Scheduled CDFG (b) Corresponding SFSM. 2.3
Construction of an SFSM
An SFSM can be constructed from a scheduled CDFG in the following manner: For each Test, Join or Loop node in the CDFG, construct a corresponding state in the SFSM. For each Block node in the CDFG, construct a series of states in the SFSM. That is, for each state a CDFG Block is scheduled into, construct a corresponding SFSM state. In Figure 1, Block B 2 in the CDFG has been scheduled across three states and maps to three nodes in the SFSM. For each edge in the CDFG, a corresponding transition is constructed in the SFSM. Edges to and from CDFG Block nodes are special cases. An edge to a Block node is modeled as a transition to the first state of a series of Action states. An edge from a Block node is modeled as a transition from the last state of a series of Action states. From this construction, it is clear that the wellstructuredness properties for control flow nodes of a CDFG also apply to the states of an SFSM. A reverse construction can derive a CDFG from an SFSM description. These constructions demonstrate the equivalence of the scheduled CDFG and SFSM models. Note that while a scheduled CDFG can be modeled by an SFSM, a SFSM state is not semantically the same as a control step in the scheduled CDFG. In a scheduled CDFG, several control flow nodes can be assigned to the same control step. For example, it is possible in a CDFG that a Test node and portions of successor Block nodes are assigned to the same state. However, from an SFSM model, we can derive an FSMD with states that correspond to the states in the scheduled CDFG. The steps used for this construction are similar to rules used in scheduling a CDFG. The construction of an FSMD from an SFSM consists of two steps:
- Every Test node has a corresponding Join successor. - Test-Join pairs are properly nested. - A Loop node is the only entry and exit point for a cycle.
2.2
L--f----tt, L
/Test\
Structured FSM (SFSM)
We can represent a scheduled design by a FSM. FSMs are practical for logic and register-transfer synthesis, since well established synthesis techniques exist for them [4] [ll]. We use a form of FSM, the Structured Finite State Machine (SFSM), to bridge differences between the CDFG and finite state machine models. The SFSM model maintains the control flow structure of a scheduled CDFG within a finite state machine model. SFSMs are a subset of finite state machines with datapath (FSMD) [8]. FSMs can become unmanageable in size and complexity if the binary/Boolean encoding and transformation of data is explicitly described, e.g., describing the logical steps for performing multiplication of two 2’s complement 8-bit numbers. We can use data abstraction to elevate the level of description from the Boolean level to abstract data types such as integers. Briefly, FSMDs are finite state machines defined on the semantics of abstract variables to describe conditions for transitions, and transformations of inputs to outputs. We define FSMD (S, I U STAT,0 U A,f , h) , where S is a set of states, I is a set of inputs, STAT is a set of status signals, each a logical/relational expression, 0 is a set of outputs, A is a set of assignments, f : S x I U STAT I+ S is a transition function, and h : S x I U STAT I+ 0U A is an output function.
1. Merge Condition/Loop Test and A c t i o n states: Condition (or Loop Test) states with immediate successors that are Action states can be merged into a single state. 2. Eliminate Join s t a t u : Join states are artifacts of the original CDFG description. They can be eliminated by “skipping” them in the FSMD model.
An SFSM is astructured form of the FSMD (Figure lb). An SFSM can have four types of states: Action, Condition, Join, and Loop Test. The semantics and usage of SFSM constructs are best described in terms of the CDFG.
Consequently, given a SFSM model, a designer can derive both a CDFG and an FSMD model that are closely
333
related and behaviorally identical. It should be noted that translation t o an FSMD can constitute a “point of no return”, since further optimization of the FSMD may make it impossible t o generate an equivalent SFSM or CDFG. Several advantages arise from using both the CDFG and SFSM models. First, any changes made t o the SFSM can be correlated to the CDFG for further analysis. Second, since a scheduled CDFG and SFSM are behaviorally equivalent, we can translate between the two representations for tasks appropriate t o each model. Third, by using a hybrid of flow graphs and FSMs, we are able t o use both flow graph and FSM analysis techniques on the model.
3
there must be no intervening states between the Condition states or their corresponding Join states. The action movement transformations allow the re-ordering of actions t o alter design characteristics, e.g., so that fewer functional units are required. For action movement across a Condition/Join state, Action states must immediately precede and succeed the Condition/Join state.
4
The application of similar compiler optimizations to HLS has been done [15] [3] [5], but differ from this work in the design models and approach. Interactive use of similar transformations for retiming have been done by Potkonjak and Rabaey, and Malik et. al [13] [lo]. However, retiming differs from scheduling in the underlying data being transformed. While retiming tools allow changing the usage and number of registers in a circuit, they will not change the usage or number of operational units. Scheduling, in contrast, influences the usage and number of registers and operational units for a circuit synthesized from a transformed behavioral description. Leeser and Wolf describe transformations on an FSM model with similar effects as the transformations described here [9]. However, their system is based entirely on FSM models (BFSM and RTFSM). The structures in these models do not directly correspond t o one another or to the control flow of the original HDL description. Consequently, these models are not amenable to the interactive approach we are suggesting, where being able to represent a given change in all the models is highly desirable. Walker and Thomas have explored interactive transformation of behavioral descriptions similar to this work [16]. They have developed a system t o manipulate value trace (VT) representations derived from ISPS. Their system performs code motion and condition merging transformations similar to the transformations described in this paper. However, the V T representation is a data flow graph model variant. Unfortunately, data flow graphs are not amenable to some tasks such as state minimization or control analysis for resource sharing. For our work, we use a CDFG and have formulated the SFSM for the very reason that these models facilitate a wide range of synthesis tasks.
Transformations
Only a small set of transformations is needed to enable the rescheduling of a description while maintaining the behavior of the design. T h e transformations described here are targeted for the SFSM model. These transformation were chosen since they do not alter the well-structuredness of the design model. To preserve the functionality of the design, datadependencies between actions in the description must be maintained. For a data carrier, such as a variable, the functionality of that data carrier is preserved if the order in which its data is assigned and used is not altered. The concept of definition-use chaining (du-chaining) is used to maintain this ordering [l]. A transformation preserves the behavior of the design only if the result does not violate the ordering defined by the du-chains.
5
(c) Mwemell betwen M b n 8latm
Related Work
Status
The transformations described in this paper have been implemented in C on Sun workstations, and are currently working within the BIF design environment [7]. A graphical user interface, XBIF [6], allows the designer to interactively apply these transformations to a scheduled behavior represented as a BIF Operations-Based State Table. Figure 3 shows the application of a movement transformation t o the Fifth Order Digital Elliptic Filter benchmark. The initial schedule for this example was derived without considering register sharing. This design was manually rescheduled by the application of two movement transformations, and resulted in a decrease of 2 in the minimal number of registers required. Within the environment, an attempt t o apply a transformation incorrectly is aborted, and the user is notified via a message on the screen. Since different layout architectures may require different sched-
(d)kwemenl w x c a Condkim‘.bh state
Figure 2: Transformations These transformations are illustrated in Figure 2. The addition of an empty Action state allows flexibility in reordering the existing actions, while deletion of an empty Action state reduces the number of states with the goal of improving the design’s performance. The merging of conditions changes the control of the design such that the two condition tests are considered together in a single state rather than in two separate states. To merge conditions,
334
Figure 3: Transformation application via XBIF
T. Hadley, L. Ramachandran and E. Rundensteiner for
ules and allocations, the user can manually experiment with the rescheduling of operations to search for optimal implementations tuned to particular physical design models. We have also developed tools that translate between the CDFG and SFSM models. Thus far, this has enabled the use of an external tool, VSS [14], t o produce a scheduled CDFG from which an SFSM model is constructed in BIF. Our technical report contains detailed discussions of the transformations and models presented in this paper [2].
6
their help and input.
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Summary
Automatic schedulers may be limited in their effectiveness since they do not have information generated by subsequent synthesis tasks, or may not have knowledge of the target architecture. Also, they may not make intelligent decisions due t o the limitations of the design representation they use. To alleviate these shortcomings, a manual rescheduling capability is needed to permit designers to incorporate additional knowledge, such as floorplanning and layout information, early in the design process. In this paper, we defined a CDFG to represent behavior described in an imperative HDL. We then defined the SFSM, a well-structured, abstract FSM that is appropriate for capturing the scheduled behavior of a design. The SFSM was defined in terms of the CDFG by describing construction rules to go between these design models, thus showing the equivalence of the models. We explained the advantages of maintaining both design models, and showed that the SFSM, and hence the scheduled CDFG, is a subset of the FSMD design model used in high-level synthesis. We then outlined behavior preserving transformations suitable for scheduling in high-level synthesis. We have integrated these transformations into an interactive environment to allow manual rescheduling of a design compiled into an SFSM model. This is the first step towards an interactive HLS environment where a designer can perform various synthesis tasks simultaneously. Our current work has not dealt with timing specifications in the input behavior. Our future work will address these issues as well as focus on developing metrics to help designers apply these transformations effectively.
Acknowledgments This work was partially supported by NSF grant MIP9009239 and SRC contract 91-DJ-146. We also thank
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