Power Amplifier PAE and Ruggedness Optimization by ... - IMS Chips
Power Amplifier PAE and Ruggedness Optimization by Second Harmonic Control M.Spirito, L.N.C.de Vreede, L.K.Nanver, S.Weber∗ and J.N.Burghartz Laboratory of ECTM / DIMES, Delft University of Technology, The Netherlands ∗ WS LIN group at Infineon Technology Munich, Germany Email: [email protected] Abstract— In this paper we discuss the optimization of PAE and ruggedness of balanced push-pull output stages for handsets. For output stages it can be shown that proper second harmonic termination can enforce optimum classAB operation, independently of the antenna impedance. This yields significant PAE and ruggedness improvements under high miss-match conditions. In this work various differential output stages are presented which utilize integrated filters and/or baluns. All passive structures have been optimized for low-loss using a novel high resistivity Silicon technology. Keywords— Differential output stages, PAE, ruggedness, second harmonic termination.
I. Introduction The development of Microwave Monolithic Integrated Circuit (MMIC) for wireless applications is focused on cost reduction and increased functionality on chip to reduce the component count and board-space consumption. At the moment, Silicon and SiGe technologies are entering the PA handset market, which until recently, was dominated by III-V (GaAs) technologies. The wide use of III-V technologies for this application can be explained by the inherently better trade-off in device breakdown versus device speed. This yields significant headroom during the design cycle and eases the development of the PA modules. Quite often a shorter time to market and / or better specifications as their silicon counterparts is the result. In spite of the advantages of III-V devices, the lower costs of Si/SiGe technologies and higher integration level guarantees a continuous drive to replace the III-V parts in the output stages. In enabling Si/SiGe technologies for PA applications two major issues have to be solved. First, the robustness of the designs for severe mismatch conditions, while preserving a high PAE, must be improved. Secondly, the high losses of the integrated passive components, degrading the PAE, must be lowered. To improve for the ruggedness and PAE under mismatch conditions we apply the following approach. It is known from [1], [2] that
623
varying the source and load conditions for the secondorder harmonic has a strong impact on the PAE and the voltage swing over the active devices of the output stage. By applying this technique to a differential PA, intended for digital communication system (DCS) band, we can implement a second-harmonic control which is independent of the fundamental loading. Note that such a circuit solution, requires the use of baluns combined with second harmonic filtering to cancel out the even harmonics. Since we are aiming for high-level integration, and want to support an integrated ”plug and play” solution, we have chosen to implement the required matching networks on chip. This choice puts high demands on the passive components, since these components need to feature low-loss in order to avoid degradation of the PAE. In general, this proves to be a difficult task, due to the inherent high dielectric losses related to conventional silicon wafers. By using high-resistivity silicon substrates the losses can be significantly reduced. For this purpose a novel high-ohmic DIMES-04 RF process technology has been developed at DIMES. This process combines high performance bipolar devices (fT = 25 GHz) with low-loss passives. II. Single-Ended Power Amplifier Operation In [2] it was shown that the second harmonic termination at the source and load of a single-ended amplifier can set the amplifier operation to Class-AB or the so called inverse Class-AB. Where the inverse Class-AB refers to an opposite current and voltage behaviour in respect to Class-AB operation (Fig.1). The results presented in Fig.1 were obtained by performing an harmonic balance simulation in Agilent ADS circuit simulator. Harmonic load and source were used to set different termination for the fundamental, second and third-order harmonic. If we sweep the phase of the reflection coefficient of the second harmonic termination, while keeping its magnitude constant to 1, we can study the PAE and VCE voltage
Fig. 3 2nd harmonic terminations in shunt series resonator configuration.
Fig. 1 Inverse Class-AB IC (left) and VCE (right) versus time.
A. Second Harmonic Shorts in Single-Ended PA’s
Fig. 2 Comparison between Class-AB and inverse Class-AB PAE and Voltage swing peak.
swing as shown in Fig.2. Both amplifier operations show a comparably high PAE, but the inverse ClassAB operation exhibits a significantly higher voltage swing at the collector of the output devices (Fig.2). Previous works [1], [2] pointed out how inverse classAB is more robust to load mismatch, as the high PAE region, in terms of second harmonic terminations, is larger compared to the Class-AB (Fig.2 and Fig.5). On the contrary, to improve for ruggedness and hence to lower the stress on the amplifier the preferred amplifier, operation mode is Class-AB. From [2] it follows that this can be achieved by applying short conditions at the input and output of the amplifier for the second harmonic. In the next section we discuss the consequences of adding these second harmonic shorting concept to a single-ended configuration.
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As mentioned above, to set the amplifier in ClassAB mode, we have to provide a short 2nd -harmonic termination at the input and output of the amplifier. To make the amplifier work properly, this termination must have no degradation effects at the fundamental frequency. A structure that has the required frequency behaviour to implement the correct terminations, is a harmonic filter. To implement a harmonic short we can use a series resonance filter at the input and output of the amplifier in shunt connection (Fig.3). By choosing the second harmonic as the resonant frequency we provide, in the ideal case, short terminations at 2 · f0 without any effects at other frequencies. At first glance a series resonator appears to be a good compromise between simplicity in the design and area consumption. Additional matching networks are required to match the active device for the fundamental signal. Note that the 2nd -harmonic terminations for maximum PAE and minimum voltage swing are only valid if the reference planes are placed at the intrinsic device. Any shift of these reference planes will make the short conditions applied to the amplifier ineffective for varying load conditions (see Appendix). This yields the conclusion that 2nd harmonic shorts should be preferably placed on chip, while single-ended hybrid solution using 2nd -harmonic shorts seems less feasible. III. Differential Power Amplifier Operation When considering differential output stages, we can basically repeat the analysis of [2], shown in Section II. Here we consider a push-pull amplifier as shown in the schematic presented in Fig.4. The results of the analysis show a large similarity to the ones presented in Section II with respect to the operating classes. The results are summarized in the 3D plots of Fig.5 and Fig.6 where the x and y-axes represent the 2nd -
Fig. 4 Push pull schematic used in ADS simulation.
nd
Vce versus 2
nd
PAE versus 2
Fig. 5 harmonic load and source phase with |Γ| = 1
harmonic phase expressed in radians, source phase 0 < Φ < 2π, and load phase -π < Φ < π. From Fig.5 and Fig.6 we can notice how in the differential case it is still easy to identify the two working regions, Class-AB and inverse Class-AB. The only difference from the single-ended case is that the constant PAE region for the inverse Class-AB is more flat showing an even more constant behaviour of PAE versus second harmonic terminations. Again we find maximum PAE at relative low VCE voltage swing for the ClassAB operation (Γ2nd Source = Γ2nd Load = −1). A. 2nd harmonic shorts in Differential PA’s When considering differential amplifier structures, it is important to keep in mind, that most of the application of today front-ends require a single-ended signal as the final output. This consideration leads to the conclusion that we have to include a balance-
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Fig. 6 harmonic load and source phase with |Γ| = 1
Fig. 7 Center taped ideal transformer under common mode and differential excitation.
to-unbalance structure (balun) at the output of the amplifier. The use of a filter structure for an harmonic short at the output would still suffer from the load dependence, as shown in the single-ended case. One way to achieve a load independent harmonic short is to consider a structure that enables to decouple even from odd-order harmonic terminations. If we consider a center tapped transformer we can conclude that this structures shows different terminations depending on the mode of excitation. Considering Fig.7 we can see that in an ideal center-tapped transformer, a common mode signal will cancel out, showing centertap impedance termination; in this case this is a short. Under a differential excitation the two signals at the primary winding, do not cancel and couple with the secondary winding. This allows to set the impedance for the differential stimuli at the secondary winding of the transformer independently of the common mode
Fig. 9 Output interconnection schematic.
Fig. 8 Center tap capacitor to resonate out parasitic inductance effects.
termination (center-tap impedance). A differentially driven amplifier will generate even in-phase (common mode) harmonics and odd in anti-phase (differential mode) harmonics. In a real transformer the coils are not perfectly coupled k < 1, the value of the inductance is finite and there are losses related to the finite conductivity of the lines. This yields to an impedance different from zero seen by the common mode signal. The differential mode signal will be effected by those parasitics only in terms of losses in the quality of the transformer. To compensate for this effect and present a short to the common-mode signal, we can use a capacitor to cancel out the effect of the parasitic inductor. Adding at the center tap a capacitor C = ω22Lp we realize a series resonator between the two parallel connected inductances, Lp and Lp , and the capacitor C (Fig.8). Note, that in this way the cancellation of the parasitic inductance for the even mode can be done independent of the loading at the fundamental . Termination of one of the two ends of the secondary transformer winding in a short will provide the needed balance-unbalance transformation. However the short termination will also affect the symmetry of the structure, since the parasitic capacitance of the winding at the grounded node will be short-circuited to ground. This leads to a phase unbalance in the propagation paths of the differential signal. Both integrated and hybrid implementations of the center-tapped transformer facilitate a perfect second harmonic-termination independent from the fundamental loading. However, an integrated solution allows a better defined cancellation of the common mode series inductance.
626
IV. The implementation of fully integrated push-pull amplifiers Different topologies of the power amplifier with output power levels in the range of 20 to 27 dBm where designed and realized. The technologies used for implementing the circuit are Infineon’s B6HFC and the DIMES-04 process technologies. The Infineon process provides a double poly silicon with fT of 25 GHz and a BVceo of 5.2 V. The DIMES process is a silicon process with fT of 25 GHz, BVceo of 4 V and the option of using a normal (100 Ω·cm) or high resistivity substrate (> 1000 Ω·cm). Infineon’s technology gives the best performances for the active part of the high power amplifier circuit, while the DIMES technology with the high-resistivity substrate option allows the integration of high-quality and low-loss passive structures such as coils and transformers. A. Active Part The differences in the implementation of the active part for two different technologies are summarized in TABLE I. A simplified scheme of the interconnection of the transistors for the amplifiers is shown in Fig.9. TABLE I Active part comparison between Infineon and DIMES technology.
Emitter Area (AE ) Number of BJT’S Ballasting Resistors
Infineon B6HFC 32.8µm2 24 no
DIMES-04 32µm2 20 no
B. Test structures and their performances Harmonic filter The use of a band pass filter for 2nd -harmonic short, requires high-quality components to achieve a high attenuation of the 2nd -harmonic. High quality inductors in multi-metal-layer technology can be realized using
Fig. 10 Measured S11 versus frequency of 2nd harmonic filter.
two metal layers connected together through vias to reduce the series resistance [5]. The number of turns and the line width can be chosen to optimize the quality factor for a certain frequency [6]. High-resistivity substrate allows the use of wider lines since the substrate losses are drastically reduced. High quality capacitor can be realized with a metal-insulator-metal (MIM) structure. In Infineon’s technology a 3-metallayer capacitor was realized in order to reduce area consumption by connecting the 1st and 3rd metal layers in parallel (Fig.11). The measured result of a 3.6 GHz harmonic filter realized in Infineon B6HFC technology is presented in Fig.10. Center tapped transformer A variation of a concentric spiral transformer [4] was chosen for the structure at the input of the amplifier (Fig.12). In the implemented transformer the primary winding is at the outside as well as at the inside of the secondary winding [3]. This structure enables high turn ratio at the price of lower mutual coupling (kfactor). The reduction of capacitive coupling between the primary and secondary windings allows a larger bandwidth for the transformer. The turn ratio is 5:2; this allows to achieve a high impedance ratio. A high inductance at the primary winding sets the optimum transfer frequency of the transformer at the desired frequency. At the secondary winding the inductance is lower and a capacitance might be needed to lower the losses at the working frequency. The input capacitance of the amplifier allows to avoid the use of an extra component. The center tap at the secondary port is connected to a capacitor in order to achieve a 2nd -harmonic short
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Fig. 11 Power amplifier in Infineon’s B6HFC technology with 2nd harmonic filter at the input
Fig. 12 Schematic of implemented circuit with input and output transformer
at the input of the amplifier. The capacitor was divided in two (half value each) for space and symmetry optimization. In Fig.13 the implemented transformer at the input of the amplifier realized in DIMES04 using high resistivity substrates, is shown. Output Balun A 1:1 transformer operating as a balun (secondary grounded at one of the nodes) was designed and implemented for application at the output of the amplifier (Fig.12). Here, the silicon area consumption is largely increased to cope with the need of achieving low series resistance. This is mainly to reduce the losses connected with the higher current levels at the output. The structure is a parallel connection of two large inductor lines for the primary as well as for the secondary winding. Each line at the primary is adjacently placed to the lines of the secondary winding to improve the coupling. The structure presents a high capacitive coupling to increase the k factor at the desired frequency. Metal 1 and 2 are connected in parallel to further lower the series resistance of the large structure. A center tap with capacitor at the primary provides the second harmonic short at the
technology in Munich, for the fabrication of the chips and the support of the project. References [1] R. Jos, ”Future developments and technology otpion in Cellur Phone Power Amplifiers: from power amplifiers to integrated RF front-end module”, Proc. BCTM-2000, pp. 118-125, Minneapolis, MI. [2] F. van Rijs, R. Dekker, H.A. Visser, H.G.A. Huizing, D. Hartskeerl, P.H.C. Magnee and R. Dondero ”Influence of output impedance on power added efficiency of Sibipolar power transisotrs”, in Digest of IEEE MTT-S 2000, pp.1945-48, Boston MA. [3] W. Simb¨ urger, H. Wohlmuth, P. Weger and A. Heinz ”A Monolithic Transformer Coupled 5-W Silicon Power Amplifier with 59% PAE at 0.9 GHz”, IEEE Journal of Soild-State Circuits, vol.34, no.12, December 1999. [4] J. Long ”Monolithic transformers for silicon RF IC design”, IEEE Journal of Soild-State Circuits, vol.35, no.9, September 2000. [5] J.N. Burghartz , M. Soyuer, K.A. Jenkins ”Microwave inductors and capacitors in standard multilevel interconnect silicon technology ”, in IEEE Transactions on Microwave Theory and Techniques, vol.44, no.1, January 1996. [6] J. Sieiro, J.M. Lopez-Villegas, J. Cabanillas, J.A. Osorio, J.Samitier ”A Complete Phisical Frequency Dependent Lumped Model for RF Integrated Inductors”, in Digest of 2001 IEEE RFIC Symposium, pp.121-24, Phoenix, AZ.
Fig. 13 Power amplifier with input and output transformer in DIMES04 high resistivity technology.
Fig. 14 Insertion loss of EM simulated output balun.
output of the amplifier. Fig.13 gives the layout of the output balun connected at the output of the amplifier. Fig.14 provides the simulated insertion loss versus frequency. V. Conclusion In this paper we presented a study on optimization of a high power amplifier for the handset market PAE and ruggedness via control of 2nd -harmonic termination. The impact of 2nd -harmonic termination was analyzed for both single -ended and differential configurations. On chip solutions were discussed and implemented. VI. Acknowledgments The authors would like to acknowledge J. Sieiro and B. Rejaei for their help and suggestions and Infineon
628
Appendix Referring to fig.15 where the matching network and the variable load can be expressed as one varying quantity ZL we can calculate Zin as: Zin =
(jωL + jωL +
1 jωC ) · ZL 1 jωC + ZL
Substituting this relation in the second expression we obtain: jωr2 Ls = 0 The last equation proves that with a single ended configuration we can not achieve a short for the 2nd harmonic that is load independent.
where ZL = R + jX At the second harmonic frequency ωr , to obtain a load independ short, we must impose Zin = 0 for every value of ZL. This lead to the following conclusion: Zin = 0 ∀ ZL ⇐⇒ ωr2 LC = 1 Fig. 16
Fig. 15
In figure 16 a more realistic case is considered. Now the filter is not directly connected to the collector of the transistor but there is a passive network in between due to the interconnections. This can be represented as an inductor in the most simple case or a more complex network for larger structure. For ease of calculation we will consider the network here as a simple inductor (Ls ) consequently we can say that: Zin =
(jωL + jωL +
1 jωC ) · ZL 1 jωC + ZL
+ jωLs
To achieve a short at ωr we have to impose that: (1 − ωr2 LC) · ZL + jωr Ls (1 − ωr 2LC) + jωr2 Ls ZL = 0 To obtain the condition Zin = 0 independently from ZL we must solve the following system:
jωr Ls (1 − ωr2 LC) = 0 ZL(1 − ωr2 LC + jωr2 Ls ) = 0
The second equation is the condition for the short to be load independent, while the first full fill the condition of Zin = 0 at ωr The first of the two equation in the system is solved by the relation: ωr2 LC = 1
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I. Introduction The development of Microwave Monolithic Integrated Circuit (MMIC) for wireless applications is focused on cost reduction and increased functionality on chip to reduce the component count and board-space consumption. At the moment, Silicon and SiGe technologies are entering the PA handset market, which until recently, was dominated by III-V (GaAs) technologies. The wide use of III-V technologies for this application can be explained by the inherently better trade-off in device breakdown versus device speed. This yields significant headroom during the design cycle and eases the development of the PA modules. Quite often a shorter time to market and / or better specifications as their silicon counterparts is the result. In spite of the advantages of III-V devices, the lower costs of Si/SiGe technologies and higher integration level guarantees a continuous drive to replace the III-V parts in the output stages. In enabling Si/SiGe technologies for PA applications two major issues have to be solved. First, the robustness of the designs for severe mismatch conditions, while preserving a high PAE, must be improved. Secondly, the high losses of the integrated passive components, degrading the PAE, must be lowered. To improve for the ruggedness and PAE under mismatch conditions we apply the following approach. It is known from [1], [2] that
623
varying the source and load conditions for the secondorder harmonic has a strong impact on the PAE and the voltage swing over the active devices of the output stage. By applying this technique to a differential PA, intended for digital communication system (DCS) band, we can implement a second-harmonic control which is independent of the fundamental loading. Note that such a circuit solution, requires the use of baluns combined with second harmonic filtering to cancel out the even harmonics. Since we are aiming for high-level integration, and want to support an integrated ”plug and play” solution, we have chosen to implement the required matching networks on chip. This choice puts high demands on the passive components, since these components need to feature low-loss in order to avoid degradation of the PAE. In general, this proves to be a difficult task, due to the inherent high dielectric losses related to conventional silicon wafers. By using high-resistivity silicon substrates the losses can be significantly reduced. For this purpose a novel high-ohmic DIMES-04 RF process technology has been developed at DIMES. This process combines high performance bipolar devices (fT = 25 GHz) with low-loss passives. II. Single-Ended Power Amplifier Operation In [2] it was shown that the second harmonic termination at the source and load of a single-ended amplifier can set the amplifier operation to Class-AB or the so called inverse Class-AB. Where the inverse Class-AB refers to an opposite current and voltage behaviour in respect to Class-AB operation (Fig.1). The results presented in Fig.1 were obtained by performing an harmonic balance simulation in Agilent ADS circuit simulator. Harmonic load and source were used to set different termination for the fundamental, second and third-order harmonic. If we sweep the phase of the reflection coefficient of the second harmonic termination, while keeping its magnitude constant to 1, we can study the PAE and VCE voltage
Fig. 3 2nd harmonic terminations in shunt series resonator configuration.
Fig. 1 Inverse Class-AB IC (left) and VCE (right) versus time.
A. Second Harmonic Shorts in Single-Ended PA’s
Fig. 2 Comparison between Class-AB and inverse Class-AB PAE and Voltage swing peak.
swing as shown in Fig.2. Both amplifier operations show a comparably high PAE, but the inverse ClassAB operation exhibits a significantly higher voltage swing at the collector of the output devices (Fig.2). Previous works [1], [2] pointed out how inverse classAB is more robust to load mismatch, as the high PAE region, in terms of second harmonic terminations, is larger compared to the Class-AB (Fig.2 and Fig.5). On the contrary, to improve for ruggedness and hence to lower the stress on the amplifier the preferred amplifier, operation mode is Class-AB. From [2] it follows that this can be achieved by applying short conditions at the input and output of the amplifier for the second harmonic. In the next section we discuss the consequences of adding these second harmonic shorting concept to a single-ended configuration.
624
As mentioned above, to set the amplifier in ClassAB mode, we have to provide a short 2nd -harmonic termination at the input and output of the amplifier. To make the amplifier work properly, this termination must have no degradation effects at the fundamental frequency. A structure that has the required frequency behaviour to implement the correct terminations, is a harmonic filter. To implement a harmonic short we can use a series resonance filter at the input and output of the amplifier in shunt connection (Fig.3). By choosing the second harmonic as the resonant frequency we provide, in the ideal case, short terminations at 2 · f0 without any effects at other frequencies. At first glance a series resonator appears to be a good compromise between simplicity in the design and area consumption. Additional matching networks are required to match the active device for the fundamental signal. Note that the 2nd -harmonic terminations for maximum PAE and minimum voltage swing are only valid if the reference planes are placed at the intrinsic device. Any shift of these reference planes will make the short conditions applied to the amplifier ineffective for varying load conditions (see Appendix). This yields the conclusion that 2nd harmonic shorts should be preferably placed on chip, while single-ended hybrid solution using 2nd -harmonic shorts seems less feasible. III. Differential Power Amplifier Operation When considering differential output stages, we can basically repeat the analysis of [2], shown in Section II. Here we consider a push-pull amplifier as shown in the schematic presented in Fig.4. The results of the analysis show a large similarity to the ones presented in Section II with respect to the operating classes. The results are summarized in the 3D plots of Fig.5 and Fig.6 where the x and y-axes represent the 2nd -
Fig. 4 Push pull schematic used in ADS simulation.
nd
Vce versus 2
nd
PAE versus 2
Fig. 5 harmonic load and source phase with |Γ| = 1
harmonic phase expressed in radians, source phase 0 < Φ < 2π, and load phase -π < Φ < π. From Fig.5 and Fig.6 we can notice how in the differential case it is still easy to identify the two working regions, Class-AB and inverse Class-AB. The only difference from the single-ended case is that the constant PAE region for the inverse Class-AB is more flat showing an even more constant behaviour of PAE versus second harmonic terminations. Again we find maximum PAE at relative low VCE voltage swing for the ClassAB operation (Γ2nd Source = Γ2nd Load = −1). A. 2nd harmonic shorts in Differential PA’s When considering differential amplifier structures, it is important to keep in mind, that most of the application of today front-ends require a single-ended signal as the final output. This consideration leads to the conclusion that we have to include a balance-
625
Fig. 6 harmonic load and source phase with |Γ| = 1
Fig. 7 Center taped ideal transformer under common mode and differential excitation.
to-unbalance structure (balun) at the output of the amplifier. The use of a filter structure for an harmonic short at the output would still suffer from the load dependence, as shown in the single-ended case. One way to achieve a load independent harmonic short is to consider a structure that enables to decouple even from odd-order harmonic terminations. If we consider a center tapped transformer we can conclude that this structures shows different terminations depending on the mode of excitation. Considering Fig.7 we can see that in an ideal center-tapped transformer, a common mode signal will cancel out, showing centertap impedance termination; in this case this is a short. Under a differential excitation the two signals at the primary winding, do not cancel and couple with the secondary winding. This allows to set the impedance for the differential stimuli at the secondary winding of the transformer independently of the common mode
Fig. 9 Output interconnection schematic.
Fig. 8 Center tap capacitor to resonate out parasitic inductance effects.
termination (center-tap impedance). A differentially driven amplifier will generate even in-phase (common mode) harmonics and odd in anti-phase (differential mode) harmonics. In a real transformer the coils are not perfectly coupled k < 1, the value of the inductance is finite and there are losses related to the finite conductivity of the lines. This yields to an impedance different from zero seen by the common mode signal. The differential mode signal will be effected by those parasitics only in terms of losses in the quality of the transformer. To compensate for this effect and present a short to the common-mode signal, we can use a capacitor to cancel out the effect of the parasitic inductor. Adding at the center tap a capacitor C = ω22Lp we realize a series resonator between the two parallel connected inductances, Lp and Lp , and the capacitor C (Fig.8). Note, that in this way the cancellation of the parasitic inductance for the even mode can be done independent of the loading at the fundamental . Termination of one of the two ends of the secondary transformer winding in a short will provide the needed balance-unbalance transformation. However the short termination will also affect the symmetry of the structure, since the parasitic capacitance of the winding at the grounded node will be short-circuited to ground. This leads to a phase unbalance in the propagation paths of the differential signal. Both integrated and hybrid implementations of the center-tapped transformer facilitate a perfect second harmonic-termination independent from the fundamental loading. However, an integrated solution allows a better defined cancellation of the common mode series inductance.
626
IV. The implementation of fully integrated push-pull amplifiers Different topologies of the power amplifier with output power levels in the range of 20 to 27 dBm where designed and realized. The technologies used for implementing the circuit are Infineon’s B6HFC and the DIMES-04 process technologies. The Infineon process provides a double poly silicon with fT of 25 GHz and a BVceo of 5.2 V. The DIMES process is a silicon process with fT of 25 GHz, BVceo of 4 V and the option of using a normal (100 Ω·cm) or high resistivity substrate (> 1000 Ω·cm). Infineon’s technology gives the best performances for the active part of the high power amplifier circuit, while the DIMES technology with the high-resistivity substrate option allows the integration of high-quality and low-loss passive structures such as coils and transformers. A. Active Part The differences in the implementation of the active part for two different technologies are summarized in TABLE I. A simplified scheme of the interconnection of the transistors for the amplifiers is shown in Fig.9. TABLE I Active part comparison between Infineon and DIMES technology.
Emitter Area (AE ) Number of BJT’S Ballasting Resistors
Infineon B6HFC 32.8µm2 24 no
DIMES-04 32µm2 20 no
B. Test structures and their performances Harmonic filter The use of a band pass filter for 2nd -harmonic short, requires high-quality components to achieve a high attenuation of the 2nd -harmonic. High quality inductors in multi-metal-layer technology can be realized using
Fig. 10 Measured S11 versus frequency of 2nd harmonic filter.
two metal layers connected together through vias to reduce the series resistance [5]. The number of turns and the line width can be chosen to optimize the quality factor for a certain frequency [6]. High-resistivity substrate allows the use of wider lines since the substrate losses are drastically reduced. High quality capacitor can be realized with a metal-insulator-metal (MIM) structure. In Infineon’s technology a 3-metallayer capacitor was realized in order to reduce area consumption by connecting the 1st and 3rd metal layers in parallel (Fig.11). The measured result of a 3.6 GHz harmonic filter realized in Infineon B6HFC technology is presented in Fig.10. Center tapped transformer A variation of a concentric spiral transformer [4] was chosen for the structure at the input of the amplifier (Fig.12). In the implemented transformer the primary winding is at the outside as well as at the inside of the secondary winding [3]. This structure enables high turn ratio at the price of lower mutual coupling (kfactor). The reduction of capacitive coupling between the primary and secondary windings allows a larger bandwidth for the transformer. The turn ratio is 5:2; this allows to achieve a high impedance ratio. A high inductance at the primary winding sets the optimum transfer frequency of the transformer at the desired frequency. At the secondary winding the inductance is lower and a capacitance might be needed to lower the losses at the working frequency. The input capacitance of the amplifier allows to avoid the use of an extra component. The center tap at the secondary port is connected to a capacitor in order to achieve a 2nd -harmonic short
627
Fig. 11 Power amplifier in Infineon’s B6HFC technology with 2nd harmonic filter at the input
Fig. 12 Schematic of implemented circuit with input and output transformer
at the input of the amplifier. The capacitor was divided in two (half value each) for space and symmetry optimization. In Fig.13 the implemented transformer at the input of the amplifier realized in DIMES04 using high resistivity substrates, is shown. Output Balun A 1:1 transformer operating as a balun (secondary grounded at one of the nodes) was designed and implemented for application at the output of the amplifier (Fig.12). Here, the silicon area consumption is largely increased to cope with the need of achieving low series resistance. This is mainly to reduce the losses connected with the higher current levels at the output. The structure is a parallel connection of two large inductor lines for the primary as well as for the secondary winding. Each line at the primary is adjacently placed to the lines of the secondary winding to improve the coupling. The structure presents a high capacitive coupling to increase the k factor at the desired frequency. Metal 1 and 2 are connected in parallel to further lower the series resistance of the large structure. A center tap with capacitor at the primary provides the second harmonic short at the
technology in Munich, for the fabrication of the chips and the support of the project. References [1] R. Jos, ”Future developments and technology otpion in Cellur Phone Power Amplifiers: from power amplifiers to integrated RF front-end module”, Proc. BCTM-2000, pp. 118-125, Minneapolis, MI. [2] F. van Rijs, R. Dekker, H.A. Visser, H.G.A. Huizing, D. Hartskeerl, P.H.C. Magnee and R. Dondero ”Influence of output impedance on power added efficiency of Sibipolar power transisotrs”, in Digest of IEEE MTT-S 2000, pp.1945-48, Boston MA. [3] W. Simb¨ urger, H. Wohlmuth, P. Weger and A. Heinz ”A Monolithic Transformer Coupled 5-W Silicon Power Amplifier with 59% PAE at 0.9 GHz”, IEEE Journal of Soild-State Circuits, vol.34, no.12, December 1999. [4] J. Long ”Monolithic transformers for silicon RF IC design”, IEEE Journal of Soild-State Circuits, vol.35, no.9, September 2000. [5] J.N. Burghartz , M. Soyuer, K.A. Jenkins ”Microwave inductors and capacitors in standard multilevel interconnect silicon technology ”, in IEEE Transactions on Microwave Theory and Techniques, vol.44, no.1, January 1996. [6] J. Sieiro, J.M. Lopez-Villegas, J. Cabanillas, J.A. Osorio, J.Samitier ”A Complete Phisical Frequency Dependent Lumped Model for RF Integrated Inductors”, in Digest of 2001 IEEE RFIC Symposium, pp.121-24, Phoenix, AZ.
Fig. 13 Power amplifier with input and output transformer in DIMES04 high resistivity technology.
Fig. 14 Insertion loss of EM simulated output balun.
output of the amplifier. Fig.13 gives the layout of the output balun connected at the output of the amplifier. Fig.14 provides the simulated insertion loss versus frequency. V. Conclusion In this paper we presented a study on optimization of a high power amplifier for the handset market PAE and ruggedness via control of 2nd -harmonic termination. The impact of 2nd -harmonic termination was analyzed for both single -ended and differential configurations. On chip solutions were discussed and implemented. VI. Acknowledgments The authors would like to acknowledge J. Sieiro and B. Rejaei for their help and suggestions and Infineon
628
Appendix Referring to fig.15 where the matching network and the variable load can be expressed as one varying quantity ZL we can calculate Zin as: Zin =
(jωL + jωL +
1 jωC ) · ZL 1 jωC + ZL
Substituting this relation in the second expression we obtain: jωr2 Ls = 0 The last equation proves that with a single ended configuration we can not achieve a short for the 2nd harmonic that is load independent.
where ZL = R + jX At the second harmonic frequency ωr , to obtain a load independ short, we must impose Zin = 0 for every value of ZL. This lead to the following conclusion: Zin = 0 ∀ ZL ⇐⇒ ωr2 LC = 1 Fig. 16
Fig. 15
In figure 16 a more realistic case is considered. Now the filter is not directly connected to the collector of the transistor but there is a passive network in between due to the interconnections. This can be represented as an inductor in the most simple case or a more complex network for larger structure. For ease of calculation we will consider the network here as a simple inductor (Ls ) consequently we can say that: Zin =
(jωL + jωL +
1 jωC ) · ZL 1 jωC + ZL
+ jωLs
To achieve a short at ωr we have to impose that: (1 − ωr2 LC) · ZL + jωr Ls (1 − ωr 2LC) + jωr2 Ls ZL = 0 To obtain the condition Zin = 0 independently from ZL we must solve the following system:
jωr Ls (1 − ωr2 LC) = 0 ZL(1 − ωr2 LC + jωr2 Ls ) = 0
The second equation is the condition for the short to be load independent, while the first full fill the condition of Zin = 0 at ωr The first of the two equation in the system is solved by the relation: ωr2 LC = 1
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