Reducing test time of embedded srams - Memory Technology, Design ...
Reducing Test Time of Embedded SRAMs Baosheng Wang, Josh Yang and André Ivanov SOC Lab, Department of Electrical & Computer Engineering, University of British Columbia, Vancouver, B.C., Canada, V6T 1Z4 {baosheng, joshy, ivanov}@ece.ubc.ca
Abstract Compared with traditional functional fault models, fault model obtained from an Inductive Fault Analysis (IFA) test flow can provide an attractive basis for obtaining a good estimate of the overall test quality in terms of defect level and yield. However, the associated surging test time due to increased SRAM capacity is becoming a major challenge when testing either standalone or embedded SRAMs. This paper refines the functional fault models translated from defect simulations for embedded SRAMs with IFA proposed and described in [4]. Reconsidering the defect causes of the functional faults allows us to simplify the functional fault model FFM2 and formulate the test time required for detecting Data Retention Faults. We combine this simplification with the consideration of specific memory redundancy elements to develop a new March 6N Test algorithm. Simulation results reveal that our proposed fault modeling and test generation algorithm can reduce total test time to one half or less of that required by the methodology in [4], while maintaining the same defect and fault coverage. Keywords: Embedded SRAM test, Inductive Fault Analysis, Test Time, Memory Redundancy, March Test
1. Introduction The System-on-Chip (SoC) paradigm is associated with a trend from logic-dominant chips to memorydominant ones. From the ITRS documents [1], by 2013 over 90% of chip area will be occupied by diverse memories, e.g., embedded SRAMs (e-SRAMs). Increasingly dense e-SRAMs with large capacity are more prone to faults, not only reducing memory and SoC yield but also posing large challenges in test time. The nature of memory testing is different from that of logic testing since a memory is actually more of a mixed-signal device whose faulty behavior is often analog in nature. However, traditional functional memory fault models [2] typically assume a behavior that is digital in nature. Thus, memory tests targeting the coverage of traditional functional fault models are inherently difficult
to relate to yield. Inductive Fault Analysis (IFA) technology [3] has been proposed to extract memory faults that correspond to potential defects within the memories [4] [5]. Fault models built from IFA (here, we simply call them as IFA functional fault models) does relate more easily to test yield. However, test time challenges due to the higher and higher memory capacities still exist. To reduce the test time, in this paper we base our approach on the IFA functional fault models translated from defect simulations in [4] but simplify the FFM2 fault models and reduce test time of the Data Retention Faults by further analyzing the defect causes of these functional faults. Another aspect we consider here is the memory redundancy elements. That is, toward reducing memory yield loss, a number of different redundancy techniques are generally applied [6]. Row or column redundancy or their combinations are considered to be more applicable for high capacity memories while word redundancy is usually deemed more effective for low capacity memories according to the performance trade-offs in [6]. In practice, the specific test set development is separated from the development of the redundancy circuitry and associated repair algorithms. Our premise is that greater efficiencies, i.e., reduced test time, can be achieved by more tightly coupling these activities and by considering the redundancy techniques and simplified FFM2s. The remainder of this paper is organized as follows. In Sec. 2, we revisit the IFA functional fault models from [4] in view of simplifying them. This is achieved by reanalyzing the coupling fault and data retention fault sets. A new March 6N test algorithm based on these simplified models as well as row/column redundancy elements is proposed and presented in Sec. 3. Simulation results from fault injections are presented and discussed in Sec. 4. Finally, Sec. 5 draws some conclusions.
2. Defect Analysis of IFA Functional Fault Models 2.1 Background
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The adoption of specific fault models dictates the choice of applicable test algorithms. Obviously, the accuracy of test quality assessments directly depends on the fault model’s ability to represent the faulty behaviors caused by physical defects. Currently, there are two major methodologies available for building SRAM functional fault models: one is functional-based and the other is defect-based. In the case of the former, various faulty functional behaviors are assumed, regardless of their specific possibility and likelihood of being caused by a physical defect. In the latter case, the layout and circuit schematic are considered and Inductive Fault Analysis (IFA) is used to establish relationships between physical defects and their electrical and logical implications, as well as the statistical likelihood of such faulty behaviors. One attractive feature of functional fault models is that they tend to be simple to develop and formulate. However, their practical use is often easily jeopardized by the fact that corresponding fault lists and test sets grow unwieldy. For example a test length of (3N2 + 2N) • 2N is required to cover NPSFs (Neighborhood Pattern Sensitive Faults), where N is the number of addresses [7]. As a result, efforts are necessary to sacrifice “unimportant” or “unrealistic” functional faults from the more comprehensive sets. The difficulty then lies in establishing the relative importance of the functional faults that should be retained for consideration that correlate with final quality and yield. IFA functional fault models are proposed as an alternative to address the relationships between functional faults and test yield. In [4], the realistic functional faults translated from defect simulations under several assumptions are presented and the evaluation results are consequently in terms to defect level and yield. However, the overall test time from the fault translations to final manufacturing test is still unacceptable not only because of the lengthy IFA flow but also because of the increased memory capacity, such as in [4]. Thus, the IFA flow makes the memory test more realistic but does not solve the test time challenge especially for testing current and future e-SRAMs with higher capacity. In this paper, functional fault models derived from an IFA flow are applied but simplified to reduce test time. Based on [4], FFM2s and Data Retention Faults are revisited from the defect-level perspective.
2.2 The Simplified FFM2 Fault Class In [4], FFM2 denotes the functional faults involving two memory cells. Most of FFM2s are caused by the bridge defects between two cells. In [4], other defects
such as OC10, SW1, BC2, BC3 and OW can also lead to FFM2s. However, these defects can be detected with FFM1: BC3 and OW can be detected by the functional faults referred to as Incorrect Read Fault (IRF) and Stuck-Open Fault (SOF) respectively, while OC10, SW1 and BC2 can cause stuck-at one functional faults because the all-pass pass transistors cause the fault memory cells to be kept at logic one regardless of the read or write operations at these memory cells. Thus, according to the four cell configuration in [4], FFM2 can be simplified from the five types described in [4] to the following three types, without reducing the defect coverage (we refer to the four-cell configuration to illustrate these fault types): /BL1
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/BL2
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WL1 C1
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Figure 1. Four-cell memory configuration. Row Coupling Faults (RCFs): due to the potential bridges on the same row, the logic states of the two faulty cells (i.e., C1 and C3, or C2 and C4 in Figure 1) are always inverted from their normal/intended state. Column Coupling Faults (CCFs): because of the potential bridges on the same column, the contents of the cells (i.e., C1 and C2, or C3 and C4 in Figure 1) are coupled to the same values. Diagonal Coupling Faults (DCFs): when the potential bridges are on the same diagonal, the corresponding memory cells (i.e., C1 and C4. or C2 and C3 in Figure 1) will always retain the same logic value. After row (column) redundancy activation by the fuse repair, a whole defective row (column) of a memory cell array will be replaced by the redundancy element. Hence, only the redundant rows (columns) instead of the defective rows (columns) of the memory will be accessed subsequently. Normally, the faulty memory cells, the aggressor cell and the victim cell, subject to any one the above three coupling faults needs to be detected and repaired because both of them are assumed to be defective. However, once the redundant row (column) is used to replace that of the aggressor or victim cell, the relationship between the victim or aggressor will not exist because the aggressor or victim cell will cease to be accessed according to the applied redundancy mechanism. In other words, detecting and repairing any one faulty cell of a pair due to bridges are enough for yield improvement if no other defects occur affecting such a memory pair. For example, if C1 and C2 in Figure 1 are faulty only because they are coupled, the achieved yield when detecting and repairing C1 or C2 is
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the same as that when detecting and repairing both, that is, C1 or C2 will become fault-free if one or the other is repaired. In this fashion, not only can test time be shortened, but repair component requirements can also be reduced. Both these factors can reduce test cost.
2.3 Data Retention Fault (DRF) Another type of memory cell fault, namely the Data Retention Fault (DRF), which occurs when a memory cell fails to correctly retain a previously stored logic value after some time, is difficult to simulate using logic level simulators. This type of fault can in practice be detected by performing a read operation after a delay (TD). To reduce the necessary TD for testing DRFs, several Design-for-Test (DFT) techniques have been proposed, e.g., [8] [9] [10]. However, as these entail extra circuitry, they amount to different area penalties. In this paper, not only is the delay time (TD) for detecting such faults reduced using our proposed test algorithm described later, this reduction is also quantified according to various parameters, such as the specifics of the memory under test, test cycle time, specific reading sequence during the testing of DRFs, etc. In general, two different DRFs may occur: Cell inability to retain a logic low after a specific time referred to as TDL Cell inability to retain a logic high after a specific time referred to as TDH DRFs can be caused by a defective source/drain/gate open of the pull-up transistor of the defective cell or by a defective VDD/VSS path. Figure 2 shows one of the Data Retention Fault Models as a resistive open defect in a VSS/pull-down transistor. With this defect, the cell will fail to retain a logic low.
T
F
(a) Opens at VSS/Pull down Transistor
Figure 2. One DRF Model with a Resistive Open in the VSS/Pull- down Transistor Usually, the final TD (TDF) is the maximum value of TDL and TDH in order to cover all the potential defects. However, because the bit-line will be pre-charged to high before the read operation and the node T in Fig. 2 will be pulled high due to the charge sharing effect by the larger bit line capacitance, reading zero from these cells with a type of defect shown in Figure 2 will flip their contents
to logic one. This DRF circuit level behavior corresponds to that of a Read Destructive Fault (RDF) or a Deceptive Read Destructive Fault (DRDF) in [4]. Therefore, this kind of defect can be detected if both RDF and DRDF have already been detected and the corresponding TDF can only be prescribed by the value of TDH. A shorter TDH will reduce the testing time of DRFs. Moreover, the TD can be further reduced in the proposed test algorithm discussed in detail in Sec. 3. This reduction is possible because of the necessary delay separating write operations to different cells. If the number of memory rows and number of columns are denoted by X and Y respectively, the new final delay time (TDNF) is defined as TDNF = TDF – TDA (1) where, TDA is defined as the re-accessing time of a particular memory cell under test. According to different address sequencing during test, TDA can be quantified according to the following (the period of the test clock during the test is denoted by TP) i) assuming cells are accessed row by row, (2) TDA = TP * (2X – 1) * 2 Y ii) assuming cells are accessed column by column, (3) TDA = TP * (2X – 1) In summary, by combining equation (1), (2) and (3), the TDNF can be chosen according to the following: TDNF = TDF - TP * (2X – 1) * 2Y if a March algorithm with a row by row address sequencing is applied; = TDF - TP * (2X – 1) if a March algorithm following a column by column address sequencing is applied; = TDF for other test algorithms. For all the three cases above, if RDFs and DRDFs in [4] have already been tested then TDF = TDH, otherwise TDF = max (TDL, TDH). Furthermore, from the formulations, the test time can still be reduced because the TDF can even be nullified. For example, the TDNF in testing the memories with 128K words capacity, 9 row addresses and 8 column addresses will not be necessary by using the March row by row address sequencing if the TDF is assumed as 1ms.
3. March 6N Test Algorithms 3.1 Related Work Currently, March 9N [11] is a popular memory test algorithm. From [11], the March 9N with Data Retention Test can be described as shown in Figure 3. In the descriptions of the memory test algorithms, “ ” means the address sequencing is increasing during
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the test, “ ” means the address sequencing is decreasing during the test and delay is the necessary TDNF discussed in Sec. 2. w0
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Figure 3. The March 9N Test Algorithm with Data Retention Test Due to its ability in testing some realistic functional faults, i.e., RDFs, March SRD in [4] is more realistic than March 9N and can thus further improve fault coverage and defect coverage. The description of the March SRD test algorithm is shown in Figure 4. w0
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Figure 4. The March SRD Test Algorithm However, because March SRD is equivalent to a March 14N test algorithm, the testing time is considerably worse than that of the former. Here, the new March 6N test algorithms are proposed to reduce test time while still maintaining the same fault and defect coverage as March SRD.
3.2 The Proposed March 6N Test Algorithms According to the defect analysis of the IFA functional faults in Sec. 2, the same yield can be achieved by row/column redundancy when repairing only one of two faulty cells which are due to bridges between the two cells as that when repairing both. When writing into such faulty memory cells, because the final contents of these two cells is only determined by the cell with the higher address when the writing address sequencing is increasing and by the cell with the lower address when the writing address sequencing is decreasing, only the testing of the FFM2s will be sensitive to the address sequencing, i.e., half of the potential FFM2s could be detected when using the increasing address sequencing and decreasing address sequencing separately (this will be verified in Sec. 4). Thus, either one of the address sequencing coupled with row/column redundancy activation is adequate for meeting the yield goal. This reduces the test time significantly. The proposed March 6N test algorithms are shown in Figure 5 (a) and (b), where either one of the test algorithms with different address sequencing can be applied to achieve the same yield as [4] when coupled with row/column redundancy.
From Figure 5, the proposed March 6N test algorithms reduce the test time to less than half the time required for running the March 9N with Data Retention Test and March SRD in [4]. w0
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Figure 5 The Proposed March 6N Test Algorithms
4. Validation of the Proposed Test Algorithms 4.1 Fault Injections In order to verify the test algorithms, the embedded memory under test (EMUT) of [12] consisting of a 65536 (64K) x32bit SRAM core with 14 row addresses and 2 column addresses is injected with faults. To cover all the defects within a cell, all the functional faults FFM1s involving a single cell in [4] except DRFs were injected for validation. All the simplified FFM2s in this paper were also injected into the EMUT in [12] according to the four cell configuration in Figure 1 and the HDL program shown in Figure 6. // Writing Cells
Case Address // injecting RCFs // Address Difference between // Aggressive and Victim Cells is ONE aggessive cell address: victim cell = inverter (aggressive cell)
// injecting CCFs // Address Difference between // Aggressive and Victim Cells is FOUR aggessive cell address: victim cell = aggressive cell
// injecting DCFs // Address Difference between // Aggressive and Victim Cells is FIVE aggessive cell address: victim cell = aggressive cell
Endcase
Figure 6.Coupling Faults Injections The faults and their addresses which were selected according to the Fig. 1 are shown in Table 1. Data Retention Faults (DRFs) were not injected into the SRAM, but can be detected by reading the cells after TDNF according to the defect analysis in the Sec. 2. In Table 1, all the functional faults caused by the potential defects except DRFs were injected into the
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EMUT. All the defects which have been reported in [4] were covered in all of the functional faults mentioned above. Thus, if all the faults in Table 1 can be detected, the defect coverage and fault coverage can be maintained at the same level as those achieved in [4]. Table 1 Faults Injected into 64Kx32bit SRAM under Test Number Fault Addresses Faults of (Hex) Faults Stuck-at Fault (SAF) 4 00, 03, fd, ff Transition Fault (TF) 4 20, 22, 30, 33 Stuck-Open Fault (SOF) 4 25, 26, 34, 36 Read Destructive Faults 4 50, 53, 59, 5a (RDF) Deceptive Read 4 60, 63, 69, 6a Destructive Fault (DRDF) Incorrect Read Fault 4 70, 73, 79, 7a (IRF) Random Read Fault 4 80, 82, 90, 93 (RRF) Undefined State Fault 4 86, 88, 95, 96 (USF) Aggressor/Victim Coupling RCFs 2 06/07 Fault (CF) CCFs 4 04/08, 10/14 DCFs Total
4
0a/0f, 16/1b 42
4.2 Validation Results The proposed test algorithm was validated under a HDL simulation environment by injecting the entire functional fault FFM1s in [4] except DRFs and the proposed simplified FFM2s and testing the EMUT by using the new March 6N with row by row address sequencing. The detected fault cell addresses are shown in Table 2 when both the proposed test algorithms and injected faults were simulated. Table 2: Detected Fault Cells Using Algorithm (a) Using Algorithm (b) Faults Shown in Figure 5 shown in Figure 5 SAF 00, 03, fd, ff 00, 03, fd, ff TF 20, 22, 30, 33 20, 22, 30, 33 SOF 25, 26, 34, 36 25, 26, 34, 36 RDF 50, 53, 59, 5a 50, 53, 59, 5a DRDF 60, 63, 69, 6a 60, 63, 69, 6a IRF 70, 73, 79, 7a 70, 73, 79, 7a RRF 80, 82, 90, 93 80, 82, 90, 93 USF 86, 88, 95, 96 86, 88, 95, 96 CF 07, 08, 0f, 14, 1b 04, 06, 0a, 10, 16 Total No. 37 37
From Table 2, all the faults and defects under the initial assumptions are detected using both address sequencing. Only the detection of Coupling Faults (CFs) is affected by the address ordering. If row/column redundancy is activated, using one of the two specific address sequencing rather than both suffices to meet yield improvement goals.
4.3 Comparison with March 9N and March SRD The test time of March 9N in Figure 3 can be quantified as (12*2N * TP + 2* TDNF) and the test time of March SRD in [4] can be quantified as (14*2N * TP + 2* TDNF). However, using either of the test algorithm (a) or (b) in Figure 5, the test time of the proposed test algorithms can be reduced to (6*2N * TP + 2* TDNF). Where, N is the memory address number. In [12], the 65536 (64K) x 32 bit SRAM with X = 14 row addresses and Y =2 column addresses is tested using a 10 ns test clock period TP and row-wise test address sequencing. TDH and TDL are 0.5ms and 0.8ms respectively according to the SPICE simulation in [12]. Using formulas in Sec. 2.3, the test time of the three test algorithms is compared and shown in Table 3 according to the quantification results above. Table 3 Comparison Results Test March 9N March SRD March 6N Algorithms TP(ns)/X/Y/N 10/14/2/16 TDH/TDL (ms) 0.5/0.8 TNDF (ms) 0.8 0.8 0 Test Time (ms) 9.46 10.76 3.93 From Table 3, it was found that the test time of our proposed March test algorithm can be reduced up to 58% and 63% of that of the latter respectively when compared with March 9N with Data Retention Test and March SRD in [4]. In summary, our proposed test algorithm is more realistic and efficient in test time compared to those of March 9N with Data Retention Test and it is faster than the March SRD in [4]. Importantly, this speedup is achieved without compromising fault and defect coverage.
5. Conclusions Although an IFA-based test flow allows the establishment of the relationship between the test results and yield and defect levels better than do the methodologies based on traditional functional tests, the test application time challenge, especially arising with increased memory capacity remains. Based on the fault
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models in [4] and further defect analysis, here we simplified FFM2s which can be used to reduce test time by coupling row/column redundancy. The predetermined delay time of DRFs is formulated to test memories more efficiently. By injecting and simulating the IFA functional faults in Table 1, we found that only Coupling Faults detection was dependent on memory address sequencing. The simulation results show that the proposed March 6N test algorithms are efficient in test time when considering the row/column redundancy techniques. For example, for the 65536 (64K) x 32 bit e-SRAM in [12], the test time can be reduced to 58% and 63% of the time required by the March 9N with Data Retention Test and March SRD [4] algorithm, respectively.
6. Acknowledgements We wish to thank NSERC, Micronet and the Canadian Microelectronics Corp for providing support for this work.
7. References [1] Alan Allan, et al. “2001 Technology Roadmap for Semiconductors”, IEEE Computer, pp. 42-53, Vol. 35, No. 1, January 2002. [2] A. J. van de Goor, “Testing Semiconductor Memories, Theory and Practice”, ComTex Publishing, Gouda, the Netherlands, 1998. Web: http://cardit.et.tudelft.nl/~vdgoor [3] J. P. Shen, et al., “Inductive fault analysis of MOS integrated circuits”, IEEE Design and Test of Computers, Vol. 2, No. 6, pp. 13-26, December 1985.
[4] Said Hamdioui, A. J. van de Goor, “An experimental analysis of spot defects in SRAMs: realistic fault models and tests”, Proceedings of the Ninth Asian Test Symposium (ATS2000), pp. 131-138, 2000. [5] T.M Mak, et al., “Cache RAM Inductive Fault Analysis with Fab Defect Modeling,” International Test Conference, pp. 862871, 1998. [6] E. Rondey, Y. Tellier, S. Borri, “A silicon-based yield gain evaluation methodology for embedded-SRAMs with different redundancy scenarios”, Proceedings of the Eighth IEEE International On-Line Testing Workshop, pp. 251 - 255, July 2002. [7] Dong-Chual Kang; Sang-Bock Cho, “An efficient built-in selftest algorithm for neighborhood pattern sensitive faults in highdensity memories”, Proceedings of the 4th Korea-Russia Int'l Symp. on Science and Tech, Vol. 2, 2000, pp. 218 -223. [8] J. Castillejos, V. H. Champac, “A forced-voltage technique to test data retention faults in CMOS SRAM by IDDQ testing”, Proceedings of the 40th Midwest Symposium on Circuits and Systems, Vol. 1, pp. 433 - 436, Aug.1997. [9] V. H. Champac, V. Avendano, M. Linares, “Bit line sensing strategy for testing for data retention faults in CMOS SRAMs”, Electronics Letters, Vol.36, No. 14, pp. 1182-1183, 6 July 2000. [10] A. Meixner, J. Banik, “Weak write test mode: an SRAM cell stability design for test technique”, Proceedings of International Test Conference, pp. 309 -318, Oct. 1996. [11] R. Dekker, et al., “A realistic fault model and test algorithms for static random access memories”, IEEE Transactions on Computer – Aided Design of Integrated Circuits and Systems, Vol. 9, No. 6, pp. 567-572, June 1990. [12] Baosheng Wang, Josh Yang, “SRAM Design and Optimization”, University of British Columbia EECE579 Homework 3, Dec. 2002.
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Abstract Compared with traditional functional fault models, fault model obtained from an Inductive Fault Analysis (IFA) test flow can provide an attractive basis for obtaining a good estimate of the overall test quality in terms of defect level and yield. However, the associated surging test time due to increased SRAM capacity is becoming a major challenge when testing either standalone or embedded SRAMs. This paper refines the functional fault models translated from defect simulations for embedded SRAMs with IFA proposed and described in [4]. Reconsidering the defect causes of the functional faults allows us to simplify the functional fault model FFM2 and formulate the test time required for detecting Data Retention Faults. We combine this simplification with the consideration of specific memory redundancy elements to develop a new March 6N Test algorithm. Simulation results reveal that our proposed fault modeling and test generation algorithm can reduce total test time to one half or less of that required by the methodology in [4], while maintaining the same defect and fault coverage. Keywords: Embedded SRAM test, Inductive Fault Analysis, Test Time, Memory Redundancy, March Test
1. Introduction The System-on-Chip (SoC) paradigm is associated with a trend from logic-dominant chips to memorydominant ones. From the ITRS documents [1], by 2013 over 90% of chip area will be occupied by diverse memories, e.g., embedded SRAMs (e-SRAMs). Increasingly dense e-SRAMs with large capacity are more prone to faults, not only reducing memory and SoC yield but also posing large challenges in test time. The nature of memory testing is different from that of logic testing since a memory is actually more of a mixed-signal device whose faulty behavior is often analog in nature. However, traditional functional memory fault models [2] typically assume a behavior that is digital in nature. Thus, memory tests targeting the coverage of traditional functional fault models are inherently difficult
to relate to yield. Inductive Fault Analysis (IFA) technology [3] has been proposed to extract memory faults that correspond to potential defects within the memories [4] [5]. Fault models built from IFA (here, we simply call them as IFA functional fault models) does relate more easily to test yield. However, test time challenges due to the higher and higher memory capacities still exist. To reduce the test time, in this paper we base our approach on the IFA functional fault models translated from defect simulations in [4] but simplify the FFM2 fault models and reduce test time of the Data Retention Faults by further analyzing the defect causes of these functional faults. Another aspect we consider here is the memory redundancy elements. That is, toward reducing memory yield loss, a number of different redundancy techniques are generally applied [6]. Row or column redundancy or their combinations are considered to be more applicable for high capacity memories while word redundancy is usually deemed more effective for low capacity memories according to the performance trade-offs in [6]. In practice, the specific test set development is separated from the development of the redundancy circuitry and associated repair algorithms. Our premise is that greater efficiencies, i.e., reduced test time, can be achieved by more tightly coupling these activities and by considering the redundancy techniques and simplified FFM2s. The remainder of this paper is organized as follows. In Sec. 2, we revisit the IFA functional fault models from [4] in view of simplifying them. This is achieved by reanalyzing the coupling fault and data retention fault sets. A new March 6N test algorithm based on these simplified models as well as row/column redundancy elements is proposed and presented in Sec. 3. Simulation results from fault injections are presented and discussed in Sec. 4. Finally, Sec. 5 draws some conclusions.
2. Defect Analysis of IFA Functional Fault Models 2.1 Background
Proceedings of the 2003 International Workshop on Memory Technology, Design and Testing (MTDT’03) 1087-4852/03 $17.00 © 2003 IEEE
The adoption of specific fault models dictates the choice of applicable test algorithms. Obviously, the accuracy of test quality assessments directly depends on the fault model’s ability to represent the faulty behaviors caused by physical defects. Currently, there are two major methodologies available for building SRAM functional fault models: one is functional-based and the other is defect-based. In the case of the former, various faulty functional behaviors are assumed, regardless of their specific possibility and likelihood of being caused by a physical defect. In the latter case, the layout and circuit schematic are considered and Inductive Fault Analysis (IFA) is used to establish relationships between physical defects and their electrical and logical implications, as well as the statistical likelihood of such faulty behaviors. One attractive feature of functional fault models is that they tend to be simple to develop and formulate. However, their practical use is often easily jeopardized by the fact that corresponding fault lists and test sets grow unwieldy. For example a test length of (3N2 + 2N) • 2N is required to cover NPSFs (Neighborhood Pattern Sensitive Faults), where N is the number of addresses [7]. As a result, efforts are necessary to sacrifice “unimportant” or “unrealistic” functional faults from the more comprehensive sets. The difficulty then lies in establishing the relative importance of the functional faults that should be retained for consideration that correlate with final quality and yield. IFA functional fault models are proposed as an alternative to address the relationships between functional faults and test yield. In [4], the realistic functional faults translated from defect simulations under several assumptions are presented and the evaluation results are consequently in terms to defect level and yield. However, the overall test time from the fault translations to final manufacturing test is still unacceptable not only because of the lengthy IFA flow but also because of the increased memory capacity, such as in [4]. Thus, the IFA flow makes the memory test more realistic but does not solve the test time challenge especially for testing current and future e-SRAMs with higher capacity. In this paper, functional fault models derived from an IFA flow are applied but simplified to reduce test time. Based on [4], FFM2s and Data Retention Faults are revisited from the defect-level perspective.
2.2 The Simplified FFM2 Fault Class In [4], FFM2 denotes the functional faults involving two memory cells. Most of FFM2s are caused by the bridge defects between two cells. In [4], other defects
such as OC10, SW1, BC2, BC3 and OW can also lead to FFM2s. However, these defects can be detected with FFM1: BC3 and OW can be detected by the functional faults referred to as Incorrect Read Fault (IRF) and Stuck-Open Fault (SOF) respectively, while OC10, SW1 and BC2 can cause stuck-at one functional faults because the all-pass pass transistors cause the fault memory cells to be kept at logic one regardless of the read or write operations at these memory cells. Thus, according to the four cell configuration in [4], FFM2 can be simplified from the five types described in [4] to the following three types, without reducing the defect coverage (we refer to the four-cell configuration to illustrate these fault types): /BL1
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/BL2
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WL1 C1
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Figure 1. Four-cell memory configuration. Row Coupling Faults (RCFs): due to the potential bridges on the same row, the logic states of the two faulty cells (i.e., C1 and C3, or C2 and C4 in Figure 1) are always inverted from their normal/intended state. Column Coupling Faults (CCFs): because of the potential bridges on the same column, the contents of the cells (i.e., C1 and C2, or C3 and C4 in Figure 1) are coupled to the same values. Diagonal Coupling Faults (DCFs): when the potential bridges are on the same diagonal, the corresponding memory cells (i.e., C1 and C4. or C2 and C3 in Figure 1) will always retain the same logic value. After row (column) redundancy activation by the fuse repair, a whole defective row (column) of a memory cell array will be replaced by the redundancy element. Hence, only the redundant rows (columns) instead of the defective rows (columns) of the memory will be accessed subsequently. Normally, the faulty memory cells, the aggressor cell and the victim cell, subject to any one the above three coupling faults needs to be detected and repaired because both of them are assumed to be defective. However, once the redundant row (column) is used to replace that of the aggressor or victim cell, the relationship between the victim or aggressor will not exist because the aggressor or victim cell will cease to be accessed according to the applied redundancy mechanism. In other words, detecting and repairing any one faulty cell of a pair due to bridges are enough for yield improvement if no other defects occur affecting such a memory pair. For example, if C1 and C2 in Figure 1 are faulty only because they are coupled, the achieved yield when detecting and repairing C1 or C2 is
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the same as that when detecting and repairing both, that is, C1 or C2 will become fault-free if one or the other is repaired. In this fashion, not only can test time be shortened, but repair component requirements can also be reduced. Both these factors can reduce test cost.
2.3 Data Retention Fault (DRF) Another type of memory cell fault, namely the Data Retention Fault (DRF), which occurs when a memory cell fails to correctly retain a previously stored logic value after some time, is difficult to simulate using logic level simulators. This type of fault can in practice be detected by performing a read operation after a delay (TD). To reduce the necessary TD for testing DRFs, several Design-for-Test (DFT) techniques have been proposed, e.g., [8] [9] [10]. However, as these entail extra circuitry, they amount to different area penalties. In this paper, not only is the delay time (TD) for detecting such faults reduced using our proposed test algorithm described later, this reduction is also quantified according to various parameters, such as the specifics of the memory under test, test cycle time, specific reading sequence during the testing of DRFs, etc. In general, two different DRFs may occur: Cell inability to retain a logic low after a specific time referred to as TDL Cell inability to retain a logic high after a specific time referred to as TDH DRFs can be caused by a defective source/drain/gate open of the pull-up transistor of the defective cell or by a defective VDD/VSS path. Figure 2 shows one of the Data Retention Fault Models as a resistive open defect in a VSS/pull-down transistor. With this defect, the cell will fail to retain a logic low.
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Figure 2. One DRF Model with a Resistive Open in the VSS/Pull- down Transistor Usually, the final TD (TDF) is the maximum value of TDL and TDH in order to cover all the potential defects. However, because the bit-line will be pre-charged to high before the read operation and the node T in Fig. 2 will be pulled high due to the charge sharing effect by the larger bit line capacitance, reading zero from these cells with a type of defect shown in Figure 2 will flip their contents
to logic one. This DRF circuit level behavior corresponds to that of a Read Destructive Fault (RDF) or a Deceptive Read Destructive Fault (DRDF) in [4]. Therefore, this kind of defect can be detected if both RDF and DRDF have already been detected and the corresponding TDF can only be prescribed by the value of TDH. A shorter TDH will reduce the testing time of DRFs. Moreover, the TD can be further reduced in the proposed test algorithm discussed in detail in Sec. 3. This reduction is possible because of the necessary delay separating write operations to different cells. If the number of memory rows and number of columns are denoted by X and Y respectively, the new final delay time (TDNF) is defined as TDNF = TDF – TDA (1) where, TDA is defined as the re-accessing time of a particular memory cell under test. According to different address sequencing during test, TDA can be quantified according to the following (the period of the test clock during the test is denoted by TP) i) assuming cells are accessed row by row, (2) TDA = TP * (2X – 1) * 2 Y ii) assuming cells are accessed column by column, (3) TDA = TP * (2X – 1) In summary, by combining equation (1), (2) and (3), the TDNF can be chosen according to the following: TDNF = TDF - TP * (2X – 1) * 2Y if a March algorithm with a row by row address sequencing is applied; = TDF - TP * (2X – 1) if a March algorithm following a column by column address sequencing is applied; = TDF for other test algorithms. For all the three cases above, if RDFs and DRDFs in [4] have already been tested then TDF = TDH, otherwise TDF = max (TDL, TDH). Furthermore, from the formulations, the test time can still be reduced because the TDF can even be nullified. For example, the TDNF in testing the memories with 128K words capacity, 9 row addresses and 8 column addresses will not be necessary by using the March row by row address sequencing if the TDF is assumed as 1ms.
3. March 6N Test Algorithms 3.1 Related Work Currently, March 9N [11] is a popular memory test algorithm. From [11], the March 9N with Data Retention Test can be described as shown in Figure 3. In the descriptions of the memory test algorithms, “ ” means the address sequencing is increasing during
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the test, “ ” means the address sequencing is decreasing during the test and delay is the necessary TDNF discussed in Sec. 2. w0
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Figure 3. The March 9N Test Algorithm with Data Retention Test Due to its ability in testing some realistic functional faults, i.e., RDFs, March SRD in [4] is more realistic than March 9N and can thus further improve fault coverage and defect coverage. The description of the March SRD test algorithm is shown in Figure 4. w0
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Figure 4. The March SRD Test Algorithm However, because March SRD is equivalent to a March 14N test algorithm, the testing time is considerably worse than that of the former. Here, the new March 6N test algorithms are proposed to reduce test time while still maintaining the same fault and defect coverage as March SRD.
3.2 The Proposed March 6N Test Algorithms According to the defect analysis of the IFA functional faults in Sec. 2, the same yield can be achieved by row/column redundancy when repairing only one of two faulty cells which are due to bridges between the two cells as that when repairing both. When writing into such faulty memory cells, because the final contents of these two cells is only determined by the cell with the higher address when the writing address sequencing is increasing and by the cell with the lower address when the writing address sequencing is decreasing, only the testing of the FFM2s will be sensitive to the address sequencing, i.e., half of the potential FFM2s could be detected when using the increasing address sequencing and decreasing address sequencing separately (this will be verified in Sec. 4). Thus, either one of the address sequencing coupled with row/column redundancy activation is adequate for meeting the yield goal. This reduces the test time significantly. The proposed March 6N test algorithms are shown in Figure 5 (a) and (b), where either one of the test algorithms with different address sequencing can be applied to achieve the same yield as [4] when coupled with row/column redundancy.
From Figure 5, the proposed March 6N test algorithms reduce the test time to less than half the time required for running the March 9N with Data Retention Test and March SRD in [4]. w0
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Figure 5 The Proposed March 6N Test Algorithms
4. Validation of the Proposed Test Algorithms 4.1 Fault Injections In order to verify the test algorithms, the embedded memory under test (EMUT) of [12] consisting of a 65536 (64K) x32bit SRAM core with 14 row addresses and 2 column addresses is injected with faults. To cover all the defects within a cell, all the functional faults FFM1s involving a single cell in [4] except DRFs were injected for validation. All the simplified FFM2s in this paper were also injected into the EMUT in [12] according to the four cell configuration in Figure 1 and the HDL program shown in Figure 6. // Writing Cells
Case Address // injecting RCFs // Address Difference between // Aggressive and Victim Cells is ONE aggessive cell address: victim cell = inverter (aggressive cell)
// injecting CCFs // Address Difference between // Aggressive and Victim Cells is FOUR aggessive cell address: victim cell = aggressive cell
// injecting DCFs // Address Difference between // Aggressive and Victim Cells is FIVE aggessive cell address: victim cell = aggressive cell
Endcase
Figure 6.Coupling Faults Injections The faults and their addresses which were selected according to the Fig. 1 are shown in Table 1. Data Retention Faults (DRFs) were not injected into the SRAM, but can be detected by reading the cells after TDNF according to the defect analysis in the Sec. 2. In Table 1, all the functional faults caused by the potential defects except DRFs were injected into the
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EMUT. All the defects which have been reported in [4] were covered in all of the functional faults mentioned above. Thus, if all the faults in Table 1 can be detected, the defect coverage and fault coverage can be maintained at the same level as those achieved in [4]. Table 1 Faults Injected into 64Kx32bit SRAM under Test Number Fault Addresses Faults of (Hex) Faults Stuck-at Fault (SAF) 4 00, 03, fd, ff Transition Fault (TF) 4 20, 22, 30, 33 Stuck-Open Fault (SOF) 4 25, 26, 34, 36 Read Destructive Faults 4 50, 53, 59, 5a (RDF) Deceptive Read 4 60, 63, 69, 6a Destructive Fault (DRDF) Incorrect Read Fault 4 70, 73, 79, 7a (IRF) Random Read Fault 4 80, 82, 90, 93 (RRF) Undefined State Fault 4 86, 88, 95, 96 (USF) Aggressor/Victim Coupling RCFs 2 06/07 Fault (CF) CCFs 4 04/08, 10/14 DCFs Total
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4.2 Validation Results The proposed test algorithm was validated under a HDL simulation environment by injecting the entire functional fault FFM1s in [4] except DRFs and the proposed simplified FFM2s and testing the EMUT by using the new March 6N with row by row address sequencing. The detected fault cell addresses are shown in Table 2 when both the proposed test algorithms and injected faults were simulated. Table 2: Detected Fault Cells Using Algorithm (a) Using Algorithm (b) Faults Shown in Figure 5 shown in Figure 5 SAF 00, 03, fd, ff 00, 03, fd, ff TF 20, 22, 30, 33 20, 22, 30, 33 SOF 25, 26, 34, 36 25, 26, 34, 36 RDF 50, 53, 59, 5a 50, 53, 59, 5a DRDF 60, 63, 69, 6a 60, 63, 69, 6a IRF 70, 73, 79, 7a 70, 73, 79, 7a RRF 80, 82, 90, 93 80, 82, 90, 93 USF 86, 88, 95, 96 86, 88, 95, 96 CF 07, 08, 0f, 14, 1b 04, 06, 0a, 10, 16 Total No. 37 37
From Table 2, all the faults and defects under the initial assumptions are detected using both address sequencing. Only the detection of Coupling Faults (CFs) is affected by the address ordering. If row/column redundancy is activated, using one of the two specific address sequencing rather than both suffices to meet yield improvement goals.
4.3 Comparison with March 9N and March SRD The test time of March 9N in Figure 3 can be quantified as (12*2N * TP + 2* TDNF) and the test time of March SRD in [4] can be quantified as (14*2N * TP + 2* TDNF). However, using either of the test algorithm (a) or (b) in Figure 5, the test time of the proposed test algorithms can be reduced to (6*2N * TP + 2* TDNF). Where, N is the memory address number. In [12], the 65536 (64K) x 32 bit SRAM with X = 14 row addresses and Y =2 column addresses is tested using a 10 ns test clock period TP and row-wise test address sequencing. TDH and TDL are 0.5ms and 0.8ms respectively according to the SPICE simulation in [12]. Using formulas in Sec. 2.3, the test time of the three test algorithms is compared and shown in Table 3 according to the quantification results above. Table 3 Comparison Results Test March 9N March SRD March 6N Algorithms TP(ns)/X/Y/N 10/14/2/16 TDH/TDL (ms) 0.5/0.8 TNDF (ms) 0.8 0.8 0 Test Time (ms) 9.46 10.76 3.93 From Table 3, it was found that the test time of our proposed March test algorithm can be reduced up to 58% and 63% of that of the latter respectively when compared with March 9N with Data Retention Test and March SRD in [4]. In summary, our proposed test algorithm is more realistic and efficient in test time compared to those of March 9N with Data Retention Test and it is faster than the March SRD in [4]. Importantly, this speedup is achieved without compromising fault and defect coverage.
5. Conclusions Although an IFA-based test flow allows the establishment of the relationship between the test results and yield and defect levels better than do the methodologies based on traditional functional tests, the test application time challenge, especially arising with increased memory capacity remains. Based on the fault
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models in [4] and further defect analysis, here we simplified FFM2s which can be used to reduce test time by coupling row/column redundancy. The predetermined delay time of DRFs is formulated to test memories more efficiently. By injecting and simulating the IFA functional faults in Table 1, we found that only Coupling Faults detection was dependent on memory address sequencing. The simulation results show that the proposed March 6N test algorithms are efficient in test time when considering the row/column redundancy techniques. For example, for the 65536 (64K) x 32 bit e-SRAM in [12], the test time can be reduced to 58% and 63% of the time required by the March 9N with Data Retention Test and March SRD [4] algorithm, respectively.
6. Acknowledgements We wish to thank NSERC, Micronet and the Canadian Microelectronics Corp for providing support for this work.
7. References [1] Alan Allan, et al. “2001 Technology Roadmap for Semiconductors”, IEEE Computer, pp. 42-53, Vol. 35, No. 1, January 2002. [2] A. J. van de Goor, “Testing Semiconductor Memories, Theory and Practice”, ComTex Publishing, Gouda, the Netherlands, 1998. Web: http://cardit.et.tudelft.nl/~vdgoor [3] J. P. Shen, et al., “Inductive fault analysis of MOS integrated circuits”, IEEE Design and Test of Computers, Vol. 2, No. 6, pp. 13-26, December 1985.
[4] Said Hamdioui, A. J. van de Goor, “An experimental analysis of spot defects in SRAMs: realistic fault models and tests”, Proceedings of the Ninth Asian Test Symposium (ATS2000), pp. 131-138, 2000. [5] T.M Mak, et al., “Cache RAM Inductive Fault Analysis with Fab Defect Modeling,” International Test Conference, pp. 862871, 1998. [6] E. Rondey, Y. Tellier, S. Borri, “A silicon-based yield gain evaluation methodology for embedded-SRAMs with different redundancy scenarios”, Proceedings of the Eighth IEEE International On-Line Testing Workshop, pp. 251 - 255, July 2002. [7] Dong-Chual Kang; Sang-Bock Cho, “An efficient built-in selftest algorithm for neighborhood pattern sensitive faults in highdensity memories”, Proceedings of the 4th Korea-Russia Int'l Symp. on Science and Tech, Vol. 2, 2000, pp. 218 -223. [8] J. Castillejos, V. H. Champac, “A forced-voltage technique to test data retention faults in CMOS SRAM by IDDQ testing”, Proceedings of the 40th Midwest Symposium on Circuits and Systems, Vol. 1, pp. 433 - 436, Aug.1997. [9] V. H. Champac, V. Avendano, M. Linares, “Bit line sensing strategy for testing for data retention faults in CMOS SRAMs”, Electronics Letters, Vol.36, No. 14, pp. 1182-1183, 6 July 2000. [10] A. Meixner, J. Banik, “Weak write test mode: an SRAM cell stability design for test technique”, Proceedings of International Test Conference, pp. 309 -318, Oct. 1996. [11] R. Dekker, et al., “A realistic fault model and test algorithms for static random access memories”, IEEE Transactions on Computer – Aided Design of Integrated Circuits and Systems, Vol. 9, No. 6, pp. 567-572, June 1990. [12] Baosheng Wang, Josh Yang, “SRAM Design and Optimization”, University of British Columbia EECE579 Homework 3, Dec. 2002.
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