_)& 'T21
US008132136B2
(12) United States Patent Bueti et al.
(54)
US 8,132,136 B2
(10) Patent N0.: (45) Date of Patent: (56)
DYNAMIC CRITICAL PATH DETECTOR FOR DIGITAL LOGIC CIRCUIT PATHS
*Mar. 6, 2012
References Cited U.S. PATENT DOCUMENTS
(75) Inventors: Sera?no Bueti, Waterbury, VT (US); Kenneth J. GoodnoW, Essex Junction, VT (US); Todd E. Leonard, Williston,
VT (US); Gregory J. Mann, Win?eld, IL (US); Peter A. Sandon, Essex
5,719,783 A *
2/1998
5,724,250 A *
3/1998 KerZman et a1.
6,114,880 A *
9/2000
6,415,402 B2
7/2002 Bishop et al.
6,516,362 B1*
2/2003
7,941,772 B2 * 2004/0034844 A1*
Junction, VT (US); Peter A. Twombly, Shelbume, VT (US); Charles S.
2005/0007154 A1*
2006/0263913 A1
Buer et al.
.................... .. 327/39
Magro et al. .................. .. 710/58
5/2011 Bueti et a1. 2/2004 Beerel et al. 1/2005
716/106 716/18
Patella et a1. ................... .. 327/2
11/2006 Marshall
Woodruff, Charlotte, VT (US)
(Continued)
(73) Assignee: International Business Machines
FOREIGN PATENT DOCUMENTS
Corporation, Armonk, NY (US) Notice:
KerZman et a1. ................ .. 716/6
99/17186
WO
Subject to any disclaimer, the term of this patent is extended or adjusted under 35
4/1999
OTHER PUBLICATIONS Notice of Allowance dated Jan. 6, 2011, in U.S. Appl. No.
U.S.C. 154(b) by 611 days.
11/834,110.
This patent is subject to a terminal dis claimer.
(Continued) Primary Examiner * Suchin Parihar
(21) Appl. No.: 11/937,111 (22)
Filed:
(74) Attorney, Agent, or Firm * David Cain; Roberts
MlotkoWski Safran & Cole, RC.
Nov. 8, 2007
(57)
(65)
Prior Publication Data
US 2009/0044160 A1
ABSTRACT
Method for correcting timing failures in an integrated circuit and device for monitoring an integrated circuit. The method
Feb. 12, 2009
Related U.S. Application Data
includes placing a ?rst and second latch near a critical path. The ?rst latch has an input comprising a data value on the
(63) Continuation-in-part of application No. 11/834,110,
delayed data value from the data value, latching the delayed
critical path. The method further includes generating a
?led on Aug. 6, 2007.
(51)
Int_ CL
.
G06F 17/50
(52) (58)
data value in the second latch, comparing the data value With the delayed data value to determine Whether the critical path comprises a t1mmg fallure cond1t1on, and executmg a prede termined corrective measure for the critical path. The inven
(200601)
.
.
.
.
.
.
U.S. Cl. ..................................................... .. 716/108 Field of Classi?cation Search .. .. 716/1, 6,
tion is also directed to a design Structure on which a Circuit resides_
71 6/100, 108 See application ?le for complete search history.
20 Claims, 7 Drawing Sheets
Q
\
11
12 .J
Data In
15 J
Latched Data
L1 Clk
L1
L2
C 20
16 J L2 Clk
17-J 13
18
14
Miscompare L1’
—
_)& 19
L2’
‘T21
US 8,132,136 B2 Page 2 US. PATENT DOCUMENTS
OTHER PUBLICATIONS
2007/0164787 Al*
7/2007
Grochowski et a1.
...... .. 326/46
Zoos/0174353 Al*
7/2008 Badar etal‘ “““ “
‘ 327/276
Flnal Of?ce Act10n dated Oct. 14, 2010, 1n U.S. Appl. No.
716/6 . 714/726 . 327/141
11/834,110 _ _ Non-Ful?l Of?ce Actlon dated Jun 16, 2010, m U~$~ APP1~ N~ 11/834,110.
2008/0201671 Al* 8/2008 Rejouan etal. 2008/0307277 Al* 12/2008 Tschanz etal. 2009/0115468 Al* 5/2009 Berthold e161. 2010/0153895 Al*
6/2010
2010/0153896 A1*
6/2010 Sewall et a1. ................... .. 716/6
Tetelbaumetal.
716/6
-
-
_
_
* clted by examlner
-
US. Patent
Mar. 6, 2012
@E283
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Mar. 6, 2012
Sheet 2 on
US 8,132,136 B2
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Sheet 3 of7
US 8,132,136 B2
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US. Patent
Mar. 6, 2012
Sheet 6 of7
US 8,132,136 B2
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9_:0
(12) United States Patent Bueti et al.
(54)
US 8,132,136 B2
(10) Patent N0.: (45) Date of Patent: (56)
DYNAMIC CRITICAL PATH DETECTOR FOR DIGITAL LOGIC CIRCUIT PATHS
*Mar. 6, 2012
References Cited U.S. PATENT DOCUMENTS
(75) Inventors: Sera?no Bueti, Waterbury, VT (US); Kenneth J. GoodnoW, Essex Junction, VT (US); Todd E. Leonard, Williston,
VT (US); Gregory J. Mann, Win?eld, IL (US); Peter A. Sandon, Essex
5,719,783 A *
2/1998
5,724,250 A *
3/1998 KerZman et a1.
6,114,880 A *
9/2000
6,415,402 B2
7/2002 Bishop et al.
6,516,362 B1*
2/2003
7,941,772 B2 * 2004/0034844 A1*
Junction, VT (US); Peter A. Twombly, Shelbume, VT (US); Charles S.
2005/0007154 A1*
2006/0263913 A1
Buer et al.
.................... .. 327/39
Magro et al. .................. .. 710/58
5/2011 Bueti et a1. 2/2004 Beerel et al. 1/2005
716/106 716/18
Patella et a1. ................... .. 327/2
11/2006 Marshall
Woodruff, Charlotte, VT (US)
(Continued)
(73) Assignee: International Business Machines
FOREIGN PATENT DOCUMENTS
Corporation, Armonk, NY (US) Notice:
KerZman et a1. ................ .. 716/6
99/17186
WO
Subject to any disclaimer, the term of this patent is extended or adjusted under 35
4/1999
OTHER PUBLICATIONS Notice of Allowance dated Jan. 6, 2011, in U.S. Appl. No.
U.S.C. 154(b) by 611 days.
11/834,110.
This patent is subject to a terminal dis claimer.
(Continued) Primary Examiner * Suchin Parihar
(21) Appl. No.: 11/937,111 (22)
Filed:
(74) Attorney, Agent, or Firm * David Cain; Roberts
MlotkoWski Safran & Cole, RC.
Nov. 8, 2007
(57)
(65)
Prior Publication Data
US 2009/0044160 A1
ABSTRACT
Method for correcting timing failures in an integrated circuit and device for monitoring an integrated circuit. The method
Feb. 12, 2009
Related U.S. Application Data
includes placing a ?rst and second latch near a critical path. The ?rst latch has an input comprising a data value on the
(63) Continuation-in-part of application No. 11/834,110,
delayed data value from the data value, latching the delayed
critical path. The method further includes generating a
?led on Aug. 6, 2007.
(51)
Int_ CL
.
G06F 17/50
(52) (58)
data value in the second latch, comparing the data value With the delayed data value to determine Whether the critical path comprises a t1mmg fallure cond1t1on, and executmg a prede termined corrective measure for the critical path. The inven
(200601)
.
.
.
.
.
.
U.S. Cl. ..................................................... .. 716/108 Field of Classi?cation Search .. .. 716/1, 6,
tion is also directed to a design Structure on which a Circuit resides_
71 6/100, 108 See application ?le for complete search history.
20 Claims, 7 Drawing Sheets
Q
\
11
12 .J
Data In
15 J
Latched Data
L1 Clk
L1
L2
C 20
16 J L2 Clk
17-J 13
18
14
Miscompare L1’
—
_)& 19
L2’
‘T21
US 8,132,136 B2 Page 2 US. PATENT DOCUMENTS
OTHER PUBLICATIONS
2007/0164787 Al*
7/2007
Grochowski et a1.
...... .. 326/46
Zoos/0174353 Al*
7/2008 Badar etal‘ “““ “
‘ 327/276
Flnal Of?ce Act10n dated Oct. 14, 2010, 1n U.S. Appl. No.
716/6 . 714/726 . 327/141
11/834,110 _ _ Non-Ful?l Of?ce Actlon dated Jun 16, 2010, m U~$~ APP1~ N~ 11/834,110.
2008/0201671 Al* 8/2008 Rejouan etal. 2008/0307277 Al* 12/2008 Tschanz etal. 2009/0115468 Al* 5/2009 Berthold e161. 2010/0153895 Al*
6/2010
2010/0153896 A1*
6/2010 Sewall et a1. ................... .. 716/6
Tetelbaumetal.
716/6
-
-
_
_
* clted by examlner
-
US. Patent
Mar. 6, 2012
@E283
Sheet 1 on
5
cm
SLi
NF \\
US 8,132,136 B2
3 \\|
28503 .mNi_l
2
2
W
/3
3
3x63
5She
Wm? W8 .12 V62
W2 é?
.92 P
US. Patent
Mar. 6, 2012
Sheet 2 on
US 8,132,136 B2
U
Tl +1:.5 N
38mi9:5
_‘V504 She5
8952mm
Emao E
c_Ema
sEEimgam
EmaoQE
US. Patent
Mar. 6, 2012
Sheet 3 of7
US 8,132,136 B2
w5mm
:E mO mcotcké
E5
.5 w
E0“.
US. Patent
Mar. 6, 2012
Sheet 6 of7
US 8,132,136 B2
H.‘wo\n M$c2o6z m.0 EcEm0s5;2 £3m2czm _.5 N
Ec5o:sOm0éE?3o
9_:0
