32.3 Impact of Random Telegraph Signals on Vmin in 45nm SRAM
Impact of Random Telegraph Signals on Vmin in 45nm SRAM
Seng Oon Toh, Yasumasa Tsukamoto† , Zheng Guo, Lauren Jones, Tsu-Jae King Liu, and Borivoje Nikoli´c Dept. of Electrical Engineering and Computer Sciences, University of California, Berkeley 94720, USA † Renesas Technology Corp., 4-1, Mizuhara, Itami, Hyogo, 664-0005, Japan
20x60 SRAM Macro
(c)
TESTED CELL 8 6 9 10 2 1 3
5
7
DUMMY CELL
I NTRODUCTION Large temporal fluctuations of threshold voltage (Vth ) in highly scaled CMOS transistors have been reported and attributed to random telegraph signals (RTS) [1, 2]. This paper presents a measurement technique for sampling worst-case Vth variation due to RTS. This technique is used to characterize RTS amplitude distributions in SRAM transistors of the 45nm technology. A padded-out SRAM cell array is utilized to extract RTS-induced fluctuations in SRAM write margin as well as to identify the transistors that contribute the most to write-margin fluctuation. Finally, a numerical method is developed to estimate Vmin degradation for write operation in large SRAM arrays. This method is validated using Vmin measurement data for a 64kb SRAM array. E XPERIMENTAL S ETUP A 6T SRAM testchip is fabricated in an industrial 45nm CMOS process with 0.252μm2 bit-cells. The testchip contains four 64kb SRAM arrays as well as a macro with internal nodes of 160 cells padded out through a switch network (Fig. 1) [3]. Source-meters are used to access these internal nodes using precision 4-terminal Kelvin sensing methods to accurately set voltages at all nodes. RTS measurements are conducted at a sampling rate of 60 Hz. The SRAM array is used for measuring Vmin while the SRAM macro is used for measuring Ids and Iwrite . A LTERNATING -B IAS RTS M EASUREMENT T ECHNIQUE RTS amplitude measurements are conventionally [1, 2] performed by measuring the drain current (Ids ) of the transistor under a constant gate bias. Long measurement periods are required to observe RTS-related fluctuations caused by deep traps with long time constants. This makes it prohibitive to analyze a large population of transistors, to obtain statistics necessary for estimation of the properties of large SRAM arrays. A measurement technique is therefore introduced to accelerate the oxide trapping and de-trapping processes by
97-4244-5640-6/09/$26.00 ©2009 IEEE
DUMMY CELL
SRAM Cell Under Test
DUMMY CELL
DUMMY CELL
4 DUMMY CELL
DUMMY CELL
TESTED CELL 8 6 9 10 2 1 3
5
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4
Sweep
Large SRAM Array
Switch Network
An alternating-bias random telegraph signal (RTS) characterization technique is presented, which shortens measurement time by 10x and also produces more accurate statistical distributions of RTS amplitudes. Measurements of RTS amplitudes in 45nm SRAM transistor Ids and cell write margin are reported and used to demonstrate a complex dependence of write margin on RTS in multiple transistors. Fail bit rate of SRAM with RTS is estimated using a statistical model populated by Iwrite measurements. Statistical analysis indicates a Vmin degradation of less than 50 mV due to RTS.
(b)
Source Measure Source Meter
Measure
(a)
A BSTRACT
Source Measure
SRAM Macro 20x60
Fig. 1. (a) Die photo of the testchip. (b) Layout sketch of the padded out SRAM cell with poly connection for accessing internal nodes. (c) Experimental setup for the padded out cell RTS measurement.
pulsing the gate bias to a high stress voltage (Vstress ) prior to sampling the current, and subsequently to a negative voltage (Vaccumulation ) prior to sampling the current (Fig. 2). Gate biases of Vstress and Vaccumulation force trapping and detrapping of the oxide trap. The trap remains occupied/empty even though stress voltage is removed because instantaneous trap occupancy converges to a new steady-state value as a decaying exponential [4]. Fig. 3 plots the drain currents measured using this technique, demonstrating the 10x decrease in measurement time required to observe similar RTS fluctuation. Figs. 4 and 5 compare the statistical distributions of Ids , as measured with constant time using the conventional and proposed techniques. A significant difference between the statistical distributions obtained from these two techniques is observed in the bulk of the distributions. The conventional technique underestimates the magnitude of RTS fluctuations in the bulk of the distribution due to insufficient measurement period. Alternately, measurement period of the conventional technique can be increased while sacrificing the sample population that can be collected within a reasonable amount of time. RTS IN 45 NM SRAM T RANSISTORS Fig. 6 plots statistical distributions of RTS amplitudes that are measured from transistors in SRAM cells. The ≥ 4x difference in RTS amplitudes between PMOS and NMOS devices can be explained by the difference in the capture cross-section between electrons and holes [2]. The pull-down
32.3.1
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Gate
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x 10
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N = 320
0.999
0.997
0.001
Fig. 3. Drain current of the same transistor measured using conventional and alternating-bias techniques. It takes 32s for a trap to be occupied in the conventional technique. By applying an initial 0.5ms gate stress before measurement, the trap is occupied from the start of the experiment.
0.01
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Fig. 6. Gumbel plots of normalized RTS fluctuations in drain currents, measured from transistors in the padded-out SRAM cells.
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Cumulative Probability
Alternating−Bias Lognormal Fit
Fig. 5. Histogram and lognormal distribution fits of RTS Ids fluctuations measured using conventional and alternating-bias techniques with constant time. The presented technique provides a more accurate sampling of the worstcase RTS amplitude, especially in the bulk of the distribution.
x 10
1.225 0
40
0 0
Waveforms of the alternating-bias technique.
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Conventional Lognormal Fit
20
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Source
0.997 0.99 0.98 0.95 0.9 0.5
Alternating−Bias
0.1 0.001
Conventional 0.5
1
δ Ids
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Fig. 4. Gumbel plots of RTS drain current fluctuations measured using conventional and alternating-bias techniques with constant time.
transistors exhibit slightly larger RTS amplitudes compared to the pass-gate transistors even though the larger effective area transistor should have a smaller fluctuation (Eqn. 1) [5]. A similar trend is also reported in [1]. This discrepancy is partially due to a 6% higher mobility in the pass-gate devices compared to the pull-down devices. 1 δN 1 1 δμ δId (1) = ± Id Wef f × Lef f N δNT μ δNT I MPACT OF RTS ON SRAM W RITE M ARGIN The Iwrite metric, derived from write N-curves [6] is used to characterize write margin fluctuation of the SRAM cells caused by RTS (Fig. 7-8). An SRAM cell requires a positive Iwrite to be writeable. This current-based metric is favored
IEDM09-768
over voltage-based metrics, such as wordline and bitline write metrics [3], because the measured margin fluctuations can be easily correlated with drain current fluctuations observed in the transistors. Fig. 9 plots the RTS in Iwrite and its constituents, measured from one cell. Although PU5 contributes a small amount to the N-curve current, its RTS is reflected in Iwrite because RTS amplitudes are much larger for the PMOS transistors than for the NMOS transistors (Fig. 6). Fig. 10 plots the statistical distributions of nominal Iwrite and RTS at two operating voltages. Worst-case fluctuations in Iwrite are extracted by applying stress voltages to the pass-gate and pull-up transistors before measurement. These results indicate that RTS in SRAM write margin is dependent on both bias and RTS in multiple transistors, and requires a more accurate model than fixed shifts in Vth [2] or single transistor RTS [7]. FAIL B IT R ATE (FBR) E STIMATION A statistical model of SRAM write failure is developed in order to estimate the impact of RTS on write margin in large arrays. Measured nominal Iwrite data is fitted to a normal distribution while RTS fluctuation data is fitted to a hybrid distribution (Fig. 11). This hybrid distribution allows accurate modeling of both the bulk and tail of the distribution. The joint probability density function (PDF) of these two distributions is obtained through numerical analysis (Fig. 12-13). The most probable failure point (MPFP) corresponds to the point in the design space where the first failure is likely to occur. The FBR
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Fig. 8. Currents contributing to Iwrite . The Iwrite metric corresponds to the minimum point of the N-curve after the peak. It measures the relative strengths of PG3 and PD1 compared to PU5 during the critical phase of the write operation.
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Fig. 12. Scatter plots of measured nominal Iwrite and RTS fluctuation at nominal and low operating voltages. The RTS amplitude appears to be uncorrelated with nominal Iwrite values.
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Voltage at CL (V)
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Standard Normal Quantiles
0.4
x 10
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Fig. 11. (a) Quantile-quantile plot of Iwrite with normal distribution fit. (b) Quantile-quantile plot of RTS fluctuation in Iwrite with hybrid distribution fit. The bulk of the distribution is fitted using a log-normal distribution while data above a certain threshold is fitted to a generalized pareto distribution. Accurate fitting of the tail of the distribution is critical for estimating RTSinduced fluctuation in large arrays.
δ Iwrite / σ
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Fig. 10. (a) Histogram of nominal Iwrite . (b) Gumbel plots of Iwrite RTS fluctuation. The Maximum RTS amplitude normalized to σIwrite at each operating voltage does not change significantly, although the shape of the distribution changes.
Fig. 7. Schematic of Iwrite measurement. The N-curve is the sum of the currents flowing out of the internal node.
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80
5.9 0.275 0.2748 0.2746 0.2744 0
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Time (s)
5
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Fig. 9. Currents and voltages measured from padded-out SRAM cell with RTS. RTS characteristics of the N-curve are influenced by RTS in both PU5 and PG3. Voltage fluctuation at node CL is minimal due to the low impedance of this node.
fluctuation despite the different shapes of the joint PDFs. The proximity of the MPFP to small values of RTS fluctuation highlights the importance of modeling an accurate RTS fluctuation distribution in the bulk. The alternating-bias technique provides this accurate model. FBR AND Vmin D EGRADATION
of the SRAM is calculated by integrating the joint PDF up to the boundary defined by the probability corresponding to the MPFP. Figs. 13 and 14 plot the joint PDFs, estimated based on measured Iwrite at nominal and low operating voltages. The MPFP of both operating conditions occurs within the same region, characterized by low nominal Iwrite and small RTS
The FBR of the SRAM cell is estimated at different voltages based on statistical distributions fitted to measured data (Fig. 15). The FBR degradation by RTS at the nominal voltage is minimal even in large SRAM arrays (10σ) because the MPFP is dominated by the bulk of the RTS fluctuation distributions rather than the tail. Vmin degradation is estimated from Fig. 15 by observing the increase in Vdd required to maintain a
32.3.3
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0.01 write
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Fig. 13. Joint probability density function of nominal Iwrite and RTS fluctuation at nominal Vdd . The MPFP is found by tracing the write failure contour and finding the point with the highest probability.
0.34
0.36
0.38
0.4
0.42
0.44
(Normalized to Nominal Operating Volage)
Fig. 16. Measured fail bit count of a 64kb SRAM array. Fail bit count measures the number of cells with Vmin greater than a corresponding voltage. Extrapolation of fail bit count to 100 estimates the largest Vmin in the array. Measured Vmin degradation is less than 50 mV.
6 0.45
Failure : Iwrite − δ Iwrite < 0
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C ONCLUSION 5
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/σ
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Fig. 14. Joint probability density function of nominal Iwrite and RTS fluctuation at low Vdd .
Statistical analysis confirmed by measurements indicates that Vmin degradation due to RTS is less than 50 mV, even in the presence of large RTS fluctuations. Furthermore, degradation due to RTS becomes less significant in larger SRAM arrays. To demonstrate this, a measurement technique to accelerate RTS testing is presented. Measurements of worstcase RTS amplitudes in 45nm SRAM transistor Ids and cell Iwrite show the complex dependence of write margin on RTS in multiple transistors. Vmin degradation is numerically estimated based on the joint distribution of nominal Iwrite and RTS amplitude and shows good agreement with experimental data. ACKNOWLEDGMENT
3
Fail Bit Rate (σ)
This work was supported by the Center for Circuit & System Solutions (C2S2) Focus Center, one of five research centers funded under the Focus Center Research Program, a Semiconductor Research Corporation program and the National Science Foundation Infrastructure Grant No. 040342. Chip fabrication was donated by STMicroelectronics. Andrew Carlson contributed to the chip design.
No RTS
4 64kb Array 5
With RTS
6 7 8
0.04 (a.u.)
9 10 0.65
R EFERENCES 0.7
0.75
0.8
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Vdd (Normalized to Nominal Operating Voltage)
1
Fig. 15. FBR of SRAM at different voltages. FBR increases by 0.6σ at low voltages and 0.2σ at nominal operating voltage. Vmin is degraded by less than 50mV for small arrays (4σ) and is not significant in large arrays.
similar FBR. The estimated Vmin degradation corresponding to a 64kb SRAM array is experimentally verified by measuring Vmin fluctuation in an actual array. The minimum (nominal) and maximum Vmin values of each cell is measured and illustrated in Fig. 16 as fail bit count. Measured results (0.04 a.u.) matches estimated Vmin degradation. Mismatch in the absolute Vmin values between these two figures is caused by layout-induced differences between the 64kb SRAM arrays and the SRAM macros used for Iwrite measurements [3].
IEDM09-770
[1] N. Tega et al., VLSI Tech. Technical Digest, pp. 50–51, 2009. [2] N. Tega et al., IRPS Technical Digest, pp. 541–546, 2008. [3] Z. Guo, A. Carlson, L. T. Pang, K. Duong, T. J. King Liu, and B. Nikolic, VLSI Circ. Technical Digest, pp. 42–43, 2008. [4] J. Kolhatkar et al., IEDM Technical Digest, pp. 759–762, 2004. [5] K. Hung, P. Ko, C. Hu, and Y. Cheng, IEEE Electron Device Letters, pp. 90–92, 1990. [6] A. Carlson, Z. Guo, S. Balasubramanian, L. T. Pang, T. J. King Liu, and B. Nikolic, IEEE SOI Conference Proceedings, pp. 105–106, Oct. 2006. [7] K. Fukuda, Y. Shimizu, K. Amemiya, M. Kamoshida, and C. Hu, IEDM Technical Digest, pp. 169–172, 2007.
32.3.4
Seng Oon Toh, Yasumasa Tsukamoto† , Zheng Guo, Lauren Jones, Tsu-Jae King Liu, and Borivoje Nikoli´c Dept. of Electrical Engineering and Computer Sciences, University of California, Berkeley 94720, USA † Renesas Technology Corp., 4-1, Mizuhara, Itami, Hyogo, 664-0005, Japan
20x60 SRAM Macro
(c)
TESTED CELL 8 6 9 10 2 1 3
5
7
DUMMY CELL
I NTRODUCTION Large temporal fluctuations of threshold voltage (Vth ) in highly scaled CMOS transistors have been reported and attributed to random telegraph signals (RTS) [1, 2]. This paper presents a measurement technique for sampling worst-case Vth variation due to RTS. This technique is used to characterize RTS amplitude distributions in SRAM transistors of the 45nm technology. A padded-out SRAM cell array is utilized to extract RTS-induced fluctuations in SRAM write margin as well as to identify the transistors that contribute the most to write-margin fluctuation. Finally, a numerical method is developed to estimate Vmin degradation for write operation in large SRAM arrays. This method is validated using Vmin measurement data for a 64kb SRAM array. E XPERIMENTAL S ETUP A 6T SRAM testchip is fabricated in an industrial 45nm CMOS process with 0.252μm2 bit-cells. The testchip contains four 64kb SRAM arrays as well as a macro with internal nodes of 160 cells padded out through a switch network (Fig. 1) [3]. Source-meters are used to access these internal nodes using precision 4-terminal Kelvin sensing methods to accurately set voltages at all nodes. RTS measurements are conducted at a sampling rate of 60 Hz. The SRAM array is used for measuring Vmin while the SRAM macro is used for measuring Ids and Iwrite . A LTERNATING -B IAS RTS M EASUREMENT T ECHNIQUE RTS amplitude measurements are conventionally [1, 2] performed by measuring the drain current (Ids ) of the transistor under a constant gate bias. Long measurement periods are required to observe RTS-related fluctuations caused by deep traps with long time constants. This makes it prohibitive to analyze a large population of transistors, to obtain statistics necessary for estimation of the properties of large SRAM arrays. A measurement technique is therefore introduced to accelerate the oxide trapping and de-trapping processes by
97-4244-5640-6/09/$26.00 ©2009 IEEE
DUMMY CELL
SRAM Cell Under Test
DUMMY CELL
DUMMY CELL
4 DUMMY CELL
DUMMY CELL
TESTED CELL 8 6 9 10 2 1 3
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An alternating-bias random telegraph signal (RTS) characterization technique is presented, which shortens measurement time by 10x and also produces more accurate statistical distributions of RTS amplitudes. Measurements of RTS amplitudes in 45nm SRAM transistor Ids and cell write margin are reported and used to demonstrate a complex dependence of write margin on RTS in multiple transistors. Fail bit rate of SRAM with RTS is estimated using a statistical model populated by Iwrite measurements. Statistical analysis indicates a Vmin degradation of less than 50 mV due to RTS.
(b)
Source Measure Source Meter
Measure
(a)
A BSTRACT
Source Measure
SRAM Macro 20x60
Fig. 1. (a) Die photo of the testchip. (b) Layout sketch of the padded out SRAM cell with poly connection for accessing internal nodes. (c) Experimental setup for the padded out cell RTS measurement.
pulsing the gate bias to a high stress voltage (Vstress ) prior to sampling the current, and subsequently to a negative voltage (Vaccumulation ) prior to sampling the current (Fig. 2). Gate biases of Vstress and Vaccumulation force trapping and detrapping of the oxide trap. The trap remains occupied/empty even though stress voltage is removed because instantaneous trap occupancy converges to a new steady-state value as a decaying exponential [4]. Fig. 3 plots the drain currents measured using this technique, demonstrating the 10x decrease in measurement time required to observe similar RTS fluctuation. Figs. 4 and 5 compare the statistical distributions of Ids , as measured with constant time using the conventional and proposed techniques. A significant difference between the statistical distributions obtained from these two techniques is observed in the bulk of the distributions. The conventional technique underestimates the magnitude of RTS fluctuations in the bulk of the distribution due to insufficient measurement period. Alternately, measurement period of the conventional technique can be increased while sacrificing the sample population that can be collected within a reasonable amount of time. RTS IN 45 NM SRAM T RANSISTORS Fig. 6 plots statistical distributions of RTS amplitudes that are measured from transistors in SRAM cells. The ≥ 4x difference in RTS amplitudes between PMOS and NMOS devices can be explained by the difference in the capture cross-section between electrons and holes [2]. The pull-down
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Fig. 3. Drain current of the same transistor measured using conventional and alternating-bias techniques. It takes 32s for a trap to be occupied in the conventional technique. By applying an initial 0.5ms gate stress before measurement, the trap is occupied from the start of the experiment.
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ds
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Fig. 6. Gumbel plots of normalized RTS fluctuations in drain currents, measured from transistors in the padded-out SRAM cells.
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Fig. 5. Histogram and lognormal distribution fits of RTS Ids fluctuations measured using conventional and alternating-bias techniques with constant time. The presented technique provides a more accurate sampling of the worstcase RTS amplitude, especially in the bulk of the distribution.
x 10
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Waveforms of the alternating-bias technique.
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Fig. 4. Gumbel plots of RTS drain current fluctuations measured using conventional and alternating-bias techniques with constant time.
transistors exhibit slightly larger RTS amplitudes compared to the pass-gate transistors even though the larger effective area transistor should have a smaller fluctuation (Eqn. 1) [5]. A similar trend is also reported in [1]. This discrepancy is partially due to a 6% higher mobility in the pass-gate devices compared to the pull-down devices. 1 δN 1 1 δμ δId (1) = ± Id Wef f × Lef f N δNT μ δNT I MPACT OF RTS ON SRAM W RITE M ARGIN The Iwrite metric, derived from write N-curves [6] is used to characterize write margin fluctuation of the SRAM cells caused by RTS (Fig. 7-8). An SRAM cell requires a positive Iwrite to be writeable. This current-based metric is favored
IEDM09-768
over voltage-based metrics, such as wordline and bitline write metrics [3], because the measured margin fluctuations can be easily correlated with drain current fluctuations observed in the transistors. Fig. 9 plots the RTS in Iwrite and its constituents, measured from one cell. Although PU5 contributes a small amount to the N-curve current, its RTS is reflected in Iwrite because RTS amplitudes are much larger for the PMOS transistors than for the NMOS transistors (Fig. 6). Fig. 10 plots the statistical distributions of nominal Iwrite and RTS at two operating voltages. Worst-case fluctuations in Iwrite are extracted by applying stress voltages to the pass-gate and pull-up transistors before measurement. These results indicate that RTS in SRAM write margin is dependent on both bias and RTS in multiple transistors, and requires a more accurate model than fixed shifts in Vth [2] or single transistor RTS [7]. FAIL B IT R ATE (FBR) E STIMATION A statistical model of SRAM write failure is developed in order to estimate the impact of RTS on write margin in large arrays. Measured nominal Iwrite data is fitted to a normal distribution while RTS fluctuation data is fitted to a hybrid distribution (Fig. 11). This hybrid distribution allows accurate modeling of both the bulk and tail of the distribution. The joint probability density function (PDF) of these two distributions is obtained through numerical analysis (Fig. 12-13). The most probable failure point (MPFP) corresponds to the point in the design space where the first failure is likely to occur. The FBR
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Fig. 8. Currents contributing to Iwrite . The Iwrite metric corresponds to the minimum point of the N-curve after the peak. It measures the relative strengths of PG3 and PD1 compared to PU5 during the critical phase of the write operation.
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Fig. 12. Scatter plots of measured nominal Iwrite and RTS fluctuation at nominal and low operating voltages. The RTS amplitude appears to be uncorrelated with nominal Iwrite values.
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Standard Normal Quantiles
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x 10
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Fig. 11. (a) Quantile-quantile plot of Iwrite with normal distribution fit. (b) Quantile-quantile plot of RTS fluctuation in Iwrite with hybrid distribution fit. The bulk of the distribution is fitted using a log-normal distribution while data above a certain threshold is fitted to a generalized pareto distribution. Accurate fitting of the tail of the distribution is critical for estimating RTSinduced fluctuation in large arrays.
δ Iwrite / σ
N−curve (A)
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Fig. 10. (a) Histogram of nominal Iwrite . (b) Gumbel plots of Iwrite RTS fluctuation. The Maximum RTS amplitude normalized to σIwrite at each operating voltage does not change significantly, although the shape of the distribution changes.
Fig. 7. Schematic of Iwrite measurement. The N-curve is the sum of the currents flowing out of the internal node.
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5
0.99 0.98
/σ
PG4
40
0.997
write
PU6
Count
PU5
Cumulative Probability
80
5.9 0.275 0.2748 0.2746 0.2744 0
1
2
3
4
Time (s)
5
6
7
8
9
Fig. 9. Currents and voltages measured from padded-out SRAM cell with RTS. RTS characteristics of the N-curve are influenced by RTS in both PU5 and PG3. Voltage fluctuation at node CL is minimal due to the low impedance of this node.
fluctuation despite the different shapes of the joint PDFs. The proximity of the MPFP to small values of RTS fluctuation highlights the importance of modeling an accurate RTS fluctuation distribution in the bulk. The alternating-bias technique provides this accurate model. FBR AND Vmin D EGRADATION
of the SRAM is calculated by integrating the joint PDF up to the boundary defined by the probability corresponding to the MPFP. Figs. 13 and 14 plot the joint PDFs, estimated based on measured Iwrite at nominal and low operating voltages. The MPFP of both operating conditions occurs within the same region, characterized by low nominal Iwrite and small RTS
The FBR of the SRAM cell is estimated at different voltages based on statistical distributions fitted to measured data (Fig. 15). The FBR degradation by RTS at the nominal voltage is minimal even in large SRAM arrays (10σ) because the MPFP is dominated by the bulk of the RTS fluctuation distributions rather than the tail. Vmin degradation is estimated from Fig. 15 by observing the increase in Vdd required to maintain a
32.3.3
IEDM09-769
0.01 write
0.5
− δ Iwrite < 0
Joint PDF I =0 write
0.008
3.8e−22
δ Iwrite / σ
0.4 3.8e−10
0.006
0.3 1e−4
0.004
0.2
10
Nominal Fit Maximum Maximum Fit
1
10
0.04 (a.u.)
0.002
MPFP
0.1
Nominal 2
Fail Bit Count (N)
Failure : I
0
10 0
2
4
6
8
10
Iwrite / σ
12
14
16
18
20
0
0.3
0.32
V
min
Fig. 13. Joint probability density function of nominal Iwrite and RTS fluctuation at nominal Vdd . The MPFP is found by tracing the write failure contour and finding the point with the highest probability.
0.34
0.36
0.38
0.4
0.42
0.44
(Normalized to Nominal Operating Volage)
Fig. 16. Measured fail bit count of a 64kb SRAM array. Fail bit count measures the number of cells with Vmin greater than a corresponding voltage. Extrapolation of fail bit count to 100 estimates the largest Vmin in the array. Measured Vmin degradation is less than 50 mV.
6 0.45
Failure : Iwrite − δ Iwrite < 0
Joint PDF Iwrite = 0
0.4
δI
write
/σ
0.35
C ONCLUSION 5
0.005
0.3
0.05
4
0.2
3
0.25 0.2 0.15 0.1
2
0.05 0
MPFP 0
1
2
3
I
4
write
/σ
5
6
1
7
Fig. 14. Joint probability density function of nominal Iwrite and RTS fluctuation at low Vdd .
Statistical analysis confirmed by measurements indicates that Vmin degradation due to RTS is less than 50 mV, even in the presence of large RTS fluctuations. Furthermore, degradation due to RTS becomes less significant in larger SRAM arrays. To demonstrate this, a measurement technique to accelerate RTS testing is presented. Measurements of worstcase RTS amplitudes in 45nm SRAM transistor Ids and cell Iwrite show the complex dependence of write margin on RTS in multiple transistors. Vmin degradation is numerically estimated based on the joint distribution of nominal Iwrite and RTS amplitude and shows good agreement with experimental data. ACKNOWLEDGMENT
3
Fail Bit Rate (σ)
This work was supported by the Center for Circuit & System Solutions (C2S2) Focus Center, one of five research centers funded under the Focus Center Research Program, a Semiconductor Research Corporation program and the National Science Foundation Infrastructure Grant No. 040342. Chip fabrication was donated by STMicroelectronics. Andrew Carlson contributed to the chip design.
No RTS
4 64kb Array 5
With RTS
6 7 8
0.04 (a.u.)
9 10 0.65
R EFERENCES 0.7
0.75
0.8
0.85
0.9
0.95
Vdd (Normalized to Nominal Operating Voltage)
1
Fig. 15. FBR of SRAM at different voltages. FBR increases by 0.6σ at low voltages and 0.2σ at nominal operating voltage. Vmin is degraded by less than 50mV for small arrays (4σ) and is not significant in large arrays.
similar FBR. The estimated Vmin degradation corresponding to a 64kb SRAM array is experimentally verified by measuring Vmin fluctuation in an actual array. The minimum (nominal) and maximum Vmin values of each cell is measured and illustrated in Fig. 16 as fail bit count. Measured results (0.04 a.u.) matches estimated Vmin degradation. Mismatch in the absolute Vmin values between these two figures is caused by layout-induced differences between the 64kb SRAM arrays and the SRAM macros used for Iwrite measurements [3].
IEDM09-770
[1] N. Tega et al., VLSI Tech. Technical Digest, pp. 50–51, 2009. [2] N. Tega et al., IRPS Technical Digest, pp. 541–546, 2008. [3] Z. Guo, A. Carlson, L. T. Pang, K. Duong, T. J. King Liu, and B. Nikolic, VLSI Circ. Technical Digest, pp. 42–43, 2008. [4] J. Kolhatkar et al., IEDM Technical Digest, pp. 759–762, 2004. [5] K. Hung, P. Ko, C. Hu, and Y. Cheng, IEEE Electron Device Letters, pp. 90–92, 1990. [6] A. Carlson, Z. Guo, S. Balasubramanian, L. T. Pang, T. J. King Liu, and B. Nikolic, IEEE SOI Conference Proceedings, pp. 105–106, Oct. 2006. [7] K. Fukuda, Y. Shimizu, K. Amemiya, M. Kamoshida, and C. Hu, IEDM Technical Digest, pp. 169–172, 2007.
32.3.4
