8. A Design Example: Digital Alarm Clock
Digital Logic Design and Analysis
c August 1998 ptb,kr
8. A Design Example: Digital Alarm Clock Poras T. Balsara and Kamlesh Rath
8.1
Department of Electrical Engineering The University of Texas at Dallas
A Design Example: Digital Alarm Clock
Simulation results
Design details
Overall architecture
Speci cations and usage
General design Methodology
Digital Alarm Clock Design
A Design Example: Digital Alarm Clock
8.2
c August 1998 ptb,kr
General Design Methodology
8.3
c August 1998 ptb,kr
Top-down vs Bottom-up design methodology. Proceed in a top-down fashion starting with a high level speci cation of the system to be designed. Develop a top level architecture block diagram. Determine speci cations of building blocks and interface among di erent blocks. Design building blocks by going down the hierarchy till you reach the most primitive blocks, i.e., combinational logic gates and ip- ops in this design environment. Design and thoroughly simulate the most basic blocks using the primitive components. Build next (higher) level blocks using the above basic blocks, simulating thoroughly at each level { Bottom-up design process.
A Design Example: Digital Alarm Clock
Speci cations and Usage
Digital clock with alarm. Displays hours and minutes in 12 hour mode with AM/PM and Alarm ON LED indicators. Push button switches to set time of day and alarm time. Push button switches to set hours and minutes. Push button switch that toggles alarm on or o and a speaker to provide an audible tone when alarm goes o . Hours Set_Time
Minutes Alarm on/off
Set_Alarm Speaker AM/PM
Alarm on/off LED
A Design Example: Digital Alarm Clock
8.4
c August 1998 ptb,kr
8.5
c August 1998 ptb,kr
To set time of day: { Press Set Time push button switch and { Push Hours switch to modify Hours display or Minutes switch to modify Minutes display. { Release Set Time switch to continue normal operation. { Each push of Hours or Minutes switch will increment the corresponding display by one. { Hours and Minutes switches should not be operated at the same time. To set alarm time: { Press Set Alarm and switch and use Hours and Minutes switches as mentioned above to set alarm time. { Release Set Alarm switch. { In order to turn-on the alarm push the Alarm on/o switch once. Pushing it again will turn-o the alarm. { Once the alarm goes o it can be shut only by pushing the Alarm on/o switch.
A Design Example: Digital Alarm Clock
Overall Architecture
8.6
c August 1998 ptb,kr
of this design are from the Synopsys VSS Family Tutorials, ver 3.3
There are two distinct components in this designa : (a) clock time circuit, and (b) alarm time circuit. These blocks generate data for hours, minutes and AM/PM displays. There is no need to display alarm time all the time. It should be displayed only when alarm time is being set. At all other times clock time is displayed. This is achieved by multiplexing the data outputs from the clock time and alarm time circuits using Set Alarm as control input. Since the display devices are 7-Segment LED displays there is a need for either a binary-to-7-segment or a BCD-to-7-segment converter. A magnitude comparator is needed to compare the clock and alarm times and to generate a signal which can turn on an alarm ringer if the alarm was turned on earlier.
a Parts
A Design Example: Digital Alarm Clock
AM/PM
Alarm_on/off 2
7
7
Hrs.
7 Mins.
Display Drivers 2
7
7
7
BCD-7 Segment Converter H 5
M 7
Multiplexer Set Alarm
Alarm Time Block
13
13
Clock Time Block
Set Time Hrs. Mins.
CLK
Comparator
=
Tone Generator & Ringer Control
Speaker
Alarm_on
A Design Example: Digital Alarm Clock
8.7
c August 1998 ptb,kr
Clock Time Block chrs cmins
5 7
set_time CLOCK TIME
hrs
BLOCK
cam_pm
mins
CLK
inc_h chrs cmins cam_pm
5 7
TIME COUNTER
inc_m
TIME
inc_s
STATE MACHINE
set_time hrs mins CLK
A Design Example: Digital Alarm Clock
8.8
c August 1998 ptb,kr
Time State Machine:
Based on the status of set time input it generates input signals for the time counter. If set time is active it generates pulses on inc h or inc m line each time hrs. or mins. switch is pushed. In the normal mode, it sets inc s high so that the time counter counts the pulse on CLK input which has a frequency of 1 Hz. set_time hrs mins
inc_h inc_m inc_s
101 010 SET_MINS 01
101 000
all other conditions 000 all other conditions 001
COUNT TIME 00
all other conditions 000
SET_HRS
110 10 0
A Design Example: Digital Alarm Clock
110 000
10
8.9
c August 1998 ptb,kr
.
set_time
Q0 hrs min inc_h Q1 inc_m
inc_s clk TIME-SM
Schematic diagram of Time State Machine A Design Example: Digital Alarm Clock
8.10
c August 1998 ptb,kr
Time Counter:
8.11
c August 1998 ptb,kr
Input to the counter has a frequency of 1 Hz. To generate minutes output this input has to be divided by 60. This can be done by using a mod-60 counter or by using a mod-10 and a mod-6 counter with a ripple carry between them. To generate hours output the minutes output has to be divided by 60. Hours counter is a mod-13 counter whose output can be used to generate the AM/PM signal. The mod-6 and mod-10 counters generate BCD output, whereas the mod-13 counter generates binary output which is converted to two BCD digits. AM/PM signal is turned on or o each time hours count reaches 12. During the set time mode the minutes and hours counters are detached from their normal ripple carry inputs and are incremented by pulses on the inc m and inc h inputs.
A Design Example: Digital Alarm Clock
.
am_pm
Hours 1
Minutes
4
3
. . 13
Seconds (not displayed)
4 .6 .
3
. 10 .
MUX
4 .6 .
. . 10
CLK
MUX
1 pulse/hour
1 pulse/minute
1 pulse/second
inc_h
inc_m
inc_s set_time
Block diagram of Time Counter
A Design Example: Digital Alarm Clock
8.12
c August 1998 ptb,kr
.
Q2
Q1
Q0
carry-out
clk
MOD-6
Schematic diagram of Mod-6 Counter A Design Example: Digital Alarm Clock
8.13
c August 1998 ptb,kr
.
carry-out
MOD-10
Q3
Q2
Q1
8.14
Q0
Schematic diagram of Mod-10 Counter A Design Example: Digital Alarm Clock
clk
c August 1998 ptb,kr
.
carry-out
MOD-13 (BCD)
Qt0
Q3
Q2
8.15
Q1
Q0
Schematic diagram of Mod-13 Counter A Design Example: Digital Alarm Clock
clk
c August 1998 ptb,kr
.
cam_pm
chrs
cmins csecs
mod-13
mod-6
mod-10
mod-6
mod-10
set_time inc_h inc_m inc_s TIME-CTR clk
Schematic diagram of Time Counter A Design Example: Digital Alarm Clock
8.16
c August 1998 ptb,kr
Alarm Time Block set_alarm ALARM TIME
hrs
5 7
BLOCK mins
ahrs amins aam_pm
CLK
set_alarm hrs mins
ALARM STATE MACHINE
inc_h inc_m
ALARM
5
COUNTER
7
ahrs amins aam_pm
CLK
A Design Example: Digital Alarm Clock
8.17
c August 1998 ptb,kr
Alarm State Machine:
This state machine is similar to the time state machine described earlier, except that it does not generate an inc s signal and that it is active only during the set alarm mode. set_alarm hrs mins inc_h inc_m
101 01 SET_MINS 01
101 00
all other conditions 00 all other conditions 00
IDLE 00
all other conditions 00
110 10
A Design Example: Digital Alarm Clock
SET_HRS 10
8.18
110 00
c August 1998 ptb,kr
.
set_alarm
Q0 hrs min inc_h Q1 inc_m
clk
ALARM_SM
Schematic diagram of Alarm State Machine A Design Example: Digital Alarm Clock
8.19
c August 1998 ptb,kr
Alarm Counter:
Alarm time counter circuit is a subset of the time counter circuit described earlier. It has a mod-60 minutes counter and a mod-13 hours counter. These counters receive their counting pulses from inc m and inc h inputs. am_pm
Hours 1
Minutes
4
3
. 13 .
4 .6 .
. 10 .
inc_h inc_m
A Design Example: Digital Alarm Clock
8.20
c August 1998 ptb,kr
.
aam_pm
ahrs
mod-13
amins
mod-6
mod-10
inc_h inc_m ALARM_CTR
Schematic diagram of Alarm Counter
A Design Example: Digital Alarm Clock
8.21
c August 1998 ptb,kr
AM/PM
alarm_time
Hours
8.22
Clock and Alarm Time Multiplexer
set_alarm
MUX
A Design Example: Digital Alarm Clock
clock_time
Minutes
c August 1998 ptb,kr
a g
b c
DISPLAY DRIVERS
a
b
c
d
8.23
e
f
g
c August 1998 ptb,kr
BCD-to-7-Segment Converter and Display Driver
f e d
A (8) B (4) C (2) D (1)
BCD-to-7-SEGMENT DECODER
A Design Example: Digital Alarm Clock
Alarm and Clock Time Comparator
alarm time
clock time
equal
COMPARATOR
A Design Example: Digital Alarm Clock
8.24
c August 1998 ptb,kr
Ringer State Machine
This machine determines when the alarm ringer (audible output for the speaker) turns on. Ringer turns on when alarm is turned on AND the clock time matches the alarm time. Once the ringer is on, it can only be turned o by turning o the alarm on/o switch. alarm_on equal ring 11 1 00,01,10 0
IDLE 0
WAKEUP 1
0
1
1
0
OSCILLATOR
Speaker Output
ring
A Design Example: Digital Alarm Clock
8.25
c August 1998 ptb,kr
.
alarm_on/off
RINGER-SM
equal
clk osc
8.26
Schematic diagram of Ringer State Machine A Design Example: Digital Alarm Clock
ring
speaker
c August 1998 ptb,kr
hrs mins
set_alarm
alarm-ctr
alarm_time
Digital Alarm Clock Circuit .
set alarm set time
alarm_on/off
clk
"alarm-blk"
alarm-sm
alarm_on/off osc_in
A Design Example: Digital Alarm Clock
equal
8.27
clock_time
ringer-sm
alarm_on/off
speaker
MUX
cam_pm
time-ctr
"time-blk"
time-sm
c August 1998 ptb,kr
Some Simulation Results
8.28
Simulation results of the Mod-6 counter A Design Example: Digital Alarm Clock
c August 1998 ptb,kr
8.29
Simulation results of the Mod-13 BCD counter A Design Example: Digital Alarm Clock
c August 1998 ptb,kr
.
8.30
Simulation results of the Alarm State Machine A Design Example: Digital Alarm Clock
c August 1998 ptb,kr
8.31
Simulation results of the Ringer State Machine A Design Example: Digital Alarm Clock
c August 1998 ptb,kr
c August 1998 ptb,kr
8. A Design Example: Digital Alarm Clock Poras T. Balsara and Kamlesh Rath
8.1
Department of Electrical Engineering The University of Texas at Dallas
A Design Example: Digital Alarm Clock
Simulation results
Design details
Overall architecture
Speci cations and usage
General design Methodology
Digital Alarm Clock Design
A Design Example: Digital Alarm Clock
8.2
c August 1998 ptb,kr
General Design Methodology
8.3
c August 1998 ptb,kr
Top-down vs Bottom-up design methodology. Proceed in a top-down fashion starting with a high level speci cation of the system to be designed. Develop a top level architecture block diagram. Determine speci cations of building blocks and interface among di erent blocks. Design building blocks by going down the hierarchy till you reach the most primitive blocks, i.e., combinational logic gates and ip- ops in this design environment. Design and thoroughly simulate the most basic blocks using the primitive components. Build next (higher) level blocks using the above basic blocks, simulating thoroughly at each level { Bottom-up design process.
A Design Example: Digital Alarm Clock
Speci cations and Usage
Digital clock with alarm. Displays hours and minutes in 12 hour mode with AM/PM and Alarm ON LED indicators. Push button switches to set time of day and alarm time. Push button switches to set hours and minutes. Push button switch that toggles alarm on or o and a speaker to provide an audible tone when alarm goes o . Hours Set_Time
Minutes Alarm on/off
Set_Alarm Speaker AM/PM
Alarm on/off LED
A Design Example: Digital Alarm Clock
8.4
c August 1998 ptb,kr
8.5
c August 1998 ptb,kr
To set time of day: { Press Set Time push button switch and { Push Hours switch to modify Hours display or Minutes switch to modify Minutes display. { Release Set Time switch to continue normal operation. { Each push of Hours or Minutes switch will increment the corresponding display by one. { Hours and Minutes switches should not be operated at the same time. To set alarm time: { Press Set Alarm and switch and use Hours and Minutes switches as mentioned above to set alarm time. { Release Set Alarm switch. { In order to turn-on the alarm push the Alarm on/o switch once. Pushing it again will turn-o the alarm. { Once the alarm goes o it can be shut only by pushing the Alarm on/o switch.
A Design Example: Digital Alarm Clock
Overall Architecture
8.6
c August 1998 ptb,kr
of this design are from the Synopsys VSS Family Tutorials, ver 3.3
There are two distinct components in this designa : (a) clock time circuit, and (b) alarm time circuit. These blocks generate data for hours, minutes and AM/PM displays. There is no need to display alarm time all the time. It should be displayed only when alarm time is being set. At all other times clock time is displayed. This is achieved by multiplexing the data outputs from the clock time and alarm time circuits using Set Alarm as control input. Since the display devices are 7-Segment LED displays there is a need for either a binary-to-7-segment or a BCD-to-7-segment converter. A magnitude comparator is needed to compare the clock and alarm times and to generate a signal which can turn on an alarm ringer if the alarm was turned on earlier.
a Parts
A Design Example: Digital Alarm Clock
AM/PM
Alarm_on/off 2
7
7
Hrs.
7 Mins.
Display Drivers 2
7
7
7
BCD-7 Segment Converter H 5
M 7
Multiplexer Set Alarm
Alarm Time Block
13
13
Clock Time Block
Set Time Hrs. Mins.
CLK
Comparator
=
Tone Generator & Ringer Control
Speaker
Alarm_on
A Design Example: Digital Alarm Clock
8.7
c August 1998 ptb,kr
Clock Time Block chrs cmins
5 7
set_time CLOCK TIME
hrs
BLOCK
cam_pm
mins
CLK
inc_h chrs cmins cam_pm
5 7
TIME COUNTER
inc_m
TIME
inc_s
STATE MACHINE
set_time hrs mins CLK
A Design Example: Digital Alarm Clock
8.8
c August 1998 ptb,kr
Time State Machine:
Based on the status of set time input it generates input signals for the time counter. If set time is active it generates pulses on inc h or inc m line each time hrs. or mins. switch is pushed. In the normal mode, it sets inc s high so that the time counter counts the pulse on CLK input which has a frequency of 1 Hz. set_time hrs mins
inc_h inc_m inc_s
101 010 SET_MINS 01
101 000
all other conditions 000 all other conditions 001
COUNT TIME 00
all other conditions 000
SET_HRS
110 10 0
A Design Example: Digital Alarm Clock
110 000
10
8.9
c August 1998 ptb,kr
.
set_time
Q0 hrs min inc_h Q1 inc_m
inc_s clk TIME-SM
Schematic diagram of Time State Machine A Design Example: Digital Alarm Clock
8.10
c August 1998 ptb,kr
Time Counter:
8.11
c August 1998 ptb,kr
Input to the counter has a frequency of 1 Hz. To generate minutes output this input has to be divided by 60. This can be done by using a mod-60 counter or by using a mod-10 and a mod-6 counter with a ripple carry between them. To generate hours output the minutes output has to be divided by 60. Hours counter is a mod-13 counter whose output can be used to generate the AM/PM signal. The mod-6 and mod-10 counters generate BCD output, whereas the mod-13 counter generates binary output which is converted to two BCD digits. AM/PM signal is turned on or o each time hours count reaches 12. During the set time mode the minutes and hours counters are detached from their normal ripple carry inputs and are incremented by pulses on the inc m and inc h inputs.
A Design Example: Digital Alarm Clock
.
am_pm
Hours 1
Minutes
4
3
. . 13
Seconds (not displayed)
4 .6 .
3
. 10 .
MUX
4 .6 .
. . 10
CLK
MUX
1 pulse/hour
1 pulse/minute
1 pulse/second
inc_h
inc_m
inc_s set_time
Block diagram of Time Counter
A Design Example: Digital Alarm Clock
8.12
c August 1998 ptb,kr
.
Q2
Q1
Q0
carry-out
clk
MOD-6
Schematic diagram of Mod-6 Counter A Design Example: Digital Alarm Clock
8.13
c August 1998 ptb,kr
.
carry-out
MOD-10
Q3
Q2
Q1
8.14
Q0
Schematic diagram of Mod-10 Counter A Design Example: Digital Alarm Clock
clk
c August 1998 ptb,kr
.
carry-out
MOD-13 (BCD)
Qt0
Q3
Q2
8.15
Q1
Q0
Schematic diagram of Mod-13 Counter A Design Example: Digital Alarm Clock
clk
c August 1998 ptb,kr
.
cam_pm
chrs
cmins csecs
mod-13
mod-6
mod-10
mod-6
mod-10
set_time inc_h inc_m inc_s TIME-CTR clk
Schematic diagram of Time Counter A Design Example: Digital Alarm Clock
8.16
c August 1998 ptb,kr
Alarm Time Block set_alarm ALARM TIME
hrs
5 7
BLOCK mins
ahrs amins aam_pm
CLK
set_alarm hrs mins
ALARM STATE MACHINE
inc_h inc_m
ALARM
5
COUNTER
7
ahrs amins aam_pm
CLK
A Design Example: Digital Alarm Clock
8.17
c August 1998 ptb,kr
Alarm State Machine:
This state machine is similar to the time state machine described earlier, except that it does not generate an inc s signal and that it is active only during the set alarm mode. set_alarm hrs mins inc_h inc_m
101 01 SET_MINS 01
101 00
all other conditions 00 all other conditions 00
IDLE 00
all other conditions 00
110 10
A Design Example: Digital Alarm Clock
SET_HRS 10
8.18
110 00
c August 1998 ptb,kr
.
set_alarm
Q0 hrs min inc_h Q1 inc_m
clk
ALARM_SM
Schematic diagram of Alarm State Machine A Design Example: Digital Alarm Clock
8.19
c August 1998 ptb,kr
Alarm Counter:
Alarm time counter circuit is a subset of the time counter circuit described earlier. It has a mod-60 minutes counter and a mod-13 hours counter. These counters receive their counting pulses from inc m and inc h inputs. am_pm
Hours 1
Minutes
4
3
. 13 .
4 .6 .
. 10 .
inc_h inc_m
A Design Example: Digital Alarm Clock
8.20
c August 1998 ptb,kr
.
aam_pm
ahrs
mod-13
amins
mod-6
mod-10
inc_h inc_m ALARM_CTR
Schematic diagram of Alarm Counter
A Design Example: Digital Alarm Clock
8.21
c August 1998 ptb,kr
AM/PM
alarm_time
Hours
8.22
Clock and Alarm Time Multiplexer
set_alarm
MUX
A Design Example: Digital Alarm Clock
clock_time
Minutes
c August 1998 ptb,kr
a g
b c
DISPLAY DRIVERS
a
b
c
d
8.23
e
f
g
c August 1998 ptb,kr
BCD-to-7-Segment Converter and Display Driver
f e d
A (8) B (4) C (2) D (1)
BCD-to-7-SEGMENT DECODER
A Design Example: Digital Alarm Clock
Alarm and Clock Time Comparator
alarm time
clock time
equal
COMPARATOR
A Design Example: Digital Alarm Clock
8.24
c August 1998 ptb,kr
Ringer State Machine
This machine determines when the alarm ringer (audible output for the speaker) turns on. Ringer turns on when alarm is turned on AND the clock time matches the alarm time. Once the ringer is on, it can only be turned o by turning o the alarm on/o switch. alarm_on equal ring 11 1 00,01,10 0
IDLE 0
WAKEUP 1
0
1
1
0
OSCILLATOR
Speaker Output
ring
A Design Example: Digital Alarm Clock
8.25
c August 1998 ptb,kr
.
alarm_on/off
RINGER-SM
equal
clk osc
8.26
Schematic diagram of Ringer State Machine A Design Example: Digital Alarm Clock
ring
speaker
c August 1998 ptb,kr
hrs mins
set_alarm
alarm-ctr
alarm_time
Digital Alarm Clock Circuit .
set alarm set time
alarm_on/off
clk
"alarm-blk"
alarm-sm
alarm_on/off osc_in
A Design Example: Digital Alarm Clock
equal
8.27
clock_time
ringer-sm
alarm_on/off
speaker
MUX
cam_pm
time-ctr
"time-blk"
time-sm
c August 1998 ptb,kr
Some Simulation Results
8.28
Simulation results of the Mod-6 counter A Design Example: Digital Alarm Clock
c August 1998 ptb,kr
8.29
Simulation results of the Mod-13 BCD counter A Design Example: Digital Alarm Clock
c August 1998 ptb,kr
.
8.30
Simulation results of the Alarm State Machine A Design Example: Digital Alarm Clock
c August 1998 ptb,kr
8.31
Simulation results of the Ringer State Machine A Design Example: Digital Alarm Clock
c August 1998 ptb,kr
