A 12b ENOB, 2.5MHz-BW, 4.8mW VCO-Based 0-1 MASH ADC with ...
A 12b ENOB, 2.5MHz-BW, 4.8mW VCO-Based 0-1 MASH ADC with Direct Digital Background Nonlinearity Calibration Kareem Ragab and Nan Sun The University of Texas at Austin, Austin, TX 78712 Abstract — A direct digital background calibration technique to correct nonlinearity errors in VCO-based 0-1 MASH Σ∆ ADCs is presented. The proposed technique altogether corrects VCO gain error, nonlinearity, and capacitor mismatch of the residue generating DAC. It improves SNDR of the prototype ADC from 60dB to 73.4dB in 2.5MHz signal bandwidth. The ADC consumes 4.8mW from 1.8V supply in 180nm CMOS. The measured convergence time is only 64ms. Index Terms — Analog-to-digital converters, voltage controlled oscillator, background calibration.
I. INTRODUCTION Ring voltage-controlled oscillators (VCOs) provide inherent voltage-to-phase integration and quantization, which makes them ideally suited for noise-shaped ADCs. However, their nonlinearity severely limits performance. In previous works, this limitation was overcome using indirect replica-based background calibration [1]-[3], highorder ∆Σ loop filtering [4]-[5], and using the VCO as the second stage quantizer of a 0-1 MASH [6]-[7]. The mostly digital single stage architecture of [1]-[3] has the advantage of small area. However, it requires high oversampling ratio (OSR) and sampling rate (fs). Additionally, calibration accuracy is limited by replicamatching. Embedding the VCO in a high-order ∆Σ loop [4]-[5] reduces its linearity requirement and fs. However, their mostly analog nature negates scaling benefits gained by using the VCO. The 0-1 MASH architecture [6]-[7] relaxes the requirement on VCO linearity and fs in proportion to the first stage coarse quantizer resolution and it mostly consumes dynamic power. However, residue generating DAC element mismatch and VCO linear gain drift introduce additional errors, in the form of missing codes (gaps) in the ADC transfer function at the coarse quantizer decision boundaries. These errors were mitigated using DEM and background VCO linear gain estimation [6], foreground calibration [7], or suppressed by embedding the 0-1 MASH in a high-order ∆Σ loop [5]. This paper presents a background calibration technique that simultaneously corrects for DAC mismatches, interstage gain error, and VCO nonlinearity. In contrast to [6], the technique does not need analog dither and requires minimal change to the basic 0-1 MASH architecture. To our best knowledge, the proposed technique is the first to demonstrate direct background VCO nonlinearity calibration with a short convergence time. Measured
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convergence time of only 64ms is comparable to those of [1]-[3] where indirect calibration schemes were adopted. In those schemes, the absence of the input signal from the replica path enables short convergence time. However, this sacrifices calibration accuracy as the schemes of [1]-[3] rely on accurate replica-matching, which is hard to guarantee under process, voltage, and temperature (PVT) variations. A direct application of the technique in [1] to calibrate the VCOs in the signal path suffers from very long convergence time, in the order of tens of seconds [1]. Our proposed technique achieves fast convergence while directly calibrating the main VCOs resulting in accurate and robust operation. Fast convergence speed is achieved by reducing estimation error in the calibration loop. This is enabled by the use of narrow detection windows centered on the coarse quantizer decision boundaries. Only ADC outputs corresponding to input samples falling inside these detection windows, referred to as calibration samples, are used by the calibration unit to estimate the correction parameters. This reduces the variance of the calibration samples [8] which significantly shortens startup convergence time and increases calibration loop tracking bandwidth. II. ADC ARCHITECTURE Fig. 1 presents the proposed ADC architecture and timing diagram. The ADC operates in three phases, with 0.25Ts allocated for input tracking, 0.25Ts for coarse quantization and residue settling, and 0.5Ts for fine quantization; where Ts is the conversion cycle. This is realized using one 25% and two non-overlapped 50% dutyduty-cycle clock and . The input is first bottom-plate cycle clocks sampled on a differential thermometer capacitive DAC (CDAC) at the end of the input tracking phase. A 14-level main flash, along with an auxiliary flash, is then triggered to perform coarse quantization. Coarse quantization result (Dc) is taken as either the main or the auxiliary flash output based on a pseudo-random (PN)-sequence, and is subtracted from the input using CDAC to generate the residue which settles by the end of the second phase. Discrepancy between corresponding comparators’ outputs in main and auxiliary flash is detected using XOR gates. The 14 generated flags {f-7, f-6, …, f+6, f+7} are used by the calibration unit to capture ADC output samples used to estimate decision boundary gaps in the ADC transfer function as further explained in the next section.
Fig. 1 High-level diagram and timing of the proposed ADC.
The VCO is implemented using a pseudo-differential V/I converter and two 15-stage differential ring currentcontrolled oscillators (CCOs). Schematic of the VCObased quantizer is further illustrated in Fig. 2. In 1, the V/I converter inputs are connected to a common-mode voltage to reset both CCOs frequency to nominal frequency f0. In 2, the residue voltage on CDAC is applied to the V/I converter differential inputs and the CCOs’ frequencies change in proportion as shown in Fig. 1. Hence, the CCOs differential phase represents an integration of the residue voltage. Each CCO’s multi-phase output is a quantized representation of its phase. The CCO outputs are buffered rising edge, before and sampled using SA-FFs on applying the next residue, as shown in Fig. 2. Two 5-bit synchronous counters keep track of CCOs phase overflow. This eliminates the need for center frequency calibration [1] while enabling sample rate reconfiguration as in [6]. Each counter is sampled after retiming the sampling clock using one of the CCO multi-phase outputs. A digital first-order difference shapes quantization noise and generates outputs DVCOP and DVCON which are proportional to the corresponding CCO’s average frequency fCCOP and fCCON over one Ts, as illustrated in Fig. 1. Error in combined output DVCO,DIFF due to VCO 3rd-order nonlinearity is digitally corrected using a lookup table (LUT)-based correction block, similar to [1]-[2], generating calibrated output DVCO,cal . The calibration unit estimates the VCO 3rd-order nonlinearity coefficient γ in the background and periodically updates the LUT at the end of each calibration cycle.
Fig. 2 VCO quantizer schematic.
In addition to VCO tuning curve nonlinearity, CDAC mismatches and VCO linear gain error lead to gaps in the ADC transfer function at the coarse quantizer decision boundaries as illustrated in Fig. 3a which shows a zoom-in of the ADC transfer function Dout versus Vin. These gaps are estimated by the calibration unit in the background, as illustrated in next section, and are subtracted from Dc to obtain calibrated coarse quantizer output Dc,cal. An LUT is used to map Dc to Dc,cal. Finally, Dc,cal is combined with the calibrated differential VCO output DVCO,cal to obtain final output Dout. III. PROPOSED CALIBRATION TECHNIQUE Estimation of decision boundary gaps {k-7, k-6, …, k+6, k+7} is illustrated in Fig. 3a which shows a zoom-in for k±1 on the ADC transfer function. Vth±1 and Vth±1,aux are the first positive and negative thresholds around zero for the main and auxiliary flash respectively. Random mismatches and noise cause the main and auxiliary thresholds to differ creating small detection windows around their respective means with f±1 being the detection flags. f±1 are used by the calibration unit to capture Dout samples corresponding to inputs falling inside the detection windows, referred to as calibration samples. For each flag, Dc can only have one of two values corresponding to decision gap upper and lower edges. k±1 are estimated as the difference between the mean of their respective upper and lower edge calibration samples, as illustrated in Fig. 3. The PN-sequence ensures equal probability of upper and lower edge calibration samples for accurate gap estimation independent of input signal statistics. The only practical assumption is that the
Fig. 4 High-level diagram of the calibration unit.
Fig. 3 Elimination of decision boundary gaps and nonlinearity.
input probability density function is nonzero at the decision boundaries [8]. Placing flash comparator thresholds asymmetrically enables detection of VCO 3rd-order nonlinearity error using gap difference ki- – ki+ [8]. Negative thresholds are placed at – (n/16)Vref, where n {1,3,...,13} and Vref =1.8V is the ADC reference voltage. Positive thresholds are offset by – (1/32)Vref and placed at (n/16)Vref – (1/32)Vref. In presence of negative (compressive) VCO 3rd-order nonlinearity, positive ADC transfer function segments experience more nonlinearity (compression) which increases k+i relative to their corresponding k-i, as illustrated in Fig. 3a for k±1. Error due to VCO linear gain error and CDAC mismatches changes k±i by equal amount β i, which hence can be estimated from their mean, as illustrated in Fig. 3 for β 1. Adaptive LMS loops subtract estimated 3rd-order nonlinear error from DVCO,DIFF and estimated gaps AB from Dc driving error signals to zero. Fig. 3b shows ADC transfer function after convergence. A high-level diagram of the calibration unit is shown in Fig. 4. It consists of 7 identical slices for β 1~7 estimation and one slice for γ. Calibration samples are accumulated until a specified number is collected, as indicated by the Cal samples counter. For each flag f±i, calibration samples are sorted into two sets, based on Dc, corresponding to the
Fig. 5 Die photograph.
boundary gap upper and lower edges, and are used to estimate CD±i. LMS error signals are then estimated using the sum and differences of CD±i and used to update each of the LMS accumulators. Using new estimates E and F lowrate blocks calculate corresponding Dc,cal and DVCO,cal and update the LUTs. Cal samples counter and all accumulators are then reset for next calibration cycle. An FSM controls the operation. IV. MEASUREMENT RESULTS A prototype ADC implemented in 180nm CMOS occupies an active area of 0.22mm2 excluding the digital differentiator, output adder, and the calibration unit which were implemented off-chip as indicated in Fig. 1. Die photo is shown in Fig. 5. The ADC consumes 4.8mW from 1.8V supply while operating at 51.2MS/s, out of which only 24% is analog. Power is divided into 4mW for the onchip part and 0.8mW for the off-chip part (estimated using digital synthesis) that is consumed mainly by the LUTs, digital differentiator, and final output adder. The calibration unit consumes negligible power given its low rate operation. Fig. 6 shows output PSD for a 200kHz 3.6Vpp input signal. Background calibration improves SNDR from 60dB to 73.4dB in 2.5MHz signal band and SFDR from 66dB to 81dB. Measured SNDR and SNR
maintain linear increase with input amplitude up to fullscale swing as shown in Fig. 7. Fig. 8 shows the learning curve of ADC SNDR/SFDR. Total startup convergence time is 64ms. Table I summarizes the prototype performance and compares it to state-of-the-art VCO-based Σ∆ ADCs. In this prototype, a short calibration cycle of 4ms was selected to enable fast tracking response while maintaining a low activity factor for the low-rate LUT updaters making their power dissipation negligible. The ADC achieves a figureof-merit (FoM) that is in-line with the state-of-the-art. As the ADC is mostly digital, its FoM is expected to significantly improve if implemented in a more advanced technology node.
Fig. 6 Measured ADC output power spectral density.
VII. CONCLUSION A high-speed LMS-based direct background calibration technique for correcting CDAC mismatches, VCO linear gain drift and nonlinearity in VCO-based 0-1 MASH Σ∆ ADCs is presented. Processing ADC samples falling inside narrow detection windows at the coarse quantizer decision boundaries enables high-speed error estimation and correction. The prototype is the first to demonstrate fast direct background VCO nonlinearity calibration. REFERENCES [1] G. Taylor and I. Galton, “A Mostly-Digital Variable-Rate Continuous-Time Delta-Sigma Modulator ADC,” IEEE J. Solid-State Circuits, vol. 45, no. 12, pp. 2634-2646, Dec. 2010. [2] G. Taylor and I. Galton, “A Reconfigurable Mostly-Digital SD ADC with a Worst-Case FoM of 160dB,” IEEE VLSI Dig. Tech. Papers, pp. 166-167, Jun. 2012. [3] S. Rao, K. Reddy, B. Young, P. K. Hanumolu, “A 4.1mW, 12-bit ENOB, 5MHz BW, VCO-based ADC with on-chip deterministic digital background calibration in 90nm CMOS,” ,” IEEE VLSI Dig. Tech. Papers, pp. C68-C69, Jun. 2013. [4] M. Z. Straayer and M. H. Perrott, “A 12-Bit, 10-MHz Bandwidth, Continuous-Time Σ∆ ADC with a 5-Bit, 950MS/s VCO-Based Quantizer,” IEEE J. Solid-State Circuits, vol. 43, no. 4, pp. 805-814, Apr. 2008. [5] K. Reddy, S. Rao, R. Inti, A. Elshazly, M. Talegaonkar, P.K. Hanumolu, “A 16-mW 78-dB SNDR 10-MHz BW CT ∆Σ ADC Using Residue-Cancelling VCO-Based Quantizer,” IEEE J. Solid-State Circuits, vol. 43, no. 4, pp. 805-814, Apr. 2012. [6] A. Ghosh and S. Pamarti, “A 50MHz bandwidth, 10-b ENOB, 8.2mW VCO-based ADC enabled by filtereddithering based linearization,” IEEE CICC, Sep. 2013. [7] A. Sanyal, K. Ragab, L. Chen, T.R. Vishwanathan, S. Yan, and N. Sun, “A Hybrid SAR-VCO Delta-Sigma ADC with First-Order Noise Shaping,,” IEEE CICC, Sep. 2014. [8] N. Sun, “Exploiting Process Variation and Noise in Comparators to Calibrate Interstage Gain Nonlinearity in Pipelined ADCs,” IEEE Trans Circ. Syst. – I, vol. 59, no. 4, pp. 685-695, Apr. 2012.
Fig. 7 Measured SNR and SNDR vs. input amplitude.
Fig. 8 Measured SNDR/SFDR learning curve. Table I Performance summary and comparison. This work [2] [3] [4] [5] [6] Process [nm] 65 90 130 90 65 180 fs [MHz] 51.2 2400 640 950 600 1000 BW [MHz] 37.5 5 10 10 30 2.5 SNDR [dB] 70 73.9 72 78 64 73.4 Power [mW] 39 4.1 40 16 8.2 4.8* 2 Area [mm ] 0.08 0.16 0.41 0.36 0.62 0.22 Direct Calibration No No Yes N/A 28 105 Convergence Time [ms] 64 FOM [dB]** 160 165 156 166 160 161 *Includes 0.8mW estimated power for off-chip blocks **FoM = SNDR + 10log10(BW/Power)
I. INTRODUCTION Ring voltage-controlled oscillators (VCOs) provide inherent voltage-to-phase integration and quantization, which makes them ideally suited for noise-shaped ADCs. However, their nonlinearity severely limits performance. In previous works, this limitation was overcome using indirect replica-based background calibration [1]-[3], highorder ∆Σ loop filtering [4]-[5], and using the VCO as the second stage quantizer of a 0-1 MASH [6]-[7]. The mostly digital single stage architecture of [1]-[3] has the advantage of small area. However, it requires high oversampling ratio (OSR) and sampling rate (fs). Additionally, calibration accuracy is limited by replicamatching. Embedding the VCO in a high-order ∆Σ loop [4]-[5] reduces its linearity requirement and fs. However, their mostly analog nature negates scaling benefits gained by using the VCO. The 0-1 MASH architecture [6]-[7] relaxes the requirement on VCO linearity and fs in proportion to the first stage coarse quantizer resolution and it mostly consumes dynamic power. However, residue generating DAC element mismatch and VCO linear gain drift introduce additional errors, in the form of missing codes (gaps) in the ADC transfer function at the coarse quantizer decision boundaries. These errors were mitigated using DEM and background VCO linear gain estimation [6], foreground calibration [7], or suppressed by embedding the 0-1 MASH in a high-order ∆Σ loop [5]. This paper presents a background calibration technique that simultaneously corrects for DAC mismatches, interstage gain error, and VCO nonlinearity. In contrast to [6], the technique does not need analog dither and requires minimal change to the basic 0-1 MASH architecture. To our best knowledge, the proposed technique is the first to demonstrate direct background VCO nonlinearity calibration with a short convergence time. Measured
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convergence time of only 64ms is comparable to those of [1]-[3] where indirect calibration schemes were adopted. In those schemes, the absence of the input signal from the replica path enables short convergence time. However, this sacrifices calibration accuracy as the schemes of [1]-[3] rely on accurate replica-matching, which is hard to guarantee under process, voltage, and temperature (PVT) variations. A direct application of the technique in [1] to calibrate the VCOs in the signal path suffers from very long convergence time, in the order of tens of seconds [1]. Our proposed technique achieves fast convergence while directly calibrating the main VCOs resulting in accurate and robust operation. Fast convergence speed is achieved by reducing estimation error in the calibration loop. This is enabled by the use of narrow detection windows centered on the coarse quantizer decision boundaries. Only ADC outputs corresponding to input samples falling inside these detection windows, referred to as calibration samples, are used by the calibration unit to estimate the correction parameters. This reduces the variance of the calibration samples [8] which significantly shortens startup convergence time and increases calibration loop tracking bandwidth. II. ADC ARCHITECTURE Fig. 1 presents the proposed ADC architecture and timing diagram. The ADC operates in three phases, with 0.25Ts allocated for input tracking, 0.25Ts for coarse quantization and residue settling, and 0.5Ts for fine quantization; where Ts is the conversion cycle. This is realized using one 25% and two non-overlapped 50% dutyduty-cycle clock and . The input is first bottom-plate cycle clocks sampled on a differential thermometer capacitive DAC (CDAC) at the end of the input tracking phase. A 14-level main flash, along with an auxiliary flash, is then triggered to perform coarse quantization. Coarse quantization result (Dc) is taken as either the main or the auxiliary flash output based on a pseudo-random (PN)-sequence, and is subtracted from the input using CDAC to generate the residue which settles by the end of the second phase. Discrepancy between corresponding comparators’ outputs in main and auxiliary flash is detected using XOR gates. The 14 generated flags {f-7, f-6, …, f+6, f+7} are used by the calibration unit to capture ADC output samples used to estimate decision boundary gaps in the ADC transfer function as further explained in the next section.
Fig. 1 High-level diagram and timing of the proposed ADC.
The VCO is implemented using a pseudo-differential V/I converter and two 15-stage differential ring currentcontrolled oscillators (CCOs). Schematic of the VCObased quantizer is further illustrated in Fig. 2. In 1, the V/I converter inputs are connected to a common-mode voltage to reset both CCOs frequency to nominal frequency f0. In 2, the residue voltage on CDAC is applied to the V/I converter differential inputs and the CCOs’ frequencies change in proportion as shown in Fig. 1. Hence, the CCOs differential phase represents an integration of the residue voltage. Each CCO’s multi-phase output is a quantized representation of its phase. The CCO outputs are buffered rising edge, before and sampled using SA-FFs on applying the next residue, as shown in Fig. 2. Two 5-bit synchronous counters keep track of CCOs phase overflow. This eliminates the need for center frequency calibration [1] while enabling sample rate reconfiguration as in [6]. Each counter is sampled after retiming the sampling clock using one of the CCO multi-phase outputs. A digital first-order difference shapes quantization noise and generates outputs DVCOP and DVCON which are proportional to the corresponding CCO’s average frequency fCCOP and fCCON over one Ts, as illustrated in Fig. 1. Error in combined output DVCO,DIFF due to VCO 3rd-order nonlinearity is digitally corrected using a lookup table (LUT)-based correction block, similar to [1]-[2], generating calibrated output DVCO,cal . The calibration unit estimates the VCO 3rd-order nonlinearity coefficient γ in the background and periodically updates the LUT at the end of each calibration cycle.
Fig. 2 VCO quantizer schematic.
In addition to VCO tuning curve nonlinearity, CDAC mismatches and VCO linear gain error lead to gaps in the ADC transfer function at the coarse quantizer decision boundaries as illustrated in Fig. 3a which shows a zoom-in of the ADC transfer function Dout versus Vin. These gaps are estimated by the calibration unit in the background, as illustrated in next section, and are subtracted from Dc to obtain calibrated coarse quantizer output Dc,cal. An LUT is used to map Dc to Dc,cal. Finally, Dc,cal is combined with the calibrated differential VCO output DVCO,cal to obtain final output Dout. III. PROPOSED CALIBRATION TECHNIQUE Estimation of decision boundary gaps {k-7, k-6, …, k+6, k+7} is illustrated in Fig. 3a which shows a zoom-in for k±1 on the ADC transfer function. Vth±1 and Vth±1,aux are the first positive and negative thresholds around zero for the main and auxiliary flash respectively. Random mismatches and noise cause the main and auxiliary thresholds to differ creating small detection windows around their respective means with f±1 being the detection flags. f±1 are used by the calibration unit to capture Dout samples corresponding to inputs falling inside the detection windows, referred to as calibration samples. For each flag, Dc can only have one of two values corresponding to decision gap upper and lower edges. k±1 are estimated as the difference between the mean of their respective upper and lower edge calibration samples, as illustrated in Fig. 3. The PN-sequence ensures equal probability of upper and lower edge calibration samples for accurate gap estimation independent of input signal statistics. The only practical assumption is that the
Fig. 4 High-level diagram of the calibration unit.
Fig. 3 Elimination of decision boundary gaps and nonlinearity.
input probability density function is nonzero at the decision boundaries [8]. Placing flash comparator thresholds asymmetrically enables detection of VCO 3rd-order nonlinearity error using gap difference ki- – ki+ [8]. Negative thresholds are placed at – (n/16)Vref, where n {1,3,...,13} and Vref =1.8V is the ADC reference voltage. Positive thresholds are offset by – (1/32)Vref and placed at (n/16)Vref – (1/32)Vref. In presence of negative (compressive) VCO 3rd-order nonlinearity, positive ADC transfer function segments experience more nonlinearity (compression) which increases k+i relative to their corresponding k-i, as illustrated in Fig. 3a for k±1. Error due to VCO linear gain error and CDAC mismatches changes k±i by equal amount β i, which hence can be estimated from their mean, as illustrated in Fig. 3 for β 1. Adaptive LMS loops subtract estimated 3rd-order nonlinear error from DVCO,DIFF and estimated gaps AB from Dc driving error signals to zero. Fig. 3b shows ADC transfer function after convergence. A high-level diagram of the calibration unit is shown in Fig. 4. It consists of 7 identical slices for β 1~7 estimation and one slice for γ. Calibration samples are accumulated until a specified number is collected, as indicated by the Cal samples counter. For each flag f±i, calibration samples are sorted into two sets, based on Dc, corresponding to the
Fig. 5 Die photograph.
boundary gap upper and lower edges, and are used to estimate CD±i. LMS error signals are then estimated using the sum and differences of CD±i and used to update each of the LMS accumulators. Using new estimates E and F lowrate blocks calculate corresponding Dc,cal and DVCO,cal and update the LUTs. Cal samples counter and all accumulators are then reset for next calibration cycle. An FSM controls the operation. IV. MEASUREMENT RESULTS A prototype ADC implemented in 180nm CMOS occupies an active area of 0.22mm2 excluding the digital differentiator, output adder, and the calibration unit which were implemented off-chip as indicated in Fig. 1. Die photo is shown in Fig. 5. The ADC consumes 4.8mW from 1.8V supply while operating at 51.2MS/s, out of which only 24% is analog. Power is divided into 4mW for the onchip part and 0.8mW for the off-chip part (estimated using digital synthesis) that is consumed mainly by the LUTs, digital differentiator, and final output adder. The calibration unit consumes negligible power given its low rate operation. Fig. 6 shows output PSD for a 200kHz 3.6Vpp input signal. Background calibration improves SNDR from 60dB to 73.4dB in 2.5MHz signal band and SFDR from 66dB to 81dB. Measured SNDR and SNR
maintain linear increase with input amplitude up to fullscale swing as shown in Fig. 7. Fig. 8 shows the learning curve of ADC SNDR/SFDR. Total startup convergence time is 64ms. Table I summarizes the prototype performance and compares it to state-of-the-art VCO-based Σ∆ ADCs. In this prototype, a short calibration cycle of 4ms was selected to enable fast tracking response while maintaining a low activity factor for the low-rate LUT updaters making their power dissipation negligible. The ADC achieves a figureof-merit (FoM) that is in-line with the state-of-the-art. As the ADC is mostly digital, its FoM is expected to significantly improve if implemented in a more advanced technology node.
Fig. 6 Measured ADC output power spectral density.
VII. CONCLUSION A high-speed LMS-based direct background calibration technique for correcting CDAC mismatches, VCO linear gain drift and nonlinearity in VCO-based 0-1 MASH Σ∆ ADCs is presented. Processing ADC samples falling inside narrow detection windows at the coarse quantizer decision boundaries enables high-speed error estimation and correction. The prototype is the first to demonstrate fast direct background VCO nonlinearity calibration. REFERENCES [1] G. Taylor and I. Galton, “A Mostly-Digital Variable-Rate Continuous-Time Delta-Sigma Modulator ADC,” IEEE J. Solid-State Circuits, vol. 45, no. 12, pp. 2634-2646, Dec. 2010. [2] G. Taylor and I. Galton, “A Reconfigurable Mostly-Digital SD ADC with a Worst-Case FoM of 160dB,” IEEE VLSI Dig. Tech. Papers, pp. 166-167, Jun. 2012. [3] S. Rao, K. Reddy, B. Young, P. K. Hanumolu, “A 4.1mW, 12-bit ENOB, 5MHz BW, VCO-based ADC with on-chip deterministic digital background calibration in 90nm CMOS,” ,” IEEE VLSI Dig. Tech. Papers, pp. C68-C69, Jun. 2013. [4] M. Z. Straayer and M. H. Perrott, “A 12-Bit, 10-MHz Bandwidth, Continuous-Time Σ∆ ADC with a 5-Bit, 950MS/s VCO-Based Quantizer,” IEEE J. Solid-State Circuits, vol. 43, no. 4, pp. 805-814, Apr. 2008. [5] K. Reddy, S. Rao, R. Inti, A. Elshazly, M. Talegaonkar, P.K. Hanumolu, “A 16-mW 78-dB SNDR 10-MHz BW CT ∆Σ ADC Using Residue-Cancelling VCO-Based Quantizer,” IEEE J. Solid-State Circuits, vol. 43, no. 4, pp. 805-814, Apr. 2012. [6] A. Ghosh and S. Pamarti, “A 50MHz bandwidth, 10-b ENOB, 8.2mW VCO-based ADC enabled by filtereddithering based linearization,” IEEE CICC, Sep. 2013. [7] A. Sanyal, K. Ragab, L. Chen, T.R. Vishwanathan, S. Yan, and N. Sun, “A Hybrid SAR-VCO Delta-Sigma ADC with First-Order Noise Shaping,,” IEEE CICC, Sep. 2014. [8] N. Sun, “Exploiting Process Variation and Noise in Comparators to Calibrate Interstage Gain Nonlinearity in Pipelined ADCs,” IEEE Trans Circ. Syst. – I, vol. 59, no. 4, pp. 685-695, Apr. 2012.
Fig. 7 Measured SNR and SNDR vs. input amplitude.
Fig. 8 Measured SNDR/SFDR learning curve. Table I Performance summary and comparison. This work [2] [3] [4] [5] [6] Process [nm] 65 90 130 90 65 180 fs [MHz] 51.2 2400 640 950 600 1000 BW [MHz] 37.5 5 10 10 30 2.5 SNDR [dB] 70 73.9 72 78 64 73.4 Power [mW] 39 4.1 40 16 8.2 4.8* 2 Area [mm ] 0.08 0.16 0.41 0.36 0.62 0.22 Direct Calibration No No Yes N/A 28 105 Convergence Time [ms] 64 FOM [dB]** 160 165 156 166 160 161 *Includes 0.8mW estimated power for off-chip blocks **FoM = SNDR + 10log10(BW/Power)
