A 148fsrms Integrated Noise 4MHz Bandwidth All-Digital ... - koasas
A 148f srms Integrated Noise 4MHz Bandwidth All-Digital Second-Order ΔΣ Time-to-Digital Converter Using Gated Switched-Ring Oscillator Wonsik Yu, KwangSeok Kim, and SeongHwan Cho Department of EE, KAIST Daejon, Republic of Korea Email: [email protected], [email protected], [email protected]
SRO
DCF
978-1-4673-6146-0/13/$31.00 ©2013 IEEE
SRO
counter
II. P ROPOSED 1-1 MASH ΔΣ TDC USING GSRO A 1-1 MASH TDC from [8] is shown in Fig. 1(a). The first stage SRO-TDC that performs first-order noise shaping is followed by a quantization error generator (QEGen) that produces
TIN
QE1 QE Gen
I. I NTRODUCTION High resolution time-to-digital converters (TDCs) are employed in digital PLLs, time-domain ADCs, jitter measurement and time-of-flight detection [1]–[3]. For low-bandwidth applications, ΔΣ TDCs exploiting noise-shaping property have been proposed to achieve high-resolution, high linearity. In [4], a GRO-TDC has been introduced as a first-order ΔΣ TDC, achieving picosecond time-resolution with 90dB dynamic range. Unfortunately, over-sampling ratio (OSR) of a GRO-TDC is limited by the input pulse rate (fi ) since sampling frequency (fS ) must be the same as fi . Thus, the time-resolution is limited if the input pulse rate is low. To achieve high OSR for low input pulse rates, an SROTDC [5] was proposed, where fS can be higher than fi , resulting in a finer time-resolution. To further improve the time-resolution and signal bandwidth, a second-order MASH TDC using SROs has been proposed [8] since the OSR cannot be increased indefinitely. Unfortunately, a high-order ΔΣ TDC using SRO requires complex calibration to compensate for the error from frequency difference between the SROs. As a result, it consumes additional power and area as well as a long settling time [8]. In this paper, we propose a gated switched-ring oscillator (GSRO) which not only removes the need for complex calibration in high-order ΔΣ TDC but also allows for obtaining high OSR. Using the proposed GSRO, a novel second-order ΔΣ TDC is implemented, achieving low integrated noise and wide dynamic range with low complexity.
TIN counter
Abstract— This paper presents an all-digital second-order ΔΣ time-to-digital converter (TDC) by using switched-ring oscillator (SRO) and gated switched-ring oscillator (GSRO). Unlike conventional multi-stage noise-shaping (MASH) TDC using the SRO, the proposed TDC does not require complex calibration to compensate for the error from frequency difference between the SROs. The prototype TDC achieves 148f srms integrated noise and 80.4dB dynamic range in 4MHz signal bandwidth at 400MS/s while consuming 6.55mW in a 65nm CMOS process.
DOUT
QE1 1st SRO fL freq. 2nd SRO f L Freq.
CLK
(a)
fL fH fH fH
fL
Time
(b)
Fig. 1. Conventional implementation of the 1-1 MASH TDC using SRO. (a) Block diagram. (b) Timing diagram. fL represents the minimum frequency and fH represents the maximum frequency of the oscillator. GSRO CTRL CTRL
YGSRO
EN YGSRO
EN
GSRO freq.
(a)
Fig. 2.
fL
fH
0
0
fH
(b)
0 Time
(a) Block diagram and (b) Timing diagram of the GSRO.
a quantization error pulse. The first stage quantization error (QE1 ) of width TQE1 is fed to the second stage SRO-TDC. Thus, it can be expected that this architecture will achieve second-order noise shaping. Unfortunately, there is frequency difference between the first and second stage oscillators during TQE1 as shown Fig .1(b), since frequency change of the first stage SRO cannot be tracked by the second stage SRO. Hence, an undesired gain is multiplied to QE1 , which destroys the second-order noise shaping [8]. Although the frequency difference between the first and second stage SROs can result from layout mismatch and manufacturing imperfections, frequency tracking error dominates the degradation of noise shaping. In [8], this problem is solved by using an off-chip calibration based on an LMS filter. In this paper, we overcome this problem by proposing a GSRO whose operation principle is shown in Fig. 2. As can be seen, GSRO is basically an SRO with phase-holding gates added at supply and ground. Hence, GSRO acts as an SRO when the gates are closed and holds the phase like a GRO when the gates are open. Note that GSRO can also be con-
GSRO
Ti(=1/fi)
Start Stop
Pulse Gen
TIN
Y1 1
Multi-bit D1 Counter DCLK DCLK Gen
GSRO
CEN
DOUT
Y2 9
CEN
EN
Y
Y
CEN
EN
Y
Y
DCF
QE1 QE Gen
EN
CEN
Multi-bit D2 Counter
EN
CEN
EN
EN
CEN
QEIN
TS(=1/fS)
CLK Y
(a)
CTRL [n]
[n+1]
Y
Samplig Clock(CLK) Start
Fig. 4.
Q-noise pulse(QE1)
TQE1[n]
Sync. Pulse(QEIN)
TQEIN[n]
TQE1[n+1]
GSRO output Y2
2
GSRO freq.
Y
Stop
SRO output (Y1)
nd
Y
EN
Input pulse (TIN)
1st SRO freq.
Y Y
CEN
fL
fL fH fH
fL
fL
fL
0
fL fH
0
fL
0
0
(b)
Time
Fig. 3. (a) Block diagram and (b) Timing diagram of the proposed ΔΣ TDC. Y1 and Y2 represent the output of the GSRO in the first and second stage, respectively.
sidered as frequency controllable GRO. The schematic of the GSRO is shown in Fig. 4, which is basically a gated delay-line with frequency control via CTRL. Multi-path structure [4] is applied to reduce the gating skew error due to leakage current. The block diagram and timing diagram of the proposed TDC using GSRO are shown in Fig. 3. In the first stage, GSRO is configured as an SRO by closing the EN gates. In the second stage, QEGen shown in Fig. 5(a) generates quantization error pulse QE1 and a frequency sync pulse QEIN . An offset is added to QE1 to avoid narrow pulse width which leads to a deadzone problem. The offset is easily subtracted in the digital cancellation filter (DCF). Since QE1 controls the gates of the GSRO and QEIN controls the frequency of the GSRO, oscillation frequencies of the first stage SRO and second stage GSRO are the same during TQE1 , as shown in Fig. 3(b). Therefore, gain calibration is not needed and second-order noise shaping can be achieved by a simple DCF used in a typical MASH modulator as shown in Fig. 5(b). Although the first stage SRO-TDC looks similar to the circuit shown in [5], there is a couple of key differences that are noteworthy. First, the first stage counter counts only one of
Proposed 9-stage GSRO using multi-path structure.
the multi-phase outputs of the SRO instead of counting all the phases. As quantization error of the first stage is removed after the DCF, there is no need to minimize TQE1 by counting all the phases. As a result, complexity and power consumption of the first stage SRO-TDC is significantly reduced. Second, the frequency of the SRO is designed to be higher than fS so that there exists at least one rising edge during a sampling period. This is because a residue pulse must be generated every cycle to complete the second-order noise-shaping. This is in contrast to [5] where the frequency of the SRO can be smaller than fS and hence a residue pulse may not be produced every cycle. Therefore, we employ a multi-bit counter shown in Fig. 6(a) to generate a residue pulse every cycle instead of a one-bit counter. One drawback of the multi-bit counter is that metastability may cause large error. In order to reduce the effect of meta-stability, a delayed clock generator (DCLKGen) is proposed by sampling the counter output (CN Toutput ) with a delayed clock as shown in Fig. 6(b) and (c). Similar to MASH ADCs, some non-idealities of the proposed MASH TDC benefits from noise shaping. For example, 1/f noise, phase noise, and gating skew error of the second stage GSRO is reduced as they are first-order noise-shaped and filtered. In addition, the proposed structure is immune to mismatch between the delay-cells of the GSRO, since only the second stage uses multi-phase outputs and the effect of mismatch is second-order noise-shaped.
III. E XPERIMENTAL R ESULTS A prototype of the proposed ΔΣ TDC was fabricated in a 65nm CMOS and it occupies an active area of 250 x 210μm (0.053 mm2 ) as shown in Fig. 7. The proposed TDC operates at 400 MS/s with 200 MHz input pulse rate. To verify the performance of the proposed TDC, power supply of an offchip delay-line was modulated. The measured output spectrum of a 390 kHz, 19 ps peak-to-peak sinusoidal input with a time offset of approximately 1 ns is shown in Fig. 8, where it can
D
CLK
D
D
GSRO(Y1)
Q
RST
D
Q
RST
Pulse Gen
QE1
QEIN
TIN
(a) z-1
x9
D1
DOUT z-1
D2
(b) Fig. 5. (a) Schematic of quantization error generator (QEGen) (b) Block diagram of digital cancellation filter (DCF). Fig. 7. GSRO(Y1)
Counter CNT output
Register
DCLK
CLK GSRO(Y1)
D
D
D
Q
RST
Register Differentiator
D
Q
Chip micrograph.
DCLK
RST
D1
(a)
(b)
GSRO(Y1) CNT output metastable
CLK DCLK
stable Time
(c) Fig. 6. (a) Schematic of the multi-bit counter (b) Schematic of the delayed clock generator (c) Timing diagram of the delayed clock generator. Fig. 8. Measured output spectrum. 65,536pt FFT is performed with a Hanning window.
be seen that second-order noise-shaping is achieved with 1/f noise dominating at low frequencies. The measured integrated noise (Tint,rms ) from 10 kHz to 4 MHz is -74.6 dB, which translates to 148 f srms at 200 MHz input pulse rate. The measured integrated noise for different OSRs is shown in Fig. 9, where the proposed TDC achieves better performance than a conventional SRO-TDC under the same OSR. Note that the integrated noise of the proposed TDC is limited by thermal and 1/f noise at higher OSRs (>100). The power consumption of the proposed TDC depends on the input pulse width, TIN . The upper limit is 6.55 mW, which is when the input is always high. When the average input pulse width is 1 ns, the power consumption is 5.35 mW. The performance of the proposed TDC is summarized and compared with the recent state-ofthe-art ΔΣ TDCs in Table I and Fig. 10. The proposed TDC achieves the widest bandwidth while achieving good FoM. Note that FoM1 used for ΔΣ converters is a better indication of the performance than FoM2 defined for Nyquist converters.
IV. CONCLUSION In this paper, a novel all-digital second-order ΔΣ TDC has been proposed that achieves wide dynamic range, wide bandwidth and low integrated noise. Using the proposed GSRO, the order of noise-shaping has been increased by cascading GSRO-TDC without any calibration. Since time-resolution of the GSRO depends on the speed of logic gate, the proposed architecture is expected to gain higher performance with the continued scaling of the CMOS process. V. ACKNOWLEDGMENTS This research was supported by the Basic Science Research Program through the National Research Foundation of Korea (NRF) grant funded by the Korea government (MEST) (20120000701) and IDEC of KAIST. The authors would like to thank Dr. Hayun Chung for helpful discussions.
TABLE I P ERFORMANCE SUMMARY AND COMPARISON WITH OTHER STATE - OF - THE ART ΔΣ TDC S . VLSI ’09 [4]
CICC ’10 [9]
JSSC ’12 [6]
ISSCC ’12 [5]
90-nm
130-nm
90-nm
90-nm
65-nm
65-nm
SRO
Charge Pump**
FSO
GSRO
90 MS/s
16 MS/s
400 MS/s
Process
130-nm
Scheme
GRO
fs
50 MS/s
156.25 MS/s
50 MS/s
500 MS/s
Phase-domain ΔΣ Relaxation Osc.
VLSI ’12 [7]
VLSI ’12 [8]* This work
fi
50 MHz
156.25 MHz
50 MHz
80 MHz
90 MHz
16 MHz
200 MHz
Bandwidth
1 MHz
1 MHz
1 MHz
1 MHz
2.8 MHz
0.5 MHz
4 MHz
Tint,rms
80 fs
–
–
315 fs
–
–
148 fs
Resolution
1 ps
2.4 ps
5.6 ps
–
3 ps
35 ps
1.4 ps
Full scale range
12 ns
3.2 ns
20 ns
12.5 ns
5.55 ns
31.25 ns
4 ns
Power consumption
21 mW
2.1 mW
1.7 mW
2.1 mW
2.81 mW
0.28 mW
6.55 mW
Active die area
0.04 mm2
0.12 mm2
0.11 mm2
0.02 mm2
0.43 mm2
FoM1[dB]***
171
156
157
169
162
FoM2[fJ/step]****
228
399
293
92
159
305
96
Calibration
No
No
Background
No
No
Background
No
0.0007 mm2 0.05 mm2 154
168
* Does not include power and area consumed by off-chip calibration. ** Charge-pump with noise-shaping single slope quantizer. *** F oM 1 = DR+10log10 (Bandwidth/P ower) [dB], where DR = 20log10 (Trange /Tint,rms ). ****F oM 2 = P ower/2Bit /2/Bandwidth, where Bit=number of bit : Bit=(DR − 1.76)/6.02.
-40
175
FOM1 [dB]
Integrated Noise [dB]
[4]
170
-50 SRO-TDC -60
165 [7] 160
-70
[6] [9]
155
Proposed TDC
This work
[5]
[8]
-80 101
102 OSR
0
103
Fig. 10.
Fig. 9. Measured integrated noise for different OSRs. The integrated noise is varied by changing signal bandwidth.
R EFERENCES [1] K.-S.Kim et al., “A 7 bit, 3.75 ps Resolution Two-Step Time-to-Digital Converter in 65 nm CMOS Using Pulse-Train Time Amplifie,” IEEE J. Solid-State Circuits, vol. 48, no. 4, pp. 1009–1017, Apr. 2013. [2] D.-W. Jee et al., “A 2 GHz Fractional-N Digital PLL with 1b Noise Shaping ΔΣ TDC,” IEEE J. Solid-State Circuits, vol. 47, no. 4, pp. 875–883, Dec. 2010. [3] S. Naraghi et al., “A 9-bit, 14 μW and 0.06 mm2 Pulse Position Modulation ADC in 90 nm Digital CMOS,” IEEE J. Solid-State Circuits, vol. 45, no. 9, pp. 1870–1880, Sep. 2010. [4] M.Z. Straayer et al., “A Multi-Path Gated Ring Oscillator TDC With First-Order Noise Shaping,” IEEE J. Solid-State Circuits, vol. 44, no. 4, pp. 1089–1098, Apr. 2009. [5] A. Elshazly et al., “A 13b 315fsrms 2mW 500MS/s 1MHz Bandwidth
[6] [7] [8] [9]
1
2 3 Bandwidth [MHz]
4
5
FoM comparison with recent reported ΔΣ TDCs.
Highly Digital Time-to-Digital Converter Using Switched Ring Oscillators,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2012, pp. 464–466. Y. Cao et al., “1-1-1 MASH ΔΣ Time-to-Digital Converter With 6ps Resolution and Third-Order Noise-Shaping,” IEEE J. Solid-State Circuits, vol. 47, no. 9, pp. 2093–2106, Sep. 2012. M. Gande et al., “A 71dB Dynamic Range Third-Order ΔΣ TDC using Charge-Pump,” in IEEE Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2012, pp. 168–169. T. Konish et al., “A 61-dB SNDR 700 μm2 Second-Order All-Digital TDC with Low-Jitter Frequency Shift Oscillator and Dynamic Flipflops,” in IEEE Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2012, pp. 190–191. B. Young et al., “A 2.4ps resolution 2.1mW Second-Order Noise-Shaped Time-to-Digital Converter With 3.2ns Range in 1MHz Bandwidth,” in Proc. IEEE CICC, Sep. 2010, pp. 1–4.
SRO
DCF
978-1-4673-6146-0/13/$31.00 ©2013 IEEE
SRO
counter
II. P ROPOSED 1-1 MASH ΔΣ TDC USING GSRO A 1-1 MASH TDC from [8] is shown in Fig. 1(a). The first stage SRO-TDC that performs first-order noise shaping is followed by a quantization error generator (QEGen) that produces
TIN
QE1 QE Gen
I. I NTRODUCTION High resolution time-to-digital converters (TDCs) are employed in digital PLLs, time-domain ADCs, jitter measurement and time-of-flight detection [1]–[3]. For low-bandwidth applications, ΔΣ TDCs exploiting noise-shaping property have been proposed to achieve high-resolution, high linearity. In [4], a GRO-TDC has been introduced as a first-order ΔΣ TDC, achieving picosecond time-resolution with 90dB dynamic range. Unfortunately, over-sampling ratio (OSR) of a GRO-TDC is limited by the input pulse rate (fi ) since sampling frequency (fS ) must be the same as fi . Thus, the time-resolution is limited if the input pulse rate is low. To achieve high OSR for low input pulse rates, an SROTDC [5] was proposed, where fS can be higher than fi , resulting in a finer time-resolution. To further improve the time-resolution and signal bandwidth, a second-order MASH TDC using SROs has been proposed [8] since the OSR cannot be increased indefinitely. Unfortunately, a high-order ΔΣ TDC using SRO requires complex calibration to compensate for the error from frequency difference between the SROs. As a result, it consumes additional power and area as well as a long settling time [8]. In this paper, we propose a gated switched-ring oscillator (GSRO) which not only removes the need for complex calibration in high-order ΔΣ TDC but also allows for obtaining high OSR. Using the proposed GSRO, a novel second-order ΔΣ TDC is implemented, achieving low integrated noise and wide dynamic range with low complexity.
TIN counter
Abstract— This paper presents an all-digital second-order ΔΣ time-to-digital converter (TDC) by using switched-ring oscillator (SRO) and gated switched-ring oscillator (GSRO). Unlike conventional multi-stage noise-shaping (MASH) TDC using the SRO, the proposed TDC does not require complex calibration to compensate for the error from frequency difference between the SROs. The prototype TDC achieves 148f srms integrated noise and 80.4dB dynamic range in 4MHz signal bandwidth at 400MS/s while consuming 6.55mW in a 65nm CMOS process.
DOUT
QE1 1st SRO fL freq. 2nd SRO f L Freq.
CLK
(a)
fL fH fH fH
fL
Time
(b)
Fig. 1. Conventional implementation of the 1-1 MASH TDC using SRO. (a) Block diagram. (b) Timing diagram. fL represents the minimum frequency and fH represents the maximum frequency of the oscillator. GSRO CTRL CTRL
YGSRO
EN YGSRO
EN
GSRO freq.
(a)
Fig. 2.
fL
fH
0
0
fH
(b)
0 Time
(a) Block diagram and (b) Timing diagram of the GSRO.
a quantization error pulse. The first stage quantization error (QE1 ) of width TQE1 is fed to the second stage SRO-TDC. Thus, it can be expected that this architecture will achieve second-order noise shaping. Unfortunately, there is frequency difference between the first and second stage oscillators during TQE1 as shown Fig .1(b), since frequency change of the first stage SRO cannot be tracked by the second stage SRO. Hence, an undesired gain is multiplied to QE1 , which destroys the second-order noise shaping [8]. Although the frequency difference between the first and second stage SROs can result from layout mismatch and manufacturing imperfections, frequency tracking error dominates the degradation of noise shaping. In [8], this problem is solved by using an off-chip calibration based on an LMS filter. In this paper, we overcome this problem by proposing a GSRO whose operation principle is shown in Fig. 2. As can be seen, GSRO is basically an SRO with phase-holding gates added at supply and ground. Hence, GSRO acts as an SRO when the gates are closed and holds the phase like a GRO when the gates are open. Note that GSRO can also be con-
GSRO
Ti(=1/fi)
Start Stop
Pulse Gen
TIN
Y1 1
Multi-bit D1 Counter DCLK DCLK Gen
GSRO
CEN
DOUT
Y2 9
CEN
EN
Y
Y
CEN
EN
Y
Y
DCF
QE1 QE Gen
EN
CEN
Multi-bit D2 Counter
EN
CEN
EN
EN
CEN
QEIN
TS(=1/fS)
CLK Y
(a)
CTRL [n]
[n+1]
Y
Samplig Clock(CLK) Start
Fig. 4.
Q-noise pulse(QE1)
TQE1[n]
Sync. Pulse(QEIN)
TQEIN[n]
TQE1[n+1]
GSRO output Y2
2
GSRO freq.
Y
Stop
SRO output (Y1)
nd
Y
EN
Input pulse (TIN)
1st SRO freq.
Y Y
CEN
fL
fL fH fH
fL
fL
fL
0
fL fH
0
fL
0
0
(b)
Time
Fig. 3. (a) Block diagram and (b) Timing diagram of the proposed ΔΣ TDC. Y1 and Y2 represent the output of the GSRO in the first and second stage, respectively.
sidered as frequency controllable GRO. The schematic of the GSRO is shown in Fig. 4, which is basically a gated delay-line with frequency control via CTRL. Multi-path structure [4] is applied to reduce the gating skew error due to leakage current. The block diagram and timing diagram of the proposed TDC using GSRO are shown in Fig. 3. In the first stage, GSRO is configured as an SRO by closing the EN gates. In the second stage, QEGen shown in Fig. 5(a) generates quantization error pulse QE1 and a frequency sync pulse QEIN . An offset is added to QE1 to avoid narrow pulse width which leads to a deadzone problem. The offset is easily subtracted in the digital cancellation filter (DCF). Since QE1 controls the gates of the GSRO and QEIN controls the frequency of the GSRO, oscillation frequencies of the first stage SRO and second stage GSRO are the same during TQE1 , as shown in Fig. 3(b). Therefore, gain calibration is not needed and second-order noise shaping can be achieved by a simple DCF used in a typical MASH modulator as shown in Fig. 5(b). Although the first stage SRO-TDC looks similar to the circuit shown in [5], there is a couple of key differences that are noteworthy. First, the first stage counter counts only one of
Proposed 9-stage GSRO using multi-path structure.
the multi-phase outputs of the SRO instead of counting all the phases. As quantization error of the first stage is removed after the DCF, there is no need to minimize TQE1 by counting all the phases. As a result, complexity and power consumption of the first stage SRO-TDC is significantly reduced. Second, the frequency of the SRO is designed to be higher than fS so that there exists at least one rising edge during a sampling period. This is because a residue pulse must be generated every cycle to complete the second-order noise-shaping. This is in contrast to [5] where the frequency of the SRO can be smaller than fS and hence a residue pulse may not be produced every cycle. Therefore, we employ a multi-bit counter shown in Fig. 6(a) to generate a residue pulse every cycle instead of a one-bit counter. One drawback of the multi-bit counter is that metastability may cause large error. In order to reduce the effect of meta-stability, a delayed clock generator (DCLKGen) is proposed by sampling the counter output (CN Toutput ) with a delayed clock as shown in Fig. 6(b) and (c). Similar to MASH ADCs, some non-idealities of the proposed MASH TDC benefits from noise shaping. For example, 1/f noise, phase noise, and gating skew error of the second stage GSRO is reduced as they are first-order noise-shaped and filtered. In addition, the proposed structure is immune to mismatch between the delay-cells of the GSRO, since only the second stage uses multi-phase outputs and the effect of mismatch is second-order noise-shaped.
III. E XPERIMENTAL R ESULTS A prototype of the proposed ΔΣ TDC was fabricated in a 65nm CMOS and it occupies an active area of 250 x 210μm (0.053 mm2 ) as shown in Fig. 7. The proposed TDC operates at 400 MS/s with 200 MHz input pulse rate. To verify the performance of the proposed TDC, power supply of an offchip delay-line was modulated. The measured output spectrum of a 390 kHz, 19 ps peak-to-peak sinusoidal input with a time offset of approximately 1 ns is shown in Fig. 8, where it can
D
CLK
D
D
GSRO(Y1)
Q
RST
D
Q
RST
Pulse Gen
QE1
QEIN
TIN
(a) z-1
x9
D1
DOUT z-1
D2
(b) Fig. 5. (a) Schematic of quantization error generator (QEGen) (b) Block diagram of digital cancellation filter (DCF). Fig. 7. GSRO(Y1)
Counter CNT output
Register
DCLK
CLK GSRO(Y1)
D
D
D
Q
RST
Register Differentiator
D
Q
Chip micrograph.
DCLK
RST
D1
(a)
(b)
GSRO(Y1) CNT output metastable
CLK DCLK
stable Time
(c) Fig. 6. (a) Schematic of the multi-bit counter (b) Schematic of the delayed clock generator (c) Timing diagram of the delayed clock generator. Fig. 8. Measured output spectrum. 65,536pt FFT is performed with a Hanning window.
be seen that second-order noise-shaping is achieved with 1/f noise dominating at low frequencies. The measured integrated noise (Tint,rms ) from 10 kHz to 4 MHz is -74.6 dB, which translates to 148 f srms at 200 MHz input pulse rate. The measured integrated noise for different OSRs is shown in Fig. 9, where the proposed TDC achieves better performance than a conventional SRO-TDC under the same OSR. Note that the integrated noise of the proposed TDC is limited by thermal and 1/f noise at higher OSRs (>100). The power consumption of the proposed TDC depends on the input pulse width, TIN . The upper limit is 6.55 mW, which is when the input is always high. When the average input pulse width is 1 ns, the power consumption is 5.35 mW. The performance of the proposed TDC is summarized and compared with the recent state-ofthe-art ΔΣ TDCs in Table I and Fig. 10. The proposed TDC achieves the widest bandwidth while achieving good FoM. Note that FoM1 used for ΔΣ converters is a better indication of the performance than FoM2 defined for Nyquist converters.
IV. CONCLUSION In this paper, a novel all-digital second-order ΔΣ TDC has been proposed that achieves wide dynamic range, wide bandwidth and low integrated noise. Using the proposed GSRO, the order of noise-shaping has been increased by cascading GSRO-TDC without any calibration. Since time-resolution of the GSRO depends on the speed of logic gate, the proposed architecture is expected to gain higher performance with the continued scaling of the CMOS process. V. ACKNOWLEDGMENTS This research was supported by the Basic Science Research Program through the National Research Foundation of Korea (NRF) grant funded by the Korea government (MEST) (20120000701) and IDEC of KAIST. The authors would like to thank Dr. Hayun Chung for helpful discussions.
TABLE I P ERFORMANCE SUMMARY AND COMPARISON WITH OTHER STATE - OF - THE ART ΔΣ TDC S . VLSI ’09 [4]
CICC ’10 [9]
JSSC ’12 [6]
ISSCC ’12 [5]
90-nm
130-nm
90-nm
90-nm
65-nm
65-nm
SRO
Charge Pump**
FSO
GSRO
90 MS/s
16 MS/s
400 MS/s
Process
130-nm
Scheme
GRO
fs
50 MS/s
156.25 MS/s
50 MS/s
500 MS/s
Phase-domain ΔΣ Relaxation Osc.
VLSI ’12 [7]
VLSI ’12 [8]* This work
fi
50 MHz
156.25 MHz
50 MHz
80 MHz
90 MHz
16 MHz
200 MHz
Bandwidth
1 MHz
1 MHz
1 MHz
1 MHz
2.8 MHz
0.5 MHz
4 MHz
Tint,rms
80 fs
–
–
315 fs
–
–
148 fs
Resolution
1 ps
2.4 ps
5.6 ps
–
3 ps
35 ps
1.4 ps
Full scale range
12 ns
3.2 ns
20 ns
12.5 ns
5.55 ns
31.25 ns
4 ns
Power consumption
21 mW
2.1 mW
1.7 mW
2.1 mW
2.81 mW
0.28 mW
6.55 mW
Active die area
0.04 mm2
0.12 mm2
0.11 mm2
0.02 mm2
0.43 mm2
FoM1[dB]***
171
156
157
169
162
FoM2[fJ/step]****
228
399
293
92
159
305
96
Calibration
No
No
Background
No
No
Background
No
0.0007 mm2 0.05 mm2 154
168
* Does not include power and area consumed by off-chip calibration. ** Charge-pump with noise-shaping single slope quantizer. *** F oM 1 = DR+10log10 (Bandwidth/P ower) [dB], where DR = 20log10 (Trange /Tint,rms ). ****F oM 2 = P ower/2Bit /2/Bandwidth, where Bit=number of bit : Bit=(DR − 1.76)/6.02.
-40
175
FOM1 [dB]
Integrated Noise [dB]
[4]
170
-50 SRO-TDC -60
165 [7] 160
-70
[6] [9]
155
Proposed TDC
This work
[5]
[8]
-80 101
102 OSR
0
103
Fig. 10.
Fig. 9. Measured integrated noise for different OSRs. The integrated noise is varied by changing signal bandwidth.
R EFERENCES [1] K.-S.Kim et al., “A 7 bit, 3.75 ps Resolution Two-Step Time-to-Digital Converter in 65 nm CMOS Using Pulse-Train Time Amplifie,” IEEE J. Solid-State Circuits, vol. 48, no. 4, pp. 1009–1017, Apr. 2013. [2] D.-W. Jee et al., “A 2 GHz Fractional-N Digital PLL with 1b Noise Shaping ΔΣ TDC,” IEEE J. Solid-State Circuits, vol. 47, no. 4, pp. 875–883, Dec. 2010. [3] S. Naraghi et al., “A 9-bit, 14 μW and 0.06 mm2 Pulse Position Modulation ADC in 90 nm Digital CMOS,” IEEE J. Solid-State Circuits, vol. 45, no. 9, pp. 1870–1880, Sep. 2010. [4] M.Z. Straayer et al., “A Multi-Path Gated Ring Oscillator TDC With First-Order Noise Shaping,” IEEE J. Solid-State Circuits, vol. 44, no. 4, pp. 1089–1098, Apr. 2009. [5] A. Elshazly et al., “A 13b 315fsrms 2mW 500MS/s 1MHz Bandwidth
[6] [7] [8] [9]
1
2 3 Bandwidth [MHz]
4
5
FoM comparison with recent reported ΔΣ TDCs.
Highly Digital Time-to-Digital Converter Using Switched Ring Oscillators,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2012, pp. 464–466. Y. Cao et al., “1-1-1 MASH ΔΣ Time-to-Digital Converter With 6ps Resolution and Third-Order Noise-Shaping,” IEEE J. Solid-State Circuits, vol. 47, no. 9, pp. 2093–2106, Sep. 2012. M. Gande et al., “A 71dB Dynamic Range Third-Order ΔΣ TDC using Charge-Pump,” in IEEE Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2012, pp. 168–169. T. Konish et al., “A 61-dB SNDR 700 μm2 Second-Order All-Digital TDC with Low-Jitter Frequency Shift Oscillator and Dynamic Flipflops,” in IEEE Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2012, pp. 190–191. B. Young et al., “A 2.4ps resolution 2.1mW Second-Order Noise-Shaped Time-to-Digital Converter With 3.2ns Range in 1MHz Bandwidth,” in Proc. IEEE CICC, Sep. 2010, pp. 1–4.
