A 2-6GHz Broadband CMOS Low-Noise Amplifier ... - Semantic Scholar
A 2-6GHz Broadband CMOS Low-Noise Amplifier with Current Reuse Topology Utilizing a Noise-Shaping Technique Wei-Hsiang Hung, Kuan-Ting Lin, Jian-Yu Hsieh, and Shey-Shi Lu Graduate Institute of Electronics Engineering National Taiwan University Taipei, Taiwan r96943052,d96943005,d99943020,[email protected] Abstract— A 2-6GHz broadband low-noise amplifier (LNA) with current reuse and noise-shaping technique is proposed for wideband matching, high power gain and flat noise figure (NF) response. The proposed UWB LNA is implemented in TSMC 0.18um CMOS technology. Measured results show that power gain is greater than 15dB and input return loss is larger than 10dB from 2 to 6GHz. The input third-order intercept point (IIP3) is -4dBm. Besides, a good noise figure of 3-3.7dB is obtained over the band of interest with a power dissipation of 15mW under a 1.8V power supply.
I. INTRODUCTION
topology will serious degrade the performance while implemented into the systems level. In this paper, a resistive feedback wideband matching technique is not only adopted, but the current reuse topology is also implemented in this low noise amplifier in order to achieve high gain performance. Besides, noise performance is also carefully considered. With these techniques, a broadband CMOS LNA is implemented by a standard 0.18um CMOS technology. It achieves wideband frequency response, high power gain and superior noise performance under a small area and reasonable power consumption.
The demand of high speed and high data rate wireless communication is increasing. The emerging Cognitive Radio system envisages ubiquitous wireless connectivity that supports multiple radio standards across multiple frequency bands and features reconfigurable for different services. One of the most challenging key in this broadband communication system is bringing out a front-end building block that fulfilling a broadband matching, high power gain along with low noise figure over a wide frequency range. The design of the low noise amplifier seems to be one of the crucial parts in front-end system. The amplifier should meets several severe requirements, such as broadband input matching (S11 < -10dB), sufficient gain (S21 > 10dB) to suppress the noise from the following blocks, low noise figure to enhance the sensitivity of the receiver. Furthermore, for mobile devices, low power consumption is also needed in order to extend the battery life. Many wideband CMOS low noise amplifiers have been presented recently. However, there are some limitations among them. For instance [1] and [2] used a band-pass or a high-pass filter as an input matching network that achieves a broadband matching and gain performance. However, a large number of passive elements result in large chip area and noise figure (NF) degradation for on chip implementation. Common gate topology might seem an efficient way to meet those requirements [3]. Unfortunately, insufficient gain and high noise figure in common gate
978-1-4244-9472-9/11/$26.00 ©2011 IEEE
1291
Fig. 1. Proposed LNA schematic
II. CIRCUIT TOPOLOGY AND ANALYSIS The topology of the proposed broadband CMOS LowNoise Amplifier is shown in Fig.1. The resistive feedback technique is used for the matching network and results in noise shaping. Followed by a cascade stage, in order to achieve high gain performance, a current reused function is performed by additional inductor and capacitor. In addition, a 0.2nH inductor is connected between the circuit output and pad for further extending the bandwidth [2]. A. Design of wideband matching The conventional cascade LNA with inductive source degeneration is the most popular topology for narrow band design due to its outstanding performance. However, this topology is only suitable for limited bandwidth. The input series resonance circuit has relatively high quality factor [4]. Hence, a broadband amplifier with resistive feedback has been proposed for reducing the quality factor [5]. Followed the sprite of reducing the quality factor, we used a local resistive feedback assist with gate and source inductors to form input matching network in Fig 1. In Fig. 2, we ignored the effect of Cgd and Ls, so the input impedance of the LNA can be derived as follows:
Rf
Zin sLg ( R f //
R fb RL
(1)
1 g m RL
R RL 1 1 ) sLg ( fb // ) C gs 1 g m RL C gs
B. Current Reuse Techniques The current reuse topology is considered as two stages of amplifier, which reduces current consumption through the reuse of the bias current. In Fig. 4, the first stage is a resistive feedback common source amplifier, and the second stage is a cascode amplifier. Note that additional commongate stage of the cascode configuration is implemented between two stages, and it can eliminate the miller effect and improve isolation from output return signal. In Fig. 1, after the signal is amplified by resistive feedback CS amplifier, the series Ld provides a high impedance path to block the signal. Another low impedance path is added from node X to the gate of M3, therefore the signal can once again be amplified by the second stage of cascade amplifier. The transfer function can be derived as follows:
H (s)
( R f //(1 / C gs1 )) Vout 1 ( gm1 ) Vs Rs sL g ( R f //(1 / sC gs1 )) R fb gm2
(3)
(1 / sC d ) ( sL L // RL ) ( sLd //(1 / sC gs 2 )) (1 / sC d )
In (3), the transfer function is determined by two low Q parallel resonant tanks. The first resonant tank has already been determined by input RLC matching network, so the second resonant tank can be chosen to resonance at the maximum frequency around 7GHz. Therefore, we can obtain high power gain through this current reuse topology for broadband system.
(2)
In this topology, the input gate inductor Lg can not only achieve matching but also extend the matching bandwidth. As we known, the matching bandwidth will shrink while Rf is larger, but the better noise figure we can get. Fig.3 shows that a resistive shunt-feedback topology with Lg can break the trade-off between matching bandwidth and noise figure. Therefore, we can meet the matching requirement over the band of interest from 2 to 6GHz. Fig. 3. Matching bandwidth versus Rf
Fig. 2. Small signal model for input matching circuit
1292
Rf
Rs Vs
Rfb I2
Iout
Current buffer
Lg Cgs1
Ld
gm1Vgs
LL
Cgs2
RL
Vout
gm2Vgs2
Fig. 4. Small signal model for proposed LNA
C. Noise Flatten technique Compared with [1], which used a band-pass filter as input stages, the proposed LNA adopted with one spiral inductor which simplifies the circuit complexity and reduces the signal loss due to the lossy components. Furthermore, the shunt-resistive feedback topology and current reuse technique both benefit to low noise figure and noise shaping design. In [4][6], the shape of Noise figure frequency response is dominated by the quality factor of the input matching network of the first-stage amplifier. In other words, the additional noise generated from cascade and passive components will not be a major noisy source, nevertheless, it will be suppress by the first stage of amplifier. After carefully calculation, the noise factor is (ignore gate noise)
NF 1
RPAR 2 2 (s 2 s Onf Onf ) / OnF RS G M1 R S Q IN
Fig. 5. Die photograph of the Broadband LNA.
2
(4)
where RPAR is the parasitic resistance, RS is the source resistance, γ is the coefficient of drain noise, GM1 is the transconductance of M1, QIN is the input quality factor, and Onf 1/ (Lg Ls)(Cgs Cgd) . In order to achieve a flat noise frequency response, the input quality factor should be chosen carefully. The input quality factor should be chosen as close to the maximally flat condition (Qin=0.707) as possible. In this work, resistor in feedback loop, Lg, Ls, and Cgs of M1 composed of a RL-C resonance circuit. While Lg=1.3nH, Ls=0.3nH, Rfb=340ohm and gm=100mS, the perfect compromise between noise flatness and input matching will be made simultaneously. III. MEASUREMENT RESULTS The proposed broadband LNA was implemented in a TSMC 1P6M 0.18 um CMOS technology. The die photograph is shown in Fig. 5. The die area including testing pads is about 1.00 x 0.98 mm2. The circuit was tested on wafer for RF characterization. The LNA draws 8.3 mA and the supply voltage is 1.8 V.
Fig. 6. Simulated and measured results for S11 and S21
Fig. 6 shows the simulated and measured results of the input return loss and power gain of the broadband LNA. The power gain is over 13 dB with a 3-dB frequency band from 1.8 to 7GHz while the input return losses are below 10 dB from 2 to 6GHz. In Fig. 7, the result shows not only a good low noise performance of 3.0-3.7dB from 2 to 6GHz, but also a superior flatness of the noise frequency response.
1293
TABLE I S UMMARY OF THE IMPLEMENTED CMOS WIDEBAND LNA [1],JSSC [2],MWCL [3],CICC [5],JSSC [7],MWCL [8],CAS-II [9],MWCL This Work
Freq.[GHz] 2.3-9.2 3-10.6 1.2-11.9 2-4.6 2-4.6 0.4-10 2-11.5 1.5-7
S11
I. INTRODUCTION
topology will serious degrade the performance while implemented into the systems level. In this paper, a resistive feedback wideband matching technique is not only adopted, but the current reuse topology is also implemented in this low noise amplifier in order to achieve high gain performance. Besides, noise performance is also carefully considered. With these techniques, a broadband CMOS LNA is implemented by a standard 0.18um CMOS technology. It achieves wideband frequency response, high power gain and superior noise performance under a small area and reasonable power consumption.
The demand of high speed and high data rate wireless communication is increasing. The emerging Cognitive Radio system envisages ubiquitous wireless connectivity that supports multiple radio standards across multiple frequency bands and features reconfigurable for different services. One of the most challenging key in this broadband communication system is bringing out a front-end building block that fulfilling a broadband matching, high power gain along with low noise figure over a wide frequency range. The design of the low noise amplifier seems to be one of the crucial parts in front-end system. The amplifier should meets several severe requirements, such as broadband input matching (S11 < -10dB), sufficient gain (S21 > 10dB) to suppress the noise from the following blocks, low noise figure to enhance the sensitivity of the receiver. Furthermore, for mobile devices, low power consumption is also needed in order to extend the battery life. Many wideband CMOS low noise amplifiers have been presented recently. However, there are some limitations among them. For instance [1] and [2] used a band-pass or a high-pass filter as an input matching network that achieves a broadband matching and gain performance. However, a large number of passive elements result in large chip area and noise figure (NF) degradation for on chip implementation. Common gate topology might seem an efficient way to meet those requirements [3]. Unfortunately, insufficient gain and high noise figure in common gate
978-1-4244-9472-9/11/$26.00 ©2011 IEEE
1291
Fig. 1. Proposed LNA schematic
II. CIRCUIT TOPOLOGY AND ANALYSIS The topology of the proposed broadband CMOS LowNoise Amplifier is shown in Fig.1. The resistive feedback technique is used for the matching network and results in noise shaping. Followed by a cascade stage, in order to achieve high gain performance, a current reused function is performed by additional inductor and capacitor. In addition, a 0.2nH inductor is connected between the circuit output and pad for further extending the bandwidth [2]. A. Design of wideband matching The conventional cascade LNA with inductive source degeneration is the most popular topology for narrow band design due to its outstanding performance. However, this topology is only suitable for limited bandwidth. The input series resonance circuit has relatively high quality factor [4]. Hence, a broadband amplifier with resistive feedback has been proposed for reducing the quality factor [5]. Followed the sprite of reducing the quality factor, we used a local resistive feedback assist with gate and source inductors to form input matching network in Fig 1. In Fig. 2, we ignored the effect of Cgd and Ls, so the input impedance of the LNA can be derived as follows:
Rf
Zin sLg ( R f //
R fb RL
(1)
1 g m RL
R RL 1 1 ) sLg ( fb // ) C gs 1 g m RL C gs
B. Current Reuse Techniques The current reuse topology is considered as two stages of amplifier, which reduces current consumption through the reuse of the bias current. In Fig. 4, the first stage is a resistive feedback common source amplifier, and the second stage is a cascode amplifier. Note that additional commongate stage of the cascode configuration is implemented between two stages, and it can eliminate the miller effect and improve isolation from output return signal. In Fig. 1, after the signal is amplified by resistive feedback CS amplifier, the series Ld provides a high impedance path to block the signal. Another low impedance path is added from node X to the gate of M3, therefore the signal can once again be amplified by the second stage of cascade amplifier. The transfer function can be derived as follows:
H (s)
( R f //(1 / C gs1 )) Vout 1 ( gm1 ) Vs Rs sL g ( R f //(1 / sC gs1 )) R fb gm2
(3)
(1 / sC d ) ( sL L // RL ) ( sLd //(1 / sC gs 2 )) (1 / sC d )
In (3), the transfer function is determined by two low Q parallel resonant tanks. The first resonant tank has already been determined by input RLC matching network, so the second resonant tank can be chosen to resonance at the maximum frequency around 7GHz. Therefore, we can obtain high power gain through this current reuse topology for broadband system.
(2)
In this topology, the input gate inductor Lg can not only achieve matching but also extend the matching bandwidth. As we known, the matching bandwidth will shrink while Rf is larger, but the better noise figure we can get. Fig.3 shows that a resistive shunt-feedback topology with Lg can break the trade-off between matching bandwidth and noise figure. Therefore, we can meet the matching requirement over the band of interest from 2 to 6GHz. Fig. 3. Matching bandwidth versus Rf
Fig. 2. Small signal model for input matching circuit
1292
Rf
Rs Vs
Rfb I2
Iout
Current buffer
Lg Cgs1
Ld
gm1Vgs
LL
Cgs2
RL
Vout
gm2Vgs2
Fig. 4. Small signal model for proposed LNA
C. Noise Flatten technique Compared with [1], which used a band-pass filter as input stages, the proposed LNA adopted with one spiral inductor which simplifies the circuit complexity and reduces the signal loss due to the lossy components. Furthermore, the shunt-resistive feedback topology and current reuse technique both benefit to low noise figure and noise shaping design. In [4][6], the shape of Noise figure frequency response is dominated by the quality factor of the input matching network of the first-stage amplifier. In other words, the additional noise generated from cascade and passive components will not be a major noisy source, nevertheless, it will be suppress by the first stage of amplifier. After carefully calculation, the noise factor is (ignore gate noise)
NF 1
RPAR 2 2 (s 2 s Onf Onf ) / OnF RS G M1 R S Q IN
Fig. 5. Die photograph of the Broadband LNA.
2
(4)
where RPAR is the parasitic resistance, RS is the source resistance, γ is the coefficient of drain noise, GM1 is the transconductance of M1, QIN is the input quality factor, and Onf 1/ (Lg Ls)(Cgs Cgd) . In order to achieve a flat noise frequency response, the input quality factor should be chosen carefully. The input quality factor should be chosen as close to the maximally flat condition (Qin=0.707) as possible. In this work, resistor in feedback loop, Lg, Ls, and Cgs of M1 composed of a RL-C resonance circuit. While Lg=1.3nH, Ls=0.3nH, Rfb=340ohm and gm=100mS, the perfect compromise between noise flatness and input matching will be made simultaneously. III. MEASUREMENT RESULTS The proposed broadband LNA was implemented in a TSMC 1P6M 0.18 um CMOS technology. The die photograph is shown in Fig. 5. The die area including testing pads is about 1.00 x 0.98 mm2. The circuit was tested on wafer for RF characterization. The LNA draws 8.3 mA and the supply voltage is 1.8 V.
Fig. 6. Simulated and measured results for S11 and S21
Fig. 6 shows the simulated and measured results of the input return loss and power gain of the broadband LNA. The power gain is over 13 dB with a 3-dB frequency band from 1.8 to 7GHz while the input return losses are below 10 dB from 2 to 6GHz. In Fig. 7, the result shows not only a good low noise performance of 3.0-3.7dB from 2 to 6GHz, but also a superior flatness of the noise frequency response.
1293
TABLE I S UMMARY OF THE IMPLEMENTED CMOS WIDEBAND LNA [1],JSSC [2],MWCL [3],CICC [5],JSSC [7],MWCL [8],CAS-II [9],MWCL This Work
Freq.[GHz] 2.3-9.2 3-10.6 1.2-11.9 2-4.6 2-4.6 0.4-10 2-11.5 1.5-7
S11
