A Built-In Self-Test Scheme for the Post-Bond Test of TSV s in 3D ICs
2011 29th IEEE VLSI Test Symposium
A Built-In Self-Test Scheme for the Post-Bond Test of TSVs in 3D ICs Yu-Jen Huang, Jin-Fu Li
Ji-Jan Chen*, Ding-Ming Kwai*, Yung-Fa Chou**, and Cheng-Wen Wu**
National Central University
Industrial Technology Research Institute (ITRI)
Jhongli, Taiwan 320
*Department of Electrical Engineering
Department of Electrical Engineering
*Information and Communication Research Lab. (ICL)
National Tsing-Hua University Hsinchu, Taiwan 310
architecture for TSV-based 3D ICs was proposed in [13]. Two
Abstract-Three-dimensional (3D) integration using through silicon via (TSV) has been widely acknowledged as one future integrated-circuit (IC) technology. A 3D IC including multiple dies connected with TSVs offers many benefits over current 2D ICs. However, the testing of 3D ICs is much more difficult than that of 2D ICs. In this paper, we propose a cost-effective built in self-test circuit (BIST) to test TSVs of a 3D IC. The BIST scheme, arranging the TSVs into arrays similar to memory, has the features of low test/diagnosis time and low silicon area cost. Simulation results show that the area overhead of the BIST circuit implemented with 0.18J.lm CMOS technolop; for a 16x32 TSV array in which each TSV cell size is 45J.lm is 2.24%. Also, the BIST needs only 130 clock cycles to test the TSV array with stuck-at faults. In comparison with the IEEE 1500·based test approach, the BIST scheme can achieve 85.2% area cost and 93.6% test time reduction.
different test interfaces handle the test controlling of the 3D Ie. An IEEE standard 1149.1-based and an IEEE standard 1500-based test interfaces are used for the bottom die and non-bottom dies, respectively. In [16], Chou et al. proposed a test integration method for handling the test operations of 3D ICs. An IEEE 1149.1-based and a modified IEEE 1149.1-based test interfaces control the design-for-testability circuits of the 3D IC. In [17], four analog self-test circuits were proposed to test the TSVs with pinhole defects. Leakage current of each self-test circuit is utilized to measure the TSV-to-substrate resistance, such that the short defect caused by a pinhole can be detected. Clearly, the testing of TSVs is essential for 3D ICs. One straightforward test approach to cover the defects of TSVs
I. INTRODUCTION
between dies is to wrap the terminals of each die with wrapper
Three-dimensional (3D) integration using through silicon
cells (e.g., IEEE 1149.1 boundary scan register or IEEE 1500
via (TSV) has been proposed as a very good alternative to cope
wrapper boundary register). But, this approach results in high
with the challenges faced by the current 2D technology [1].
area overhead since the number of TSVs in a 3D IC is usually
A 3D IC using TSV is implemented by stacking multiple dies
very huge. A cost-effective test approach thus is imperative.
which are vertically connected by TSVs. This enables that the
In this paper, we present a BIST scheme to test the TSVs of a
global interconnects in the 3D chip can be shortened such that
3D Ie. The scheme can test and diagnose the defective TSVs
high performance improvement can be achieved. Furthermore,
with very short test time and very low test cost.
high bandwidth can be achieved due to the significant increase
II. PRELIMINARY AND MOTIVATION
of 10 interconnection density provided by the TSVs. In addi
A. 3D Ie Testin g an d TSV Defects
tion, the 3D integration technology provides many advantages over 2D integration technology, such as high functionality,
The test flow for the 3D IC typically consists of three testing
low power, small form factor, and so on [2]. However, some
phases [4]: pre-bond test, known-good stack (KGS) test, and
challenges, e.g., in technology, yield improvement, thermal
final test (i.e., post-bond test). The pre-bond test is performed
management, infrastructure construction, and so on, should be
after the wafer fabrication. The quality of pre-bond test has a
overcome before volume production of 3D ICs using TSV
heavy impact on the final yield of 3D ICs. The KGS test is
becomes possible [2].
performed once a die is stacked. This can check weather the
Among these challenges, testing of 3D IC is a key issue
dies are damaged during the stacking process or not. If the
[3]-[5]. Recently, several research works of 3D IC testing
faulty stacked dies are identified, then the remaining dies will
have been reported [6]-[16]. In [6]-[10], the authors proposed
not be stacked. This can avoid wasting good dies. Finally, the
test optimization approaches to minimize the test cost of
final test is performed when the stacking process is completed.
3D ICs. In [11], testability of 3D random access memories
Several previous works have listed some possible defects
and content addressable memories was explored. In [12], two
in TSVs [12], [13]. TSV might be broken and have an open
effective test methods were proposed to test the TSVs of
defect or might have voids or pinholes along the TSV sidewall
3D ICs before bonding. The two test methods can be used
during the fabrication or metal filling process and have an
to screen out defective TSVs in pre-bond phase to reduce
open defect or a short defect. Before wafers are stacked, wafer
the stacking yield loss. A structured and scalable test access
thinning is executed. TSVs might crack due to the stress during
978-1-61284-656-9/111$26.00 ©2011 IEEE
20
o 0 0 1,-,00 1"'0 0
wafer stacking and bonding. Furthermore, an interconnection between two dies of a 3D IC may consist of the TSV, the microbump, and the redistribution layer (RDL). The post-bond
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o
100; 100: t
A Built-In Self-Test Scheme for the Post-Bond Test of TSVs in 3D ICs Yu-Jen Huang, Jin-Fu Li
Ji-Jan Chen*, Ding-Ming Kwai*, Yung-Fa Chou**, and Cheng-Wen Wu**
National Central University
Industrial Technology Research Institute (ITRI)
Jhongli, Taiwan 320
*Department of Electrical Engineering
Department of Electrical Engineering
*Information and Communication Research Lab. (ICL)
National Tsing-Hua University Hsinchu, Taiwan 310
architecture for TSV-based 3D ICs was proposed in [13]. Two
Abstract-Three-dimensional (3D) integration using through silicon via (TSV) has been widely acknowledged as one future integrated-circuit (IC) technology. A 3D IC including multiple dies connected with TSVs offers many benefits over current 2D ICs. However, the testing of 3D ICs is much more difficult than that of 2D ICs. In this paper, we propose a cost-effective built in self-test circuit (BIST) to test TSVs of a 3D IC. The BIST scheme, arranging the TSVs into arrays similar to memory, has the features of low test/diagnosis time and low silicon area cost. Simulation results show that the area overhead of the BIST circuit implemented with 0.18J.lm CMOS technolop; for a 16x32 TSV array in which each TSV cell size is 45J.lm is 2.24%. Also, the BIST needs only 130 clock cycles to test the TSV array with stuck-at faults. In comparison with the IEEE 1500·based test approach, the BIST scheme can achieve 85.2% area cost and 93.6% test time reduction.
different test interfaces handle the test controlling of the 3D Ie. An IEEE standard 1149.1-based and an IEEE standard 1500-based test interfaces are used for the bottom die and non-bottom dies, respectively. In [16], Chou et al. proposed a test integration method for handling the test operations of 3D ICs. An IEEE 1149.1-based and a modified IEEE 1149.1-based test interfaces control the design-for-testability circuits of the 3D IC. In [17], four analog self-test circuits were proposed to test the TSVs with pinhole defects. Leakage current of each self-test circuit is utilized to measure the TSV-to-substrate resistance, such that the short defect caused by a pinhole can be detected. Clearly, the testing of TSVs is essential for 3D ICs. One straightforward test approach to cover the defects of TSVs
I. INTRODUCTION
between dies is to wrap the terminals of each die with wrapper
Three-dimensional (3D) integration using through silicon
cells (e.g., IEEE 1149.1 boundary scan register or IEEE 1500
via (TSV) has been proposed as a very good alternative to cope
wrapper boundary register). But, this approach results in high
with the challenges faced by the current 2D technology [1].
area overhead since the number of TSVs in a 3D IC is usually
A 3D IC using TSV is implemented by stacking multiple dies
very huge. A cost-effective test approach thus is imperative.
which are vertically connected by TSVs. This enables that the
In this paper, we present a BIST scheme to test the TSVs of a
global interconnects in the 3D chip can be shortened such that
3D Ie. The scheme can test and diagnose the defective TSVs
high performance improvement can be achieved. Furthermore,
with very short test time and very low test cost.
high bandwidth can be achieved due to the significant increase
II. PRELIMINARY AND MOTIVATION
of 10 interconnection density provided by the TSVs. In addi
A. 3D Ie Testin g an d TSV Defects
tion, the 3D integration technology provides many advantages over 2D integration technology, such as high functionality,
The test flow for the 3D IC typically consists of three testing
low power, small form factor, and so on [2]. However, some
phases [4]: pre-bond test, known-good stack (KGS) test, and
challenges, e.g., in technology, yield improvement, thermal
final test (i.e., post-bond test). The pre-bond test is performed
management, infrastructure construction, and so on, should be
after the wafer fabrication. The quality of pre-bond test has a
overcome before volume production of 3D ICs using TSV
heavy impact on the final yield of 3D ICs. The KGS test is
becomes possible [2].
performed once a die is stacked. This can check weather the
Among these challenges, testing of 3D IC is a key issue
dies are damaged during the stacking process or not. If the
[3]-[5]. Recently, several research works of 3D IC testing
faulty stacked dies are identified, then the remaining dies will
have been reported [6]-[16]. In [6]-[10], the authors proposed
not be stacked. This can avoid wasting good dies. Finally, the
test optimization approaches to minimize the test cost of
final test is performed when the stacking process is completed.
3D ICs. In [11], testability of 3D random access memories
Several previous works have listed some possible defects
and content addressable memories was explored. In [12], two
in TSVs [12], [13]. TSV might be broken and have an open
effective test methods were proposed to test the TSVs of
defect or might have voids or pinholes along the TSV sidewall
3D ICs before bonding. The two test methods can be used
during the fabrication or metal filling process and have an
to screen out defective TSVs in pre-bond phase to reduce
open defect or a short defect. Before wafers are stacked, wafer
the stacking yield loss. A structured and scalable test access
thinning is executed. TSVs might crack due to the stress during
978-1-61284-656-9/111$26.00 ©2011 IEEE
20
o 0 0 1,-,00 1"'0 0
wafer stacking and bonding. Furthermore, an interconnection between two dies of a 3D IC may consist of the TSV, the microbump, and the redistribution layer (RDL). The post-bond
ro-o�
o
100; 100: t
