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A Compact Dynamic-Performance-Improved Current-Steering DAC with Random Rotation-Based Binary-Weighted Selection Wei-Te Lin, Student member, IEEE and Tai-Haur Kuo, Member, IEEE Abstract—Conventional binary-weighted current-steering DACs are generally operated with current groups where each group is binary-weighted and formed with predetermined members of a unit current-source array. This paper proposes a random rotation-based binary-weighted selection (RRBS) that efficiently performs dynamic-element matching (DEM) by randomly rotating the sequence of these units to form new binary-weighted current groups for each DAC output. Without using binary-to-thermometer decoders, RRBS features its simplicity and compactness of DEM realization. Compared to conventional binary-weighted DACs, RRBS DACs are insensitive to the mismatch of small-size current-sources and exhibit better dynamic performance. A 10-bit RRBS DAC is implemented with only 0.034mm2 in a standard 1P6M 1.8V 0.18μm CMOS process. Measured performance achieves >61dB spurious-free dynamic range (SFDR) in the Nyquist bandwidth with 500MS/s, while its active area is less than one-tenth of that required by state-of-the-art 10-bit current steering DACs. To the best of our knowledge, the proposed RRBS implements the smallest area for high-speed current-steering DACs up to now. Its SFDR is also comparable to that of 12-bit published designs. Three popular figures-of-merit (FOMs) are used to compare this design with other state-of-the-art 10~12-bit DACs, with the proposed design performing best with 2 FOMs. Index Terms — Digital-to-analog converter, current-steering, binary-weighted, Nyquist rate, dynamic element matching, DEM, random rotation-based binary-weighted selection, SFDR. This work was supported in part by the National Science Council under Grant NSC 99-2221-E-006-218-MY3. W.-T. Lin and T.-H. Kuo are with the Department of Electrical Engineering, National Cheng Kung University, Tainan 70101, Taiwan (e-mail: [email protected]; [email protected]). Source: IEEE Journal of Solid-State Circuits, Vol.47, No.2, pp.444-453 Date of Publication: 2012-02 ISSN: 0018-9200 Publisher: IEEE DOI: 10.1109/JSSC.2011.2168651 © 2012 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.
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I. INTRODUCTION Current-steering DACs are widely used in high-speed applications; however their linearity is severely affected by current-source matching accuracy. Matching accuracy is proportional to the transistor area under the same overdrive voltage. In addition, speed is affected by glitches caused by the large current source switching during mid-code transition for conventional binary-weighted DACs. Fig. 1(a) shows a diagram of a conventional binary-weighted current-steering DAC. For the sake of simplicity, switch drivers are not shown. In general, to obtain a better matching property, the weighted output currents, I(B0), I(B1), I(B2)…, are composed of unit current cells U1, U2, U3, etc. B0 controls only one unit current U1, while B1 controls U2 and U3, etc. Conventional binary DACs do not need decoding circuits, thus their structures are very simple. However, conventional binary DACs suffer from a drawback of larger glitch energy induced during mid-code transition due to the high switching activity of current sources, e.g 011…11 to 100…00. As shown in Fig. 1(b), to achieve minimum switching activity and thus reduce the resultant glitch energy, binary-to-thermometer decoders are often used to convert binary codes into thermometer codes to control unit current cells; however, the matching property of current sources is still a critical problem. Because of this, the DACs shown in Figs. 1(a) and (b) both need a large chip area to maintain matching accuracy. DAC inaccuracy due to current cell mismatches can be reduced by using large transistors with proper layout patterns or switching sequences [1]-[4]. However, large current sources result in large layout dimensions, which will cause a timing skew problem due to the presence of more parasitic component mismatches and increased routing complexity. As shown in Fig. 1(c), a calibration circuit can be used to effectively reduce the mismatch effect and increase DAC accuracy [5]-[9]. Either direct binary-weighted or binary-to-thermometer codes can
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be used to control the calibrated current sources. Nevertheless, the calibration adds design complexity and chip area. Currently, the most effective approach to reduce the mismatch effect and transistor size is the dynamic-element-matching (DEM) method implemented with a randomizer, as shown in Fig. 1(d). This can be designed to have minimum [10] or near-minimum [11] switching activity, as with the thermometer element selection in Fig. 1(b). The glitch energy can be further reduced in addition to the significant reduction in its transistor size, thus easily allowing for resolutions higher than 14-bit with a small chip area [11]. Except for when achieving both very high resolution and very high speed is desired simultaneously, very low switching activity may not be required since only a moderate reduction in glitch energy is needed with limited sacrifice of resolution and/or speed. A DEM method, random rotation-based binary-weighted selection (RRBS), is proposed which offers the circuit simplicity of binary-weighted coding and greatly reduces the mismatch effect. Compared with the conventional binary-weighted architecture shown in Fig. 1(a), the switching activity of RRBS is improved and the glitch energy issues are inherently reduced by randomization. Although its switching activity is not near-minimum, the binary-to-thermometer decoder is not required, thereby further saving chip area. As a result, the required implementation area is lower when compared to all other DEM architectures. To the best of the authors’ knowledge, the proposed RRBS is the smallest-area implementation method for high-speed current-steering DACs. Section II of this paper discusses the operational principle of the RRBS. In Section III, the dynamic performance of RRBS DACs is analyzed. Section IV discusses architecture design and analyzes RRBS implementation area, while Section V presents circuit implementation. Measurement results are given in Section VI and a conclusion is presented in Section VII.
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II. RRBS PRINCIPLE AND MISMATCH-INSENSITIVE PROPERTY As shown in Fig. 1(a), a conventional binary-weighted DAC is generally operated with current groups where each group is binary-weighted, and formed with predetermined members of a unit current-source array. Each group is controlled by a digit of binary input for connecting to or disconnecting from the DAC output. Fig. 2 shows the schematic of the proposed current-steering DAC with the RRBS method. RRBS efficiently performs DEM by randomly rotating the sequence of a unit current-source array to form new binary-weighted current groups for each DAC output. Unlike prior DEM techniques with extra binary-to-thermometer decoders and complex algorithm logic [12], the proposed RRBS is implemented with a simple randomizer circuit and without binary-to-thermometer decoders. Detailed information on the circuit realization is given in Section IV in the paper. A 3-bit binary-weighted DAC with 7 unit current sources is used to illustrate the principle of the conventional and RRBS methods shown in Figs. 3(a) and (b), respectively. DAC input codes of 6, 3, 7, 4 and 5 were used as examples. For the conventional method, current groups {U7, U6, U5, U4}, {U3, U2}, and {U1} are permanently fixed and respectively assigned to binary input codes B2, B1 and B0. For the RRBS method, randomization is realized through rotation, where left, right, and bi-directional rotations have similar performance, with the right-rotation demonstrated as an example for the sake of simplicity. R# represents the number (#) of right-rotation steps randomly generated in a range from 0 to 7. For an initial input of 6 with R4, where current groups {U7, U3, U2, U1}, {U6, U5}, and {U4} correspond to B2, B1, and B0, respectively, six current sources {U7, U6, U5, U3, U2, U1} are selected. For the second input of 3 with R5, where current groups {U7, U6, U2, U1}, {U5, U4}, and {U3} correspond to B2, B1, and B0, respectively, three current sources {U5, U4, U3}
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are selected. For the third input of 7 with R1, all current sources are selected. For the following inputs, binary current groups are similarly formed and selected. For the 3-bit DAC example, Fig. 4 shows the detailed RRBS circuit schematic, which is simply composed of a 3-bit rotator and a 3-output pseudo-random number generator (PRNG) with a repeat-cycle of 215-1. The rotator is composed of 21 multiplexers, while the PRNG is used to generate R# and is composed of 15 D-type Flip-Flops and several logic gates. The PRNG is modified from a common linear feedback shift register (LFSR) with added detection logics to avoid the lock up state. As an example, for an input with R4 as in Fig. 3(b), the new binary groups are B2 as {W7, W3, W2, W1}, B1 as {W6, W5}, and B0 as {W4}, where W7, W6..., W1 are used to control current switches in Fig. 2. A behavioral model of a 6-bit 63 unit current source DAC is used to verify the effect of mismatch-insensitivity. To simplify the RRBS design, the DAC is segmented into the three most significant bits (MSBs) and three least significant bits (LSBs), and implemented by the aforementioned 3-bit architecture shown in Fig. 4. The current source mismatch profile with the joint error distribution (50% linear + 50% quadratic) adopted from [12] is used. The respective current source mismatch values have a maximum standard deviation of 10%. Full-scale sinusoidal signals are used and simulated results were obtained by averaging 32 Monte-Carlo iterations, each corresponding to 4096 samples. Fig. 5(a) shows the simulated output spectrum of the DAC with both the conventional binary and RRBS methods. It can be seen that RRBS effectively suppresses the mismatch-induced distortion tones. Fig. 5(b) shows the spurious-free dynamic range (SFDR) with the RRBS method, where the SFDR is larger than 70dB. The input frequencies range from (73/4096)·fs to (1993/4096)·fs with a (60/4096)·fs step, while current source mismatches range from 0.25% to 10% with a 0.25% step. Because of the RRBS method, mismatch errors are
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randomized and distortion tones are greatly suppressed, which allows for the use of small-sized large-mismatched current sources. III. DYNAMIC PERFORMANCE OF RRBS DACS In current steering DACs, glitches occur when the current switches turn on / off at sampling instants. Increasing the input frequency in conventional binary-weighted DACs increases the amount of current switching, resulting in increased glitch energy. To analyze the switching property, the 6-bit DAC discussed at the end of Section II is used with full-swing inputs. Fig. 6 shows averaged switching activities with conventional binary, RRBS, and thermometer methods. Each input signal is composed of 4096 samples, and the switching activity is counted while each switch is toggled (on-to-off /off-to-on); after which, the sum for all input samples are averaged. As input signals approach the Nyquist bandwidth, and due to randomization, repeated selection of the same current sources in successive input samples occurs more frequently, thus switching activity is reduced by about 22% compared to the conventional binary-weighted method, resulting in better dynamic performance. Although RRBS has 17% more switching activity than the thermometer method at the Nyquist frequency, no other complicated algorithmic logics are required to further reduce the switching, except for when both very high resolution and very high speed are desired simultaneously. The distribution of switching activity for conventional binary-weighted and RRBS presented in Fig. 6 is plotted in detail in Fig. 7. Both Figs. 6 and 7(a) show that RRBS has more switching activity with lower input frequencies (fin ＜0.051fs). This does not present a problem for two reasons. First, the voltage transient step for low signal frequencies is fairly small; hence, the resulting distortion tones from glitch energy is small compared to that from device mismatch.
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Second, the RRBS can split the large switching activities into smaller switching activities. As in Fig. 7(a), in addition to a lower probability of large switching activity, instances of switching activity over 50 are also reduced. As aforementioned, when the input signal approaches the Nyquist frequency, the probability of having large switching activity for RRBS is reduced significantly, as Fig. 7(b) demonstrates. Timing skews between different current sources, switch drivers, and output paths are strongly dependent on the physical layout [13][14]. A complex layout may adequately compensate for timing skew, but the routing overhead could also increase wiring complexity, layout area, and power consumption [14]. If the unit current sources can be selected randomly, the timing skew can be suppressed. Furthermore, the compact layout of the RRBS DAC will also alleviate the timing skew due to smaller mismatches of parasitic components and wiring mismatches. IV. ARCHITECTURE DESIGN AND AREA ANALYSIS In this section, different RRBS DAC architectures are analyzed with respect to area and switching activity. 10-bit RRBS DACs, with their current source circuit shown in Fig. 8(a), are used as examples. To reduce the number of transistors and complex wiring connections of DACs, segmentation is required, with examples including a 6-bit RRBS with 4-bit conventional binary type (6R+4C), an 8-bit RRBS with 2-bit conventional binary type (8R+2C), and a fully 10-bit RRBS (10R). To simplify the design of a RRBS DAC, each RRBS encoder can be partitioned into two or more identical lower-bit sub-RRBS encoders. Hence, with 2 sub-RRBS, the above structures become 3R+3R+4C, 4R+4R+2C, and 5R+5R, respectively. The 4R+4R+2C structure shown in Fig. 8(b) is chosen for circuit implementation; the reason for this choice, however, will be elaborated later in this section. The above structures can be further partitioned as 2R+2R+2R+4C,
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2R+2R+2R+2R+2C, and 2R+2R+2R+2R+2R, respectively. Their respective allowable σ(I)/I calculated with the equation below [15] are 4.03%, 8.06%, and 11.4%.
(I )
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0.5 3.1
(1) 2B where σ(I)/I is the standard deviation of current source mismatch, and B is the matching accuracy
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bit, which is 4-bit, 2-bit, and 1-bit, respectively. With the calculated mismatches, simulation results show that the 3 structures all can achieve 70dB SFDR. Fig. 8(a) shows the current source circuit used for the DAC design. With a 250mV overdrive voltage, the gate area of MCS can be calculated by the following equation [15], 4 AVt2 A2 0.5 2 (V Vt ) W L GS 2 (I ) I
(2)
where Avt and Aβ are process matching parameters from the foundry. To boost output impedance, the cascoded transistor MCAS is designed with a 150 mV overdrive voltage and the same channel width as MCS. The switch pairs, MSW, are designed with minimum length and width. For equal driving ability, dummy switches are added in proportion to their respective weighting. Each switch driver is sized for a sharp transient edge with the desired cross-point voltage and drives 32 switches. The MCS area needed to achieve 2-bit matching accuracy is named AUCS, which is used as a unit for the following area calculations. According to the real circuit layout, the relative dimension is obtained as follows: 1 MUX has nearly the same dimensions as 4.5 AUCS, 1 switch pair has nearly the same dimensions as 1.25 AUCS, and one switch driver has nearly the same dimensions as 25 AUCS. The DAC area ASUM is composed of 4 major parts, i.e.
ASUM ACS ASW ASD AMUX
(3)
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where ACS, ASW, ASD, and AMUX are the total area of current-source array, switch array, switch driver array, and MUXs in randomizers, respectively. The area calculations for 7 different RRBS segmentations are made in accordance with the relative dimensions described above, with their respective results listed in Table I. For example, in the 4R+4R+2C segmentation shown in Fig. 8(b), ACS is counted for 36 × 36 unit current-sources, including the surrounding dummies. ASW is counted for all switches, including dummies, where each most significant bit (MSB) switch group is driven by 2 switch drivers, each upper least significant bit (ULSB) is driven by 1 switch driver, and each lower least significant bit (LLSB) switch group is driven by 1 switch driver. AMUX is counted for two 4-bit rotators, and each rotator is implemented with 4 × 15 unit MUXs, AUMUX. The area analyses of other segmentations are expressed in terms of the unit current-source area AUCS used for 4R+4R+2C. For example, 0.8AUCS is the corresponding unit current-source area of the 5R+5R architecture. The respective area ASUM is similarly calculated. Fig. 9 shows the comparisons of implementation area and switching activity for the different segmentations. The switching activities are calculated for input frequencies near the Nyquist bandwidth. Though a higher partition level results in lower implementation area, it also increases switching activity. The switching activity of the 5-level partition 2R+2R+2R+2R+2R is about 10% higher than that of the 2-level 5R+5R. In addition, mismatch-insensitivity is degraded because of fewer unit current sources in a RRBS sub-encoder, and thus the ability to spread out distortion tones is reduced. The 5R+5R and 2R+2R+2R+2R+2R types need only 1-bit matching accuracy, which is not achievable in reality because its gate length is smaller than the minimum rule using the 0.18μm process. However, it is possible to design a smaller-area 2R+2R+2R+2R+2R DAC using smaller devices in advanced processes. The 4R+4R+2C type optimizes the trade-off between area and switching activity and thus is chosen for circuit implementation. It eliminates
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binary-to-thermometer decoders to save 276AUCS, which corresponds to an estimated 7.5% area reduction. In addition, its estimated area is less than 15% of that of a conventional 10C DAC. V. CIRCUIT IMPLEMENTATION AND LAYOUT Fig. 8(b) shows the architecture of the implemented 4R+4R+2C DAC, where 4 MSBs and 4 ULSBs are RRBS, and 2 LLSBs are conventional binary-weighted. Its compact size is mainly achieved by eliminating binary-to-thermometer decoders, realizing simple DEM circuits and using small-area current sources. With an overdrive voltage of 250mV, the area of a unit current source, AUCS, is then decided with a channel width of 1.23μm and a channel length of 0.285μm, which corresponds to 3-bit matching accuracy rather than the 2-bit matching accuracy discussed in Section IV. This ensures that MCS can afford at least two contact placements at the drain/source of each unit current source to decrease series resistance. In addition, one extra bit for matching accuracy is preserved for design margins. Other circuits like cascoded transistors, switch pairs, and switch drivers are designed as presented in Section IV. With the RRBS technique, the matching accuracy of the current-source array was reduced from 10-bit to 3-bit, greatly reducing the active chip area and the resulting gradient mismatch error due to the shorter distances between transistors. To ensure that the MSB and ULSB portions have small mismatch, the layout of the whole MSB and ULSB current-source array is divided into 15 close regions, where each is composed of a MSB current-source group of 64 current units and a ULSB current-source group of 4 current units. The mismatch reduction is large and has been verified with Monte Carlo simulations. For the simulations, the element mismatch error profile with joint error distribution (50% linear + 50% quadratic) [12][16] is used, and the respective element mismatch values have 5.7% standard deviation for 3-bit matching accuracy. The simulated INL curves from
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3000 Monte Carlo simulations are shown in Fig. 12 (a), with their distribution shown in Fig. 12(b). Without RRBS, the maximum INL is about 3.3 LSB. In consideration to edge effects, 4 dummy rows and columns were placed surrounding the current-source array. As shown in Table I, the array of 36 × 36 unit current source including dummies is only 80μm × 70μm, thus reducing the gradient errors. Therefore, special layout patterns like the double centroid adopted in [1][3][9] or the switching sequence optimization in [2] [11][12][16][17] are not necessary. The floor plan is arranged as in Fig. 10, where the CS array is composed of current sources and cascoded transistors. In addition, digital circuits include RRBS circuits and input registers. The CS array, SW array, SW driver array, and digital circuits occupy respective areas of 0.0056mm2, 0.0086mm2, 0.005mm2, and 0.0088mm2. The active area is 130μm × 263μm ≈ 0.034mm2. The CS array is even smaller than the digital circuits, which emphasizes the importance of eliminating binary-to-thermal decoders and reducing the RRBS circuit. As described in Section IV, the binary-to-thermometer decoders correspond to 7.5% of the active area, where the ratios between each block matched the estimates in Table I. Hence, the actual layout verifies the area analysis described in Section IV. The actual layout of digital blocks is slightly larger than that calculated by equation (3) because it contains other small-area circuits such as the pseudo random number generator (PRNG), the input register array, and some dummy buffers for timing synchronization. VI. MEASUREMENT RESULTS Fig. 11 shows the measurement setup with a chip-on-board configuration. The DAC’s output current is converted to a voltage through an off-chip 50Ω resistive differential load and coupled to a spectrum analyzer through a wideband transformer. The digital inputs and clock are produced by
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Agilent ParBERT 81250. All measurements were performed by a full-scale load current of 10mA, which corresponds to a 250mV voltage swing at the output pins of the IC. The measured INL curves are shown in Fig. 13, with the measured INL curve with RRBS disabled shown in Fig. 13(a). 20 measured INL curves and their averaged INL curve are shown in Fig. 13(b), where the maximum INL is 3LSB. The averaged INL is small while RRBS is enabled. Three chips were measured and their results were found to be about the same. From Figs. 12 and 13, the simulated INL approximates the measured one, which validates the design. Figs. 14(a) and (b) show the respective power spectrum density (PSD) plots of the DAC with and without RRBS enabled for a 5MHz signal clocked at 500MS/s. With the RRBS enabled, the SFDR is increased to above 73dB. Fig. 15 shows the IMD3 spectrum with 245MHz and 247MHz signals clocked at 500MS/s, with the measured IMD3 being 62dB. Fig. 16 shows the SFDR and IMD3 over the entire Nyquist bandwidth clocked at 500MS/s. At low frequencies, the converter achieves 74dB SFDR, while it retains >61dB SFDR and >62dB IMD3 in the whole Nyquist bandwidth. Fig. 17 shows measurements with fin=0.01fs under sampling rates up to 800MS/s. The measured noise spectral density (NSD) plot is shown in Fig. 18. With RRBS enabled, the distortion tones due to mismatch are randomized then distributed into the noise floor. The noise floor is then raised by about 2dB. Two comparisons are made to further show RRBS performance. The first comparison with the conventional binary-weighted method is used to judge the effectiveness and compactness of the RRBS method. Figs. 19(a) and (b) show the respective SFDR and area comparisons with published binary-weighted current-steering 10~14-bit DACs. These DACs are implemented with the conventional binary-weighted architecture without binary-to-thermometer decoders. Our converter comprises an extremely small chip size, and achieves >61dB SFDR with a 250MHz signal
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bandwidth, which is twice the bandwidth of the nearest comparable DAC [17], as demonstrated in Fig. 19. The second comparison, summarized in Table II, was made with state-of-the-art 10~12-bit DACs on resolution, bandwidth, power consumption, and SFDR. Based on these aspects, the three most applicable figures-of-merit (FOMs) proposed in [20] [22] and [23] are adopted. FOMs [4] [21], which respectively emphasize high power efficiency and high output swing, are not adopted. Detailed definitions of the adopted FOMs are given in Table III. The proposed DAC performs well with FOM1, and best with FOM2 and FOM3. This work achieves good SFDR with less than one-tenth the active area required by state-of-the-art 10-bit current-steering DACs. VII. CONCLUSIONS In this paper, random rotation-based binary-weighted selection (RRBS) is proposed. Its mismatch-insensitivity, dynamic performance and implementation area are analyzed. A 10-bit RRBS current-steering DAC is implemented in a 0.18μm CMOS process. Its implementation area is much smaller than that of other published state-of-the-art 10-bit current-steering DACs. Its compact size is mainly achieved by eliminating binary-to-thermometer decoders, realizing simple DEM circuits, and using small-area current sources. To the best of our knowledge, the proposed RRBS is the smallest-area implementation method currently available for high-speed currentsteering DACs. The proposed DAC also achieves very good SFDR compared with other state-of-the-art 10~12-bit DACs. Despite the RRBS DACs not having minimum switching activities as with the thermometer types, their switching activities are low enough for most DAC requirements. In addition, the presented RRBS DACs do not use complex algorithms and are easily realized. Hence, other than DACs aimed at achieving both very high resolution and very high speed simultaneously, the proposed RRBS is very suitable for most current-steering DAC designs.
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ACKNOWLEDGMENT The authors would like to thank the National Chip Implementation Center (CIC), Taiwan, for their support of chip measurement. REFERENCES [1] A. van den Bosch, M. Borremans, M. Steyaert, and W. Sansen, “A 10-bit 1-GSample/s Nyquist current-steering CMOS D/A converter,” IEEE J. Solid-State Circuits, vol. 36, no. 3, pp. 315–324, Mar. 2001. [2] J. Bastos, A. M. Marques, M. S. J. Steyaert and W. Sansen, “A 12-Bit Intrinsic Accuracy High-Speed CMOS DAC,” IEEE J. Solid-State Circuits, vol. 33, no. 12, pp. 1959-1969, Dec. 1998. [3] P. Palmers and M. S. J. Steyaert, “A 10-Bit 1.6-GS/s 27-mW Current-Steering D/A Converter with 550-MHz 54-dB SFDR Bandwidth in 130-nm CMOS,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 57, no. 11, pp. 2870-2879, Nov. 2010. [4] C.-H. Lin, F. M. L. van der Goes, J. R. Westra, J. Mulder, Y. Lin, E. Arslan, E. Ayranci, X. Liu and K. Bult, “A 12 bit 2.9 GS/s DAC With IM3 > 60 dBc beyond 1GHz in 65 nm CMOS,” IEEE J. Solid-State Circuits, vol. 44, no. 12, pp. 3285-3293, Dec. 2009. [5] W.-H. Tseng, C.-W. Fan and J.-T. Wu, “A 12b 1.25GS/s DAC in 90nm CMOS with >70dB SFDR up to 500MHz,” in IEEE Solid-State Circuits Conf. Dig. Tech. Papers, 2011, pp. 192-193. [6] A. R. Bugeja and B.-S. Song, “A Self-Trimming 14-b 100-MS/s CMOS DAC,” IEEE J. Solid-State Circuits, vol. 35, no. 12, pp. 1841-1852, Dec. 2000. [7] M. P. Tiilikainen, “A 14-bit 1.8-V 20-mW 1-mm2 CMOS DAC,” IEEE J. Solid-State Circuits, vol. 36, no. 7, pp. 1144-1147, July. 2001. [8] D.-L. Shen, Y.-C. Lai and T.-C. Lee, “A 10-Bit Binary-Weighted DAC with Digital Background LMS Calibration,” in Proc. IEEE Asian Solid-State Circuits Conf. (ASSCC), Nov. 2007, pp. 352-355. [9] J.-H. Chi, S.-H. Chu and T.-H. Tsai, “A 1.8-V 12-Bit 250MS/s 25-mW Self-calibrated DAC,” in Proc. IEEE Eur. Solid-State Circuits Conf. (ESSCIRC), Sep. 2010, pp. 222-225.
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[10] D.-H. Lee and T.-H. Kuo, “Randomized Thermometer-Coding Digital-to-Analog Converter and Method Therefor,” U.S. Patent 7,679,539, Mar. 16, 2010. [11] D.-H. Lee, T.-H. Kuo and K.-L. Wen, “Low-cost 14-bit Current-steering DAC with a Randomized Thermometer-coding Method,” IEEE Trans. Circuits Syst. II, Exp. Briefs , vol. 56, no. 2, pp. 137–141, Feb. 2009. [12] D.-H. Lee, Y.-H. Lin and T.-H. Kuo, “Nyquist-Rate Current-Steering Digital-to-Analog Converters With Random Multiple Data-Weighted Averaging Technique and QN Rotated Walk Switching Scheme,” IEEE Trans. Circuits Syst. II, Exp. Briefs , vol. 53, no. 11, pp. 1264-1268, Nov. 2006. [13] T. Chen and G. G. E. Gielen, “The Analysis and Improvement of a Current-Steering DACs Dynamic SFDR-I: The Cell-Dependent Delay Difference,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 53, no. 1, pp. 3-15, Jan. 2006. [14] T. Chen and G. G. E. Gielen, “The Analysis and Improvement of a Current-Steering DACs Dynamic SFDR-II: The Output-Dependent Delay Difference,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 54, no. 2, pp. 268-279, Feb. 2007. [15] A. van den Bosch, M. S. J. Steyaert, and W. Sansen, “An Accurate Yield Model for CMOS Current-steering D/A Converters,” in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS), 2000, pp. 105–108. [16] Y. Cong and R. L. Geiger, “Switching Sequence Optimization for gradient Error Compensation in Thermometer-Decoded DAC Array,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 47, no. 7, pp. 585-595, July 2000. [17] J. Deveugele and M. S. J. Steyaert, “A 10-bit 250-MS/s Binary-Weighted Current-Steering DAC,” IEEE J. Solid-State Circuits, vol. 41, no. 2, pp. 320-329, Feb. 2006. [18] M. Borremans, A. V. den Bosch, M. Steyaert, and W. Sansen, “A low power, 10-bit CMOS D/A converter for high speed applications,” in Proc. IEEE Custom Integrated Circuits Conf. (CICC), May 2001, pp. 157–160. [19] Y. Ikeda, M. Frey and A. Matsuzawa, “A 14-bit 100-MS/s Digitally Calibrated Binary-Weighted Current-Steering CMOS DAC without Calibration ADC,” in Proc. IEEE Asian Solid-State Circuits Conf. (ASSCC), Nov. 2007, pp. 356-359.
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[20] A. Van den Bosch, M. S. J. Steyaert, and W. Sansen, “Solving static and dynamic performance limitations for high-speed D/A converters,” in Analog Circuit Design: Scalable Analog Circuit Design, High-Speed D/A Converters, RF Power Amplifiers. Norwell, MA: Kluwer, 2002, pp. 189–210. [21] D. Giotta, P. Pessl, M. Clara, W. Klatzer and R. Gaggl, “Low-power 14-bit Current Steering DAC for ADSL2+/CO Applications in 0.13μm CMOS,” in Proc IEEE Eur. Solid-State Circuits Conf. (ESSCIRC), Sep. 2004, pp. 163–166. [22] M. Clara, W. Klatzer, B. Seger, A. D. Giandomenico and L. Gori, “A 1.5V 200MS/s 13b 25mW DAC with randomized nested background calibration in 0.13μm CMOS,” in IEEE Solid-State Circuits Conf. Dig. Tech. Papers, 2007, pp. 250–251. [23] T. Chen, P. Geens, G. van der Plas, W. Dehaene and Georges Gielen, “A 14-bit 130-MHz CMOS Current-Steering DAC with Adjustable INL,” in Proc IEEE Eur. Solid-State Circuits Conf. (ESSCIRC), Sep. 2004, pp. 167–170.
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TABLES CAPTIONS TABLE I
AREA COMPARISONS FOR DIFFERENT RRBS SEGMENTATIONS.
TABLE II
COMPARISON WITH STATE-OF-THE-ART 10~12-BIT CURRENT-STEERING DACS.
TABLE III DETAILED DEFINITIONS OF DAC FOMS. FIGURES CAPTIONS Fig. 1 Diagram of (a) conventional binary-weighted coding, (b) conventional thermometer coding, (c) hybrid coding with current calibration, and (d) randomized DEM coding. Fig. 2 Diagram of the proposed DAC with random rotation-based binary- weighted selection (RRBS). Fig. 3 Operating principle of the (a) conventional binary-weighted method and (b) random rotation-based binary-weighted selection (RRBS) method where R# represents the number of right-rotation steps. Fig. 4 Detailed implementation circuits of a 3-bit RRBS example where MUX denotes multiplexer and DFF denotes D-type flip-flop. Fig. 5(a) Simulated output spectrum of a 6-bit DAC with a 10% standard deviation of current-source mismatch for the conventional binary-weighted and RRBS methods, respectively. (b) SFDR of the DAC employing RRBS with different input frequencies and mismatches. Fig. 6 Comparison of switching activities with different decoding methods in a 6-bit DAC. Input signals are with full-swing. Fig. 7 The distribution shows the occurrence of switching activity with (a) low input frequency and (b) high input frequency. Fig. 8 (a) The adopted current cell circuit and (b) the architecture of the implemented 4R+4R+2C RRBS DAC. Fig. 9 Area and switching activity of different segmentation types; each type is partitioned with its respective identical sub-RRBS encoders. Fig. 10 Photograph of the proposed DAC. Fig. 11 Measurement setup. Fig. 12(a) Simulated INL curves from 3000 Monte Carlo simulations and (b) their INL distribution. Fig. 13(a) Measured INL curve with RRBS disabled and (b) 20 measured INL curves with RRBS enabled (gray color) and their averaged INL curve (black color). Fig. 14 PSD plots (a) with and (b) without RRBS enabled for a 5MHz output signal clocked at 500MS/s. Fig. 15 Measured IMD3 spectrum with 245MHz and 247MHz signals clocked at 500MS/s. Fig. 16 SFDR and IMD3 vs. signal frequency clocked at 500MS/s.
18
Fig. 17 Measured SFDR for fin=0.01fs with sampling rates up to 800MS/s. Fig. 18 Measured noise spectral density (NSD). Fig. 19 Comparison with published binary-weighted DACs on (a) SFDR vs. signal frequency and (b) active area.
19
TABLE I AREA COMPARISONS FOR DIFFERENT RRBS SEGMENTATIONS. Segment
ACS
ASW
ASD
AMUX
ASUM
5C+5C 23×(36×36)AUCS (36×32]AUSW (36)AUSD 0 5R+5R 0.8×(36×36)AUCS [(32+32)×31)]AUSW [(1+1)×31]AUSD 2×5×31AUMUX 4R+4R+2C 1× (36×36)AUCS [(64+32)×15)+32×2]AUSW [(2+1)×15)+2]AUSD 2×4×15AUMUX 3R+3R+4C 1.7× (36×36)AUCS [(128+32)×7)+(32×4]]AUSW [(4+1)×7)+4]AUSD 2×3×7AUMUX 3R+3R+3R+1C 0.8×(36×36)AUCS [(128+32+32)×7+32]AUSW [(4+1+1)×7+1]AUSD 3×3×7AUMUX 2R+2R+2R+4C 1.7×(36×36)AUCS [(256+64+32)×3+(32×4)]AUSW [(8+2+1)×3+4]AUSD 3×2×3AUMUX 2R+2R+2R+2R+2R 0.8×(36×36)AUCS [(256+64+32+32+32)×3]AUSW [(8+2+1+1+1)×3]AUSD 5×2×3AUMUX 2R+2R+2R+2R+2C 1×(36×36)AUCS [(256+64+32+32)×3+(32×2)]AUSW [(8+2+1+1)×3+2]AUSD 4×2×3AUMUX Conditions: 1. AUCS(10-bit accuracy)=74.815μm2, AUCS(4-bit accuracy)=5.546μm2, AUCS(3-bit accuracy)=4.135μm2, AUCS(2-bit accuracy)#=3.268μm2, AUCS(1-bit accuracy)#*=2.577μm2 2. AUCS=2.15×1.52μm2, AUSW≈1.25AUCS, AUSD≈25AUCS, AUMUX≈4.5AUCS (including pitch-to-pitch space) 3. A 4-bit binary-to-thermometer decoder =40×15μm2, Two 4-bit decoders ≈367AUCS # Cannot contain two contacts on the width of drain/source region. * Violates the minimum gate length rule.
32148AUCS 6462AUCS 4891AUCS 4927AUCS 4116AUCS 4689AUCS 3342AUCS 3574AUCS
TABLE II COMPARISON WITH STATE-OF-THE ART 10~12-BIT CURRENT-STEERING DACS. [5] [3] [4] [17] ISSCC 2011 TCASI 2010 JSSC 2009 JSSC 2006 Resolution, N 10 12 10 12 10 Technology 0.18μm 90nm 0.13μm 65nm 0.18μm Sample rate (MS/s) 500 1250 1600 2900 250 Iload (mA) 10 16 10 50 10 Ptotal (mW) 24 128 23.6 188 22 BWN (MHz) 250 500 325 100 125 Area (mm2) 0.034 0.825 0.5 0.31 0.35 SFDRDC (dB) 74 75 74 74 74 SFDRNyquist (dB) 61 66 50 N/A 60 FOM1 1.07E+04 1.23E+04 2.18E+03 5.82E+03 1.60E+04 FOM2 7.50E+07 3.29E+07 N/A 4.02E+07 8.25E+07 FOM3 1.94E+04 2.46E+04 7.03E+03 1.66E+04 3.14E+05 ※ All FOMs are calculated with the performance under the power given in the respective papers. This Work
[1] JSSC 2001 10 0.35μm 1000 20 110 500 0.35 74 61 4.65E+03 3.52E+07 1.33E+04
TABLE III DETAILED DEFINITIONS OF DAC FOMS. Term Formula Origin Definition
FOM1
2 N BW N Ptotal [20] BWN: Signal BW retains 6×N dB SFDR in MHz.
FOM2 2
SFDRDC 1.76 6.02
FOM3
SFDRNyq u ist 1.76
6.02 2 f clk 1 2 Ptotal I load Rload 2
[22] SFDRDC/ SFDRNyquist: Best/ Worst measured SFDR in whole Nyquist bandwidth.
2 N BW N Ptotal Area
[23] Area: Active area in mm2.
Wei-Te Lin and Tai-Haur Kuo
20
U7
U6
U5
U4
U3
U2
U1
U7
U6
U5
U4
U3
U2
U1
Iout W7
W6
W5
W4
W3
W2
Iout
W1
W7
W5
W4
W3
W2
W1
Binary-to-thermometer
Wiring connection
B2
BN-1
W6
B1
B0
B2
BN-1
B1
(a)
B0
(b)
Calibration circuit U7
U6
U5
U4
U3
U2
U1
Iout U7
U6
U5
U4
U3
U2
U1
W7
W6
Iout W7
W6
W5
W4
W3
W2
B2
B1
W4
W3
W2
W1
Randomizer
W1
Binary-to-thermometer
Binary-weighted or binary-to-thermometer
BN-1
W5
B0
BN-1
B2
B1
B0
(d) (c) Fig. 1 Diagram of (a) conventional binary-weighted coding, (b) conventional thermometer coding, (c) hybrid coding with current calibration, and (d) randomized DEM coding.
U7
U6
U5
U4
U3
U2
U1
Iout W7
W6
W5
W4
W3
W2
W1
Simple randomizer
Wiring connection
BN-1
B2 B1 B0 Fig. 2 Diagram of the proposed DAC with random rotation-based binary-weighted selection (RRBS).
Wei-Te Lin and Tai-Haur Kuo
21
Conventional Binary-weighted Input U7 U6 U5 U4 U3 U2 U1
RRBS Input (R#) U7 U6 U5 U4 U3 U2 U1
110
B2 B2 B2 B2 B1 B1 B0
110(R4)
B2 B1 B1 B0 B2 B2 B2
011
B2 B2 B2 B2 B1 B1 B0
011(R5)
B2 B2 B1 B1 B0 B2 B2
111
B2 B2 B2 B2 B1 B1 B0
111(R1)
B0 B2 B2 B2 B2 B1 B1
100
B2 B2 B2 B2 B1 B1 B0
100(R2)
B1 B0 B2 B2 B2 B2 B1
101
B2 B2 B2 B2 B1 B1 B0
101(R0)
B2 B2 B2 B2 B1 B1 B0
(a) (b) Fig. 3 Operating principle of the (a) conventional binary-weighted method and (b) random rotation-based binary-weighted selection (RRBS) method where R# represents the number of right-rotation steps.
RotatorW7
W6
W5
W4
W3
W2
W1
PRNG CK
CK
MUX
MUX
MUX
MUX
MUX
MUX
MUX
1-step rotation
DFF
Q0
DFF CK
CK
MUX
MUX
MUX
MUX
MUX
MUX
MUX
2-step rotation
MUX
MUX
MUX
MUX
MUX
MUX
MUX
4-step rotation
DFF
Q5
DFF
Q10
DFF
Q2
DFF
Q7
DFF
DFF
Q12
DFF
DFF
Q4
CK Q8
DFF
Q9
CK
CK
CK Q11
DFF
Q3
CK
CK Q6
CK
CK
DFF
DFF
CK
CK
CK Q1
Q13
DFF
Q14
Q0
B2
B1
B0
Q14
Fig. 4 Detailed implementation circuits of a 3-bit RRBS example where MUX denotes multiplexer and DFF denotes D-type flip-flop.
Wei-Te Lin and Tai-Haur Kuo
22
(a) (b) Fig. 5(a) Simulated output spectrum of a 6-bit DAC with a 10% standard deviation of current-source mismatch for the conventional binary-weighted and RRBS methods, respectively. (b) SFDR of the DAC employing RRBS with different input frequencies and mismatches.
Averaged Switching / Sample
60
Conventional Binary RRBS ․․ Thermometer
50
40 30 20
10 0 0.0
0.1
0.2
0.3
0.4
0.5
Normalized Frequency (Fin/Fs)
Fig. 6 Comparison of switching activities with different decoding methods in a 6-bit DAC. Input signals are with full-swing.
Wei-Te Lin and Tai-Haur Kuo
23
(b)
(a)
Fig. 7 The distribution shows the occurrence of switching activity with (a) low input frequency and (b) high input frequency.
VDD MCS
… MSB
CS Array
ULSB CS Array
…
…
MSB
ULSB SW Array
…
…
MSB … SW_DR Array
ULSB SW_DR Array
MCAS
MSW
D
D
…SW Array
VDD
clk inp
clk D
D
GND
inn
LLSB CS Array
LLSB SW Array
…
…
4-bit MSB RRBS Encoder
4-bit ULSB RRBS Encoder
B9
B8
B7
B6
B5 B4
B3
B2
outp outn
LLSB SW_DR Array
B1 B0
(a) (b) Fig. 8(a) The current cell circuit and (b) the architecture of the implemented 4R+4R+2C RRBS DAC.
Wei-Te Lin and Tai-Haur Kuo
24
Fig. 9 Area and switching activity of different segmentation types; each type is partitioned with its respective identical sub-RRBS encoders.
Bias
CS Array
263μm
130μm
SW Array
SW Driver Array
Digital Circuits including RRBS
Fig. 10 Photograph of the proposed DAC.
50Ω Digital Inputs
DUT DAC
100Ω
T1-1T
To Spectrum Analyzer
50Ω Fig. 11 Measurement setup.
Wei-Te Lin and Tai-Haur Kuo
25
(a)
(b)
Fig. 12(a) Simulated INL curves from 3000 Monte Carlo simulations and (b) their INL distribution.
(b) (a) Fig. 13(a) Measured INL curve with RRBS disabled and (b) 20 measured INL curves with RRBS enabled (gray color) and their averaged INL curve (black color).
RRBS Enabled
(a)
RRBS Disabled
(b)
Fig. 14 PSD plots (a) with and (b) without RRBS enabled for a 5MHz output signal clocked at 500MS/s.
Wei-Te Lin and Tai-Haur Kuo
26
Fig. 15 Measured IMD3 spectrum with 245MHz and 247MHz signals clocked at 500MS/s.
SFDR (dB)
75 70 65 60
IMD3 SFDR
55 1
10
100
Signal Frequency, Fin (MHz)
Fig. 16 SFDR and IMD3 vs. signal frequency clocked at 500MS/s.
75
SFDR (dB)
70 65 60 55 Fin=0.01Fs 50 100
200
300
400
500
600
700
800
Sampling Frequency, Fs (MHz)
Fig. 17 Measured SFDR for fin=0.01fs with sampling rates up to 800MS/s.
Wei-Te Lin and Tai-Haur Kuo
27
-130
NSD (dBc/Hz)
RRBS Enabled RRBS Disabled -135
-140
-145 0
50
100
150
200
250
Input Frequency, Fin (MHz)
Fig. 18 Measured noise spectral density (NSD).
85
80
Active Area (mm2)
1
SFDR (dB)
75 70 65 60
55 50 45 40 0.01
14 bit 0.18µm
This work, 10bit@500MS/s JSSC2006, 10bit@250MS/s CICC2001, 10bit@30MS/s ASSCC2007, 14bit@100MS/s JSSC2001, 14bit@100MS/s ASSCC2007, 10bit@1GS/s
0.1
1
14 bit 0.18µm
0.75
0.5
10 bit 0.18µm 10 bit 0.35µm
0.25
10 bit 0.18µm
10 bit 0.18µm 10
Signal Frequency, Fin (MHz)
100
0
This Work
JSSC 2006
CICC ASSCC JSSC ASSCC 2001 2007 2001 2007
(b) (a) Fig. 19 Comparison with published binary-weighted DACs on (a) SFDR vs. signal frequency and (b) active area.
Wei-Te Lin and Tai-Haur Kuo
A Compact Dynamic-Performance-Improved Current-Steering DAC with Random Rotation-Based Binary-Weighted Selection Wei-Te Lin, Student member, IEEE and Tai-Haur Kuo, Member, IEEE Abstract—Conventional binary-weighted current-steering DACs are generally operated with current groups where each group is binary-weighted and formed with predetermined members of a unit current-source array. This paper proposes a random rotation-based binary-weighted selection (RRBS) that efficiently performs dynamic-element matching (DEM) by randomly rotating the sequence of these units to form new binary-weighted current groups for each DAC output. Without using binary-to-thermometer decoders, RRBS features its simplicity and compactness of DEM realization. Compared to conventional binary-weighted DACs, RRBS DACs are insensitive to the mismatch of small-size current-sources and exhibit better dynamic performance. A 10-bit RRBS DAC is implemented with only 0.034mm2 in a standard 1P6M 1.8V 0.18μm CMOS process. Measured performance achieves >61dB spurious-free dynamic range (SFDR) in the Nyquist bandwidth with 500MS/s, while its active area is less than one-tenth of that required by state-of-the-art 10-bit current steering DACs. To the best of our knowledge, the proposed RRBS implements the smallest area for high-speed current-steering DACs up to now. Its SFDR is also comparable to that of 12-bit published designs. Three popular figures-of-merit (FOMs) are used to compare this design with other state-of-the-art 10~12-bit DACs, with the proposed design performing best with 2 FOMs. Index Terms — Digital-to-analog converter, current-steering, binary-weighted, Nyquist rate, dynamic element matching, DEM, random rotation-based binary-weighted selection, SFDR. This work was supported in part by the National Science Council under Grant NSC 99-2221-E-006-218-MY3. W.-T. Lin and T.-H. Kuo are with the Department of Electrical Engineering, National Cheng Kung University, Tainan 70101, Taiwan (e-mail: [email protected]; [email protected]). Source: IEEE Journal of Solid-State Circuits, Vol.47, No.2, pp.444-453 Date of Publication: 2012-02 ISSN: 0018-9200 Publisher: IEEE DOI: 10.1109/JSSC.2011.2168651 © 2012 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.
2
I. INTRODUCTION Current-steering DACs are widely used in high-speed applications; however their linearity is severely affected by current-source matching accuracy. Matching accuracy is proportional to the transistor area under the same overdrive voltage. In addition, speed is affected by glitches caused by the large current source switching during mid-code transition for conventional binary-weighted DACs. Fig. 1(a) shows a diagram of a conventional binary-weighted current-steering DAC. For the sake of simplicity, switch drivers are not shown. In general, to obtain a better matching property, the weighted output currents, I(B0), I(B1), I(B2)…, are composed of unit current cells U1, U2, U3, etc. B0 controls only one unit current U1, while B1 controls U2 and U3, etc. Conventional binary DACs do not need decoding circuits, thus their structures are very simple. However, conventional binary DACs suffer from a drawback of larger glitch energy induced during mid-code transition due to the high switching activity of current sources, e.g 011…11 to 100…00. As shown in Fig. 1(b), to achieve minimum switching activity and thus reduce the resultant glitch energy, binary-to-thermometer decoders are often used to convert binary codes into thermometer codes to control unit current cells; however, the matching property of current sources is still a critical problem. Because of this, the DACs shown in Figs. 1(a) and (b) both need a large chip area to maintain matching accuracy. DAC inaccuracy due to current cell mismatches can be reduced by using large transistors with proper layout patterns or switching sequences [1]-[4]. However, large current sources result in large layout dimensions, which will cause a timing skew problem due to the presence of more parasitic component mismatches and increased routing complexity. As shown in Fig. 1(c), a calibration circuit can be used to effectively reduce the mismatch effect and increase DAC accuracy [5]-[9]. Either direct binary-weighted or binary-to-thermometer codes can
3
be used to control the calibrated current sources. Nevertheless, the calibration adds design complexity and chip area. Currently, the most effective approach to reduce the mismatch effect and transistor size is the dynamic-element-matching (DEM) method implemented with a randomizer, as shown in Fig. 1(d). This can be designed to have minimum [10] or near-minimum [11] switching activity, as with the thermometer element selection in Fig. 1(b). The glitch energy can be further reduced in addition to the significant reduction in its transistor size, thus easily allowing for resolutions higher than 14-bit with a small chip area [11]. Except for when achieving both very high resolution and very high speed is desired simultaneously, very low switching activity may not be required since only a moderate reduction in glitch energy is needed with limited sacrifice of resolution and/or speed. A DEM method, random rotation-based binary-weighted selection (RRBS), is proposed which offers the circuit simplicity of binary-weighted coding and greatly reduces the mismatch effect. Compared with the conventional binary-weighted architecture shown in Fig. 1(a), the switching activity of RRBS is improved and the glitch energy issues are inherently reduced by randomization. Although its switching activity is not near-minimum, the binary-to-thermometer decoder is not required, thereby further saving chip area. As a result, the required implementation area is lower when compared to all other DEM architectures. To the best of the authors’ knowledge, the proposed RRBS is the smallest-area implementation method for high-speed current-steering DACs. Section II of this paper discusses the operational principle of the RRBS. In Section III, the dynamic performance of RRBS DACs is analyzed. Section IV discusses architecture design and analyzes RRBS implementation area, while Section V presents circuit implementation. Measurement results are given in Section VI and a conclusion is presented in Section VII.
4
II. RRBS PRINCIPLE AND MISMATCH-INSENSITIVE PROPERTY As shown in Fig. 1(a), a conventional binary-weighted DAC is generally operated with current groups where each group is binary-weighted, and formed with predetermined members of a unit current-source array. Each group is controlled by a digit of binary input for connecting to or disconnecting from the DAC output. Fig. 2 shows the schematic of the proposed current-steering DAC with the RRBS method. RRBS efficiently performs DEM by randomly rotating the sequence of a unit current-source array to form new binary-weighted current groups for each DAC output. Unlike prior DEM techniques with extra binary-to-thermometer decoders and complex algorithm logic [12], the proposed RRBS is implemented with a simple randomizer circuit and without binary-to-thermometer decoders. Detailed information on the circuit realization is given in Section IV in the paper. A 3-bit binary-weighted DAC with 7 unit current sources is used to illustrate the principle of the conventional and RRBS methods shown in Figs. 3(a) and (b), respectively. DAC input codes of 6, 3, 7, 4 and 5 were used as examples. For the conventional method, current groups {U7, U6, U5, U4}, {U3, U2}, and {U1} are permanently fixed and respectively assigned to binary input codes B2, B1 and B0. For the RRBS method, randomization is realized through rotation, where left, right, and bi-directional rotations have similar performance, with the right-rotation demonstrated as an example for the sake of simplicity. R# represents the number (#) of right-rotation steps randomly generated in a range from 0 to 7. For an initial input of 6 with R4, where current groups {U7, U3, U2, U1}, {U6, U5}, and {U4} correspond to B2, B1, and B0, respectively, six current sources {U7, U6, U5, U3, U2, U1} are selected. For the second input of 3 with R5, where current groups {U7, U6, U2, U1}, {U5, U4}, and {U3} correspond to B2, B1, and B0, respectively, three current sources {U5, U4, U3}
5
are selected. For the third input of 7 with R1, all current sources are selected. For the following inputs, binary current groups are similarly formed and selected. For the 3-bit DAC example, Fig. 4 shows the detailed RRBS circuit schematic, which is simply composed of a 3-bit rotator and a 3-output pseudo-random number generator (PRNG) with a repeat-cycle of 215-1. The rotator is composed of 21 multiplexers, while the PRNG is used to generate R# and is composed of 15 D-type Flip-Flops and several logic gates. The PRNG is modified from a common linear feedback shift register (LFSR) with added detection logics to avoid the lock up state. As an example, for an input with R4 as in Fig. 3(b), the new binary groups are B2 as {W7, W3, W2, W1}, B1 as {W6, W5}, and B0 as {W4}, where W7, W6..., W1 are used to control current switches in Fig. 2. A behavioral model of a 6-bit 63 unit current source DAC is used to verify the effect of mismatch-insensitivity. To simplify the RRBS design, the DAC is segmented into the three most significant bits (MSBs) and three least significant bits (LSBs), and implemented by the aforementioned 3-bit architecture shown in Fig. 4. The current source mismatch profile with the joint error distribution (50% linear + 50% quadratic) adopted from [12] is used. The respective current source mismatch values have a maximum standard deviation of 10%. Full-scale sinusoidal signals are used and simulated results were obtained by averaging 32 Monte-Carlo iterations, each corresponding to 4096 samples. Fig. 5(a) shows the simulated output spectrum of the DAC with both the conventional binary and RRBS methods. It can be seen that RRBS effectively suppresses the mismatch-induced distortion tones. Fig. 5(b) shows the spurious-free dynamic range (SFDR) with the RRBS method, where the SFDR is larger than 70dB. The input frequencies range from (73/4096)·fs to (1993/4096)·fs with a (60/4096)·fs step, while current source mismatches range from 0.25% to 10% with a 0.25% step. Because of the RRBS method, mismatch errors are
6
randomized and distortion tones are greatly suppressed, which allows for the use of small-sized large-mismatched current sources. III. DYNAMIC PERFORMANCE OF RRBS DACS In current steering DACs, glitches occur when the current switches turn on / off at sampling instants. Increasing the input frequency in conventional binary-weighted DACs increases the amount of current switching, resulting in increased glitch energy. To analyze the switching property, the 6-bit DAC discussed at the end of Section II is used with full-swing inputs. Fig. 6 shows averaged switching activities with conventional binary, RRBS, and thermometer methods. Each input signal is composed of 4096 samples, and the switching activity is counted while each switch is toggled (on-to-off /off-to-on); after which, the sum for all input samples are averaged. As input signals approach the Nyquist bandwidth, and due to randomization, repeated selection of the same current sources in successive input samples occurs more frequently, thus switching activity is reduced by about 22% compared to the conventional binary-weighted method, resulting in better dynamic performance. Although RRBS has 17% more switching activity than the thermometer method at the Nyquist frequency, no other complicated algorithmic logics are required to further reduce the switching, except for when both very high resolution and very high speed are desired simultaneously. The distribution of switching activity for conventional binary-weighted and RRBS presented in Fig. 6 is plotted in detail in Fig. 7. Both Figs. 6 and 7(a) show that RRBS has more switching activity with lower input frequencies (fin ＜0.051fs). This does not present a problem for two reasons. First, the voltage transient step for low signal frequencies is fairly small; hence, the resulting distortion tones from glitch energy is small compared to that from device mismatch.
7
Second, the RRBS can split the large switching activities into smaller switching activities. As in Fig. 7(a), in addition to a lower probability of large switching activity, instances of switching activity over 50 are also reduced. As aforementioned, when the input signal approaches the Nyquist frequency, the probability of having large switching activity for RRBS is reduced significantly, as Fig. 7(b) demonstrates. Timing skews between different current sources, switch drivers, and output paths are strongly dependent on the physical layout [13][14]. A complex layout may adequately compensate for timing skew, but the routing overhead could also increase wiring complexity, layout area, and power consumption [14]. If the unit current sources can be selected randomly, the timing skew can be suppressed. Furthermore, the compact layout of the RRBS DAC will also alleviate the timing skew due to smaller mismatches of parasitic components and wiring mismatches. IV. ARCHITECTURE DESIGN AND AREA ANALYSIS In this section, different RRBS DAC architectures are analyzed with respect to area and switching activity. 10-bit RRBS DACs, with their current source circuit shown in Fig. 8(a), are used as examples. To reduce the number of transistors and complex wiring connections of DACs, segmentation is required, with examples including a 6-bit RRBS with 4-bit conventional binary type (6R+4C), an 8-bit RRBS with 2-bit conventional binary type (8R+2C), and a fully 10-bit RRBS (10R). To simplify the design of a RRBS DAC, each RRBS encoder can be partitioned into two or more identical lower-bit sub-RRBS encoders. Hence, with 2 sub-RRBS, the above structures become 3R+3R+4C, 4R+4R+2C, and 5R+5R, respectively. The 4R+4R+2C structure shown in Fig. 8(b) is chosen for circuit implementation; the reason for this choice, however, will be elaborated later in this section. The above structures can be further partitioned as 2R+2R+2R+4C,
8
2R+2R+2R+2R+2C, and 2R+2R+2R+2R+2R, respectively. Their respective allowable σ(I)/I calculated with the equation below [15] are 4.03%, 8.06%, and 11.4%.
(I )
1
0.5 3.1
(1) 2B where σ(I)/I is the standard deviation of current source mismatch, and B is the matching accuracy
I
bit, which is 4-bit, 2-bit, and 1-bit, respectively. With the calculated mismatches, simulation results show that the 3 structures all can achieve 70dB SFDR. Fig. 8(a) shows the current source circuit used for the DAC design. With a 250mV overdrive voltage, the gate area of MCS can be calculated by the following equation [15], 4 AVt2 A2 0.5 2 (V Vt ) W L GS 2 (I ) I
(2)
where Avt and Aβ are process matching parameters from the foundry. To boost output impedance, the cascoded transistor MCAS is designed with a 150 mV overdrive voltage and the same channel width as MCS. The switch pairs, MSW, are designed with minimum length and width. For equal driving ability, dummy switches are added in proportion to their respective weighting. Each switch driver is sized for a sharp transient edge with the desired cross-point voltage and drives 32 switches. The MCS area needed to achieve 2-bit matching accuracy is named AUCS, which is used as a unit for the following area calculations. According to the real circuit layout, the relative dimension is obtained as follows: 1 MUX has nearly the same dimensions as 4.5 AUCS, 1 switch pair has nearly the same dimensions as 1.25 AUCS, and one switch driver has nearly the same dimensions as 25 AUCS. The DAC area ASUM is composed of 4 major parts, i.e.
ASUM ACS ASW ASD AMUX
(3)
9
where ACS, ASW, ASD, and AMUX are the total area of current-source array, switch array, switch driver array, and MUXs in randomizers, respectively. The area calculations for 7 different RRBS segmentations are made in accordance with the relative dimensions described above, with their respective results listed in Table I. For example, in the 4R+4R+2C segmentation shown in Fig. 8(b), ACS is counted for 36 × 36 unit current-sources, including the surrounding dummies. ASW is counted for all switches, including dummies, where each most significant bit (MSB) switch group is driven by 2 switch drivers, each upper least significant bit (ULSB) is driven by 1 switch driver, and each lower least significant bit (LLSB) switch group is driven by 1 switch driver. AMUX is counted for two 4-bit rotators, and each rotator is implemented with 4 × 15 unit MUXs, AUMUX. The area analyses of other segmentations are expressed in terms of the unit current-source area AUCS used for 4R+4R+2C. For example, 0.8AUCS is the corresponding unit current-source area of the 5R+5R architecture. The respective area ASUM is similarly calculated. Fig. 9 shows the comparisons of implementation area and switching activity for the different segmentations. The switching activities are calculated for input frequencies near the Nyquist bandwidth. Though a higher partition level results in lower implementation area, it also increases switching activity. The switching activity of the 5-level partition 2R+2R+2R+2R+2R is about 10% higher than that of the 2-level 5R+5R. In addition, mismatch-insensitivity is degraded because of fewer unit current sources in a RRBS sub-encoder, and thus the ability to spread out distortion tones is reduced. The 5R+5R and 2R+2R+2R+2R+2R types need only 1-bit matching accuracy, which is not achievable in reality because its gate length is smaller than the minimum rule using the 0.18μm process. However, it is possible to design a smaller-area 2R+2R+2R+2R+2R DAC using smaller devices in advanced processes. The 4R+4R+2C type optimizes the trade-off between area and switching activity and thus is chosen for circuit implementation. It eliminates
10
binary-to-thermometer decoders to save 276AUCS, which corresponds to an estimated 7.5% area reduction. In addition, its estimated area is less than 15% of that of a conventional 10C DAC. V. CIRCUIT IMPLEMENTATION AND LAYOUT Fig. 8(b) shows the architecture of the implemented 4R+4R+2C DAC, where 4 MSBs and 4 ULSBs are RRBS, and 2 LLSBs are conventional binary-weighted. Its compact size is mainly achieved by eliminating binary-to-thermometer decoders, realizing simple DEM circuits and using small-area current sources. With an overdrive voltage of 250mV, the area of a unit current source, AUCS, is then decided with a channel width of 1.23μm and a channel length of 0.285μm, which corresponds to 3-bit matching accuracy rather than the 2-bit matching accuracy discussed in Section IV. This ensures that MCS can afford at least two contact placements at the drain/source of each unit current source to decrease series resistance. In addition, one extra bit for matching accuracy is preserved for design margins. Other circuits like cascoded transistors, switch pairs, and switch drivers are designed as presented in Section IV. With the RRBS technique, the matching accuracy of the current-source array was reduced from 10-bit to 3-bit, greatly reducing the active chip area and the resulting gradient mismatch error due to the shorter distances between transistors. To ensure that the MSB and ULSB portions have small mismatch, the layout of the whole MSB and ULSB current-source array is divided into 15 close regions, where each is composed of a MSB current-source group of 64 current units and a ULSB current-source group of 4 current units. The mismatch reduction is large and has been verified with Monte Carlo simulations. For the simulations, the element mismatch error profile with joint error distribution (50% linear + 50% quadratic) [12][16] is used, and the respective element mismatch values have 5.7% standard deviation for 3-bit matching accuracy. The simulated INL curves from
11
3000 Monte Carlo simulations are shown in Fig. 12 (a), with their distribution shown in Fig. 12(b). Without RRBS, the maximum INL is about 3.3 LSB. In consideration to edge effects, 4 dummy rows and columns were placed surrounding the current-source array. As shown in Table I, the array of 36 × 36 unit current source including dummies is only 80μm × 70μm, thus reducing the gradient errors. Therefore, special layout patterns like the double centroid adopted in [1][3][9] or the switching sequence optimization in [2] [11][12][16][17] are not necessary. The floor plan is arranged as in Fig. 10, where the CS array is composed of current sources and cascoded transistors. In addition, digital circuits include RRBS circuits and input registers. The CS array, SW array, SW driver array, and digital circuits occupy respective areas of 0.0056mm2, 0.0086mm2, 0.005mm2, and 0.0088mm2. The active area is 130μm × 263μm ≈ 0.034mm2. The CS array is even smaller than the digital circuits, which emphasizes the importance of eliminating binary-to-thermal decoders and reducing the RRBS circuit. As described in Section IV, the binary-to-thermometer decoders correspond to 7.5% of the active area, where the ratios between each block matched the estimates in Table I. Hence, the actual layout verifies the area analysis described in Section IV. The actual layout of digital blocks is slightly larger than that calculated by equation (3) because it contains other small-area circuits such as the pseudo random number generator (PRNG), the input register array, and some dummy buffers for timing synchronization. VI. MEASUREMENT RESULTS Fig. 11 shows the measurement setup with a chip-on-board configuration. The DAC’s output current is converted to a voltage through an off-chip 50Ω resistive differential load and coupled to a spectrum analyzer through a wideband transformer. The digital inputs and clock are produced by
12
Agilent ParBERT 81250. All measurements were performed by a full-scale load current of 10mA, which corresponds to a 250mV voltage swing at the output pins of the IC. The measured INL curves are shown in Fig. 13, with the measured INL curve with RRBS disabled shown in Fig. 13(a). 20 measured INL curves and their averaged INL curve are shown in Fig. 13(b), where the maximum INL is 3LSB. The averaged INL is small while RRBS is enabled. Three chips were measured and their results were found to be about the same. From Figs. 12 and 13, the simulated INL approximates the measured one, which validates the design. Figs. 14(a) and (b) show the respective power spectrum density (PSD) plots of the DAC with and without RRBS enabled for a 5MHz signal clocked at 500MS/s. With the RRBS enabled, the SFDR is increased to above 73dB. Fig. 15 shows the IMD3 spectrum with 245MHz and 247MHz signals clocked at 500MS/s, with the measured IMD3 being 62dB. Fig. 16 shows the SFDR and IMD3 over the entire Nyquist bandwidth clocked at 500MS/s. At low frequencies, the converter achieves 74dB SFDR, while it retains >61dB SFDR and >62dB IMD3 in the whole Nyquist bandwidth. Fig. 17 shows measurements with fin=0.01fs under sampling rates up to 800MS/s. The measured noise spectral density (NSD) plot is shown in Fig. 18. With RRBS enabled, the distortion tones due to mismatch are randomized then distributed into the noise floor. The noise floor is then raised by about 2dB. Two comparisons are made to further show RRBS performance. The first comparison with the conventional binary-weighted method is used to judge the effectiveness and compactness of the RRBS method. Figs. 19(a) and (b) show the respective SFDR and area comparisons with published binary-weighted current-steering 10~14-bit DACs. These DACs are implemented with the conventional binary-weighted architecture without binary-to-thermometer decoders. Our converter comprises an extremely small chip size, and achieves >61dB SFDR with a 250MHz signal
13
bandwidth, which is twice the bandwidth of the nearest comparable DAC [17], as demonstrated in Fig. 19. The second comparison, summarized in Table II, was made with state-of-the-art 10~12-bit DACs on resolution, bandwidth, power consumption, and SFDR. Based on these aspects, the three most applicable figures-of-merit (FOMs) proposed in [20] [22] and [23] are adopted. FOMs [4] [21], which respectively emphasize high power efficiency and high output swing, are not adopted. Detailed definitions of the adopted FOMs are given in Table III. The proposed DAC performs well with FOM1, and best with FOM2 and FOM3. This work achieves good SFDR with less than one-tenth the active area required by state-of-the-art 10-bit current-steering DACs. VII. CONCLUSIONS In this paper, random rotation-based binary-weighted selection (RRBS) is proposed. Its mismatch-insensitivity, dynamic performance and implementation area are analyzed. A 10-bit RRBS current-steering DAC is implemented in a 0.18μm CMOS process. Its implementation area is much smaller than that of other published state-of-the-art 10-bit current-steering DACs. Its compact size is mainly achieved by eliminating binary-to-thermometer decoders, realizing simple DEM circuits, and using small-area current sources. To the best of our knowledge, the proposed RRBS is the smallest-area implementation method currently available for high-speed currentsteering DACs. The proposed DAC also achieves very good SFDR compared with other state-of-the-art 10~12-bit DACs. Despite the RRBS DACs not having minimum switching activities as with the thermometer types, their switching activities are low enough for most DAC requirements. In addition, the presented RRBS DACs do not use complex algorithms and are easily realized. Hence, other than DACs aimed at achieving both very high resolution and very high speed simultaneously, the proposed RRBS is very suitable for most current-steering DAC designs.
14
ACKNOWLEDGMENT The authors would like to thank the National Chip Implementation Center (CIC), Taiwan, for their support of chip measurement. REFERENCES [1] A. van den Bosch, M. Borremans, M. Steyaert, and W. Sansen, “A 10-bit 1-GSample/s Nyquist current-steering CMOS D/A converter,” IEEE J. Solid-State Circuits, vol. 36, no. 3, pp. 315–324, Mar. 2001. [2] J. Bastos, A. M. Marques, M. S. J. Steyaert and W. Sansen, “A 12-Bit Intrinsic Accuracy High-Speed CMOS DAC,” IEEE J. Solid-State Circuits, vol. 33, no. 12, pp. 1959-1969, Dec. 1998. [3] P. Palmers and M. S. J. Steyaert, “A 10-Bit 1.6-GS/s 27-mW Current-Steering D/A Converter with 550-MHz 54-dB SFDR Bandwidth in 130-nm CMOS,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 57, no. 11, pp. 2870-2879, Nov. 2010. [4] C.-H. Lin, F. M. L. van der Goes, J. R. Westra, J. Mulder, Y. Lin, E. Arslan, E. Ayranci, X. Liu and K. Bult, “A 12 bit 2.9 GS/s DAC With IM3 > 60 dBc beyond 1GHz in 65 nm CMOS,” IEEE J. Solid-State Circuits, vol. 44, no. 12, pp. 3285-3293, Dec. 2009. [5] W.-H. Tseng, C.-W. Fan and J.-T. Wu, “A 12b 1.25GS/s DAC in 90nm CMOS with >70dB SFDR up to 500MHz,” in IEEE Solid-State Circuits Conf. Dig. Tech. Papers, 2011, pp. 192-193. [6] A. R. Bugeja and B.-S. Song, “A Self-Trimming 14-b 100-MS/s CMOS DAC,” IEEE J. Solid-State Circuits, vol. 35, no. 12, pp. 1841-1852, Dec. 2000. [7] M. P. Tiilikainen, “A 14-bit 1.8-V 20-mW 1-mm2 CMOS DAC,” IEEE J. Solid-State Circuits, vol. 36, no. 7, pp. 1144-1147, July. 2001. [8] D.-L. Shen, Y.-C. Lai and T.-C. Lee, “A 10-Bit Binary-Weighted DAC with Digital Background LMS Calibration,” in Proc. IEEE Asian Solid-State Circuits Conf. (ASSCC), Nov. 2007, pp. 352-355. [9] J.-H. Chi, S.-H. Chu and T.-H. Tsai, “A 1.8-V 12-Bit 250MS/s 25-mW Self-calibrated DAC,” in Proc. IEEE Eur. Solid-State Circuits Conf. (ESSCIRC), Sep. 2010, pp. 222-225.
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[10] D.-H. Lee and T.-H. Kuo, “Randomized Thermometer-Coding Digital-to-Analog Converter and Method Therefor,” U.S. Patent 7,679,539, Mar. 16, 2010. [11] D.-H. Lee, T.-H. Kuo and K.-L. Wen, “Low-cost 14-bit Current-steering DAC with a Randomized Thermometer-coding Method,” IEEE Trans. Circuits Syst. II, Exp. Briefs , vol. 56, no. 2, pp. 137–141, Feb. 2009. [12] D.-H. Lee, Y.-H. Lin and T.-H. Kuo, “Nyquist-Rate Current-Steering Digital-to-Analog Converters With Random Multiple Data-Weighted Averaging Technique and QN Rotated Walk Switching Scheme,” IEEE Trans. Circuits Syst. II, Exp. Briefs , vol. 53, no. 11, pp. 1264-1268, Nov. 2006. [13] T. Chen and G. G. E. Gielen, “The Analysis and Improvement of a Current-Steering DACs Dynamic SFDR-I: The Cell-Dependent Delay Difference,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 53, no. 1, pp. 3-15, Jan. 2006. [14] T. Chen and G. G. E. Gielen, “The Analysis and Improvement of a Current-Steering DACs Dynamic SFDR-II: The Output-Dependent Delay Difference,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 54, no. 2, pp. 268-279, Feb. 2007. [15] A. van den Bosch, M. S. J. Steyaert, and W. Sansen, “An Accurate Yield Model for CMOS Current-steering D/A Converters,” in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS), 2000, pp. 105–108. [16] Y. Cong and R. L. Geiger, “Switching Sequence Optimization for gradient Error Compensation in Thermometer-Decoded DAC Array,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 47, no. 7, pp. 585-595, July 2000. [17] J. Deveugele and M. S. J. Steyaert, “A 10-bit 250-MS/s Binary-Weighted Current-Steering DAC,” IEEE J. Solid-State Circuits, vol. 41, no. 2, pp. 320-329, Feb. 2006. [18] M. Borremans, A. V. den Bosch, M. Steyaert, and W. Sansen, “A low power, 10-bit CMOS D/A converter for high speed applications,” in Proc. IEEE Custom Integrated Circuits Conf. (CICC), May 2001, pp. 157–160. [19] Y. Ikeda, M. Frey and A. Matsuzawa, “A 14-bit 100-MS/s Digitally Calibrated Binary-Weighted Current-Steering CMOS DAC without Calibration ADC,” in Proc. IEEE Asian Solid-State Circuits Conf. (ASSCC), Nov. 2007, pp. 356-359.
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[20] A. Van den Bosch, M. S. J. Steyaert, and W. Sansen, “Solving static and dynamic performance limitations for high-speed D/A converters,” in Analog Circuit Design: Scalable Analog Circuit Design, High-Speed D/A Converters, RF Power Amplifiers. Norwell, MA: Kluwer, 2002, pp. 189–210. [21] D. Giotta, P. Pessl, M. Clara, W. Klatzer and R. Gaggl, “Low-power 14-bit Current Steering DAC for ADSL2+/CO Applications in 0.13μm CMOS,” in Proc IEEE Eur. Solid-State Circuits Conf. (ESSCIRC), Sep. 2004, pp. 163–166. [22] M. Clara, W. Klatzer, B. Seger, A. D. Giandomenico and L. Gori, “A 1.5V 200MS/s 13b 25mW DAC with randomized nested background calibration in 0.13μm CMOS,” in IEEE Solid-State Circuits Conf. Dig. Tech. Papers, 2007, pp. 250–251. [23] T. Chen, P. Geens, G. van der Plas, W. Dehaene and Georges Gielen, “A 14-bit 130-MHz CMOS Current-Steering DAC with Adjustable INL,” in Proc IEEE Eur. Solid-State Circuits Conf. (ESSCIRC), Sep. 2004, pp. 167–170.
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TABLES CAPTIONS TABLE I
AREA COMPARISONS FOR DIFFERENT RRBS SEGMENTATIONS.
TABLE II
COMPARISON WITH STATE-OF-THE-ART 10~12-BIT CURRENT-STEERING DACS.
TABLE III DETAILED DEFINITIONS OF DAC FOMS. FIGURES CAPTIONS Fig. 1 Diagram of (a) conventional binary-weighted coding, (b) conventional thermometer coding, (c) hybrid coding with current calibration, and (d) randomized DEM coding. Fig. 2 Diagram of the proposed DAC with random rotation-based binary- weighted selection (RRBS). Fig. 3 Operating principle of the (a) conventional binary-weighted method and (b) random rotation-based binary-weighted selection (RRBS) method where R# represents the number of right-rotation steps. Fig. 4 Detailed implementation circuits of a 3-bit RRBS example where MUX denotes multiplexer and DFF denotes D-type flip-flop. Fig. 5(a) Simulated output spectrum of a 6-bit DAC with a 10% standard deviation of current-source mismatch for the conventional binary-weighted and RRBS methods, respectively. (b) SFDR of the DAC employing RRBS with different input frequencies and mismatches. Fig. 6 Comparison of switching activities with different decoding methods in a 6-bit DAC. Input signals are with full-swing. Fig. 7 The distribution shows the occurrence of switching activity with (a) low input frequency and (b) high input frequency. Fig. 8 (a) The adopted current cell circuit and (b) the architecture of the implemented 4R+4R+2C RRBS DAC. Fig. 9 Area and switching activity of different segmentation types; each type is partitioned with its respective identical sub-RRBS encoders. Fig. 10 Photograph of the proposed DAC. Fig. 11 Measurement setup. Fig. 12(a) Simulated INL curves from 3000 Monte Carlo simulations and (b) their INL distribution. Fig. 13(a) Measured INL curve with RRBS disabled and (b) 20 measured INL curves with RRBS enabled (gray color) and their averaged INL curve (black color). Fig. 14 PSD plots (a) with and (b) without RRBS enabled for a 5MHz output signal clocked at 500MS/s. Fig. 15 Measured IMD3 spectrum with 245MHz and 247MHz signals clocked at 500MS/s. Fig. 16 SFDR and IMD3 vs. signal frequency clocked at 500MS/s.
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Fig. 17 Measured SFDR for fin=0.01fs with sampling rates up to 800MS/s. Fig. 18 Measured noise spectral density (NSD). Fig. 19 Comparison with published binary-weighted DACs on (a) SFDR vs. signal frequency and (b) active area.
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TABLE I AREA COMPARISONS FOR DIFFERENT RRBS SEGMENTATIONS. Segment
ACS
ASW
ASD
AMUX
ASUM
5C+5C 23×(36×36)AUCS (36×32]AUSW (36)AUSD 0 5R+5R 0.8×(36×36)AUCS [(32+32)×31)]AUSW [(1+1)×31]AUSD 2×5×31AUMUX 4R+4R+2C 1× (36×36)AUCS [(64+32)×15)+32×2]AUSW [(2+1)×15)+2]AUSD 2×4×15AUMUX 3R+3R+4C 1.7× (36×36)AUCS [(128+32)×7)+(32×4]]AUSW [(4+1)×7)+4]AUSD 2×3×7AUMUX 3R+3R+3R+1C 0.8×(36×36)AUCS [(128+32+32)×7+32]AUSW [(4+1+1)×7+1]AUSD 3×3×7AUMUX 2R+2R+2R+4C 1.7×(36×36)AUCS [(256+64+32)×3+(32×4)]AUSW [(8+2+1)×3+4]AUSD 3×2×3AUMUX 2R+2R+2R+2R+2R 0.8×(36×36)AUCS [(256+64+32+32+32)×3]AUSW [(8+2+1+1+1)×3]AUSD 5×2×3AUMUX 2R+2R+2R+2R+2C 1×(36×36)AUCS [(256+64+32+32)×3+(32×2)]AUSW [(8+2+1+1)×3+2]AUSD 4×2×3AUMUX Conditions: 1. AUCS(10-bit accuracy)=74.815μm2, AUCS(4-bit accuracy)=5.546μm2, AUCS(3-bit accuracy)=4.135μm2, AUCS(2-bit accuracy)#=3.268μm2, AUCS(1-bit accuracy)#*=2.577μm2 2. AUCS=2.15×1.52μm2, AUSW≈1.25AUCS, AUSD≈25AUCS, AUMUX≈4.5AUCS (including pitch-to-pitch space) 3. A 4-bit binary-to-thermometer decoder =40×15μm2, Two 4-bit decoders ≈367AUCS # Cannot contain two contacts on the width of drain/source region. * Violates the minimum gate length rule.
32148AUCS 6462AUCS 4891AUCS 4927AUCS 4116AUCS 4689AUCS 3342AUCS 3574AUCS
TABLE II COMPARISON WITH STATE-OF-THE ART 10~12-BIT CURRENT-STEERING DACS. [5] [3] [4] [17] ISSCC 2011 TCASI 2010 JSSC 2009 JSSC 2006 Resolution, N 10 12 10 12 10 Technology 0.18μm 90nm 0.13μm 65nm 0.18μm Sample rate (MS/s) 500 1250 1600 2900 250 Iload (mA) 10 16 10 50 10 Ptotal (mW) 24 128 23.6 188 22 BWN (MHz) 250 500 325 100 125 Area (mm2) 0.034 0.825 0.5 0.31 0.35 SFDRDC (dB) 74 75 74 74 74 SFDRNyquist (dB) 61 66 50 N/A 60 FOM1 1.07E+04 1.23E+04 2.18E+03 5.82E+03 1.60E+04 FOM2 7.50E+07 3.29E+07 N/A 4.02E+07 8.25E+07 FOM3 1.94E+04 2.46E+04 7.03E+03 1.66E+04 3.14E+05 ※ All FOMs are calculated with the performance under the power given in the respective papers. This Work
[1] JSSC 2001 10 0.35μm 1000 20 110 500 0.35 74 61 4.65E+03 3.52E+07 1.33E+04
TABLE III DETAILED DEFINITIONS OF DAC FOMS. Term Formula Origin Definition
FOM1
2 N BW N Ptotal [20] BWN: Signal BW retains 6×N dB SFDR in MHz.
FOM2 2
SFDRDC 1.76 6.02
FOM3
SFDRNyq u ist 1.76
6.02 2 f clk 1 2 Ptotal I load Rload 2
[22] SFDRDC/ SFDRNyquist: Best/ Worst measured SFDR in whole Nyquist bandwidth.
2 N BW N Ptotal Area
[23] Area: Active area in mm2.
Wei-Te Lin and Tai-Haur Kuo
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U7
U6
U5
U4
U3
U2
U1
U7
U6
U5
U4
U3
U2
U1
Iout W7
W6
W5
W4
W3
W2
Iout
W1
W7
W5
W4
W3
W2
W1
Binary-to-thermometer
Wiring connection
B2
BN-1
W6
B1
B0
B2
BN-1
B1
(a)
B0
(b)
Calibration circuit U7
U6
U5
U4
U3
U2
U1
Iout U7
U6
U5
U4
U3
U2
U1
W7
W6
Iout W7
W6
W5
W4
W3
W2
B2
B1
W4
W3
W2
W1
Randomizer
W1
Binary-to-thermometer
Binary-weighted or binary-to-thermometer
BN-1
W5
B0
BN-1
B2
B1
B0
(d) (c) Fig. 1 Diagram of (a) conventional binary-weighted coding, (b) conventional thermometer coding, (c) hybrid coding with current calibration, and (d) randomized DEM coding.
U7
U6
U5
U4
U3
U2
U1
Iout W7
W6
W5
W4
W3
W2
W1
Simple randomizer
Wiring connection
BN-1
B2 B1 B0 Fig. 2 Diagram of the proposed DAC with random rotation-based binary-weighted selection (RRBS).
Wei-Te Lin and Tai-Haur Kuo
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Conventional Binary-weighted Input U7 U6 U5 U4 U3 U2 U1
RRBS Input (R#) U7 U6 U5 U4 U3 U2 U1
110
B2 B2 B2 B2 B1 B1 B0
110(R4)
B2 B1 B1 B0 B2 B2 B2
011
B2 B2 B2 B2 B1 B1 B0
011(R5)
B2 B2 B1 B1 B0 B2 B2
111
B2 B2 B2 B2 B1 B1 B0
111(R1)
B0 B2 B2 B2 B2 B1 B1
100
B2 B2 B2 B2 B1 B1 B0
100(R2)
B1 B0 B2 B2 B2 B2 B1
101
B2 B2 B2 B2 B1 B1 B0
101(R0)
B2 B2 B2 B2 B1 B1 B0
(a) (b) Fig. 3 Operating principle of the (a) conventional binary-weighted method and (b) random rotation-based binary-weighted selection (RRBS) method where R# represents the number of right-rotation steps.
RotatorW7
W6
W5
W4
W3
W2
W1
PRNG CK
CK
MUX
MUX
MUX
MUX
MUX
MUX
MUX
1-step rotation
DFF
Q0
DFF CK
CK
MUX
MUX
MUX
MUX
MUX
MUX
MUX
2-step rotation
MUX
MUX
MUX
MUX
MUX
MUX
MUX
4-step rotation
DFF
Q5
DFF
Q10
DFF
Q2
DFF
Q7
DFF
DFF
Q12
DFF
DFF
Q4
CK Q8
DFF
Q9
CK
CK
CK Q11
DFF
Q3
CK
CK Q6
CK
CK
DFF
DFF
CK
CK
CK Q1
Q13
DFF
Q14
Q0
B2
B1
B0
Q14
Fig. 4 Detailed implementation circuits of a 3-bit RRBS example where MUX denotes multiplexer and DFF denotes D-type flip-flop.
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(a) (b) Fig. 5(a) Simulated output spectrum of a 6-bit DAC with a 10% standard deviation of current-source mismatch for the conventional binary-weighted and RRBS methods, respectively. (b) SFDR of the DAC employing RRBS with different input frequencies and mismatches.
Averaged Switching / Sample
60
Conventional Binary RRBS ․․ Thermometer
50
40 30 20
10 0 0.0
0.1
0.2
0.3
0.4
0.5
Normalized Frequency (Fin/Fs)
Fig. 6 Comparison of switching activities with different decoding methods in a 6-bit DAC. Input signals are with full-swing.
Wei-Te Lin and Tai-Haur Kuo
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(b)
(a)
Fig. 7 The distribution shows the occurrence of switching activity with (a) low input frequency and (b) high input frequency.
VDD MCS
… MSB
CS Array
ULSB CS Array
…
…
MSB
ULSB SW Array
…
…
MSB … SW_DR Array
ULSB SW_DR Array
MCAS
MSW
D
D
…SW Array
VDD
clk inp
clk D
D
GND
inn
LLSB CS Array
LLSB SW Array
…
…
4-bit MSB RRBS Encoder
4-bit ULSB RRBS Encoder
B9
B8
B7
B6
B5 B4
B3
B2
outp outn
LLSB SW_DR Array
B1 B0
(a) (b) Fig. 8(a) The current cell circuit and (b) the architecture of the implemented 4R+4R+2C RRBS DAC.
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Fig. 9 Area and switching activity of different segmentation types; each type is partitioned with its respective identical sub-RRBS encoders.
Bias
CS Array
263μm
130μm
SW Array
SW Driver Array
Digital Circuits including RRBS
Fig. 10 Photograph of the proposed DAC.
50Ω Digital Inputs
DUT DAC
100Ω
T1-1T
To Spectrum Analyzer
50Ω Fig. 11 Measurement setup.
Wei-Te Lin and Tai-Haur Kuo
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(a)
(b)
Fig. 12(a) Simulated INL curves from 3000 Monte Carlo simulations and (b) their INL distribution.
(b) (a) Fig. 13(a) Measured INL curve with RRBS disabled and (b) 20 measured INL curves with RRBS enabled (gray color) and their averaged INL curve (black color).
RRBS Enabled
(a)
RRBS Disabled
(b)
Fig. 14 PSD plots (a) with and (b) without RRBS enabled for a 5MHz output signal clocked at 500MS/s.
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Fig. 15 Measured IMD3 spectrum with 245MHz and 247MHz signals clocked at 500MS/s.
SFDR (dB)
75 70 65 60
IMD3 SFDR
55 1
10
100
Signal Frequency, Fin (MHz)
Fig. 16 SFDR and IMD3 vs. signal frequency clocked at 500MS/s.
75
SFDR (dB)
70 65 60 55 Fin=0.01Fs 50 100
200
300
400
500
600
700
800
Sampling Frequency, Fs (MHz)
Fig. 17 Measured SFDR for fin=0.01fs with sampling rates up to 800MS/s.
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-130
NSD (dBc/Hz)
RRBS Enabled RRBS Disabled -135
-140
-145 0
50
100
150
200
250
Input Frequency, Fin (MHz)
Fig. 18 Measured noise spectral density (NSD).
85
80
Active Area (mm2)
1
SFDR (dB)
75 70 65 60
55 50 45 40 0.01
14 bit 0.18µm
This work, 10bit@500MS/s JSSC2006, 10bit@250MS/s CICC2001, 10bit@30MS/s ASSCC2007, 14bit@100MS/s JSSC2001, 14bit@100MS/s ASSCC2007, 10bit@1GS/s
0.1
1
14 bit 0.18µm
0.75
0.5
10 bit 0.18µm 10 bit 0.35µm
0.25
10 bit 0.18µm
10 bit 0.18µm 10
Signal Frequency, Fin (MHz)
100
0
This Work
JSSC 2006
CICC ASSCC JSSC ASSCC 2001 2007 2001 2007
(b) (a) Fig. 19 Comparison with published binary-weighted DACs on (a) SFDR vs. signal frequency and (b) active area.
Wei-Te Lin and Tai-Haur Kuo
