A Configurable Asynchronous Pseudorandom Bit ... - Semantic Scholar
A Configurable Asynchronous Pseudorandom Bit Sequence Generator Alex Chow, Bill Coates, David Hopkins VLSI Research Group Sun Microsystems Laboratories 1
Outline • Pseudorandom bit sequences (PRBSs) • Traditional PRBS generators • An asynchronous implementation > Design > Properties
• Extension to other types of circuits
A. Chow - Mar 14 2007
ASYNC 2007
2
Properties & Applications of PRBSs • A statistically “random” bit sequence > Behaves like noise > Carries an equal number of 1's and 0's > Has near zero correlation with other PRBSs
• Useful for > Testing I/O channels > Cryptography > Spread-spectrum communication systems
A. Chow - Mar 14 2007
ASYNC 2007
3
Generating a PRBS Using a Linear Feedback Shift Register (LFSR)
• Next input bit is a linear function of the current state
Feedback Logic t1
t2
t3
tN OUT
CLK A. Chow - Mar 14 2007
ASYNC 2007
4
Generating a PRBS Using a Linear Feedback Shift Register (LFSR)
• Next input bit is a linear function of the current state • Feedback logic is a sum (XOR) of a subset of bits in the register
t1
t2
t3
tN OUT
CLK A. Chow - Mar 14 2007
ASYNC 2007
5
Feedback Tap Sequence • Not every tap sequence generates a PRBS • A PRBS must be a maximal-length sequence > An N-stage LFSR produces a PRBS of length 2N – 1 > The PRBS contains every N-bit pattern (except all 0's)
• Maximal tap sequence found using finite-field math
A. Chow - Mar 14 2007
ASYNC 2007
6
Feedback Tap Sequence Notation
• We list the positions of all tapped bits • Example: 5-stage LFSR with taps at positions 3,5 > Notation: N = 5, Taps = [5,3] > Produces a PRBS with length 25 – 1 = 31
1
2
3
4
5
OUT
CLK A. Chow - Mar 14 2007
ASYNC 2007
7
LFSR Logical Constraints • Properties of the PRBS strictly defined by LFSR topology, i.e. > Number of LFSR stages > Tap sequence (location and number of taps)
• Each LFSR circuit can produce only one PRBS
A. Chow - Mar 14 2007
ASYNC 2007
8
An Asynchronous PRBS Generator • Started as a “Friday project” • Replace shift register with asynchronous FIFO stages • We present a GasP implementation
A. Chow - Mar 14 2007
ASYNC 2007
9
Two-Tap PRBS Generator The Circuit L Feedback Logic
Tap 1 L
L
L
Tap 2 L
L
L
DATA OUT
CTL OUT
Data path Control path A. Chow - Mar 14 2007
ASYNC 2007
10
Two-Tap PRBS Generator GasP Control Elements Control merge
L
Feedback Logic
Tap 1 L
L
L
Tap 2 L
L
L
DATA OUT
CTL OUT
Control branch A. Chow - Mar 14 2007
ASYNC 2007
Data path Control path 11
Enforcing Proper Bit Sequence • LFSR uses global clock > Every stage contains valid data > Data moves in lock-step > Bit sequencing and synchronization implicitly enforced
• Async implementation requires explicit control > Not every stage contains valid data > Data bits may propagate autonomously > Must explicitly synchronize pairs of control tokens to
guarantee correct data sequencing
A. Chow - Mar 14 2007
ASYNC 2007
12
Two-Tap PRBS Generator Example
• Emulate 5-stage LFSR with taps = [5,3] X
X L
I
X L
L
L
L
X L
X L
L
L
DATA OUT
CTL OUT
STOP
Data bit Control token A. Chow - Mar 14 2007
ASYNC 2007
13
Two-Tap PRBS Generator Example
• Emulate 5-stage LFSR with taps = [5,3] X L
I
X L
L
L
X L
L
X L
L
L
DATA OUT
CTL OUT
Data bit Control token A. Chow - Mar 14 2007
ASYNC 2007
14
Two-Tap PRBS Generator Example
• Emulate 5-stage LFSR with taps = [5,3] X L
I
X L
L
X L
L
X L
L
X L
L
DATA OUT
CTL OUT
Data bit Control token A. Chow - Mar 14 2007
ASYNC 2007
15
Two-Tap PRBS Generator Example
• Emulate 5-stage LFSR with taps = [5,3] X
X L
Physical taps [8,4]
I
1L
2L
3L
4L
X
5L
X
6L
X
7L
8L
DATA OUT
CTL OUT
STOP
Data bit Control token A. Chow - Mar 14 2007
ASYNC 2007
16
Two-Tap PRBS Generator Example
• Emulate 5-stage LFSR with taps = [5,3] X
X L
Logical taps [5,3]
I
X L
1
L
2
L
3
L
X L
X L
L
4
L
5
DATA OUT
CTL OUT
STOP
Data bit Control token A. Chow - Mar 14 2007
ASYNC 2007
17
Physical & Logical Independence • LFSR: > Physical tap sequence = logical tap sequence
• Asynchronous implementation: > Logical tap sequence depends only on token distribution > Physical circuit structure need only enable logical tap
sequence, not match it
A. Chow - Mar 14 2007
ASYNC 2007
18
Configurability • Async control decouples logical bit distribution from physical circuit structure • One circuit can produce many different PRBSs
A. Chow - Mar 14 2007
ASYNC 2007
19
Generating Different PRBSs Example
• Construct a circuit to generate all two-tap maximallength patterns of order N ≤ 7 Order N
Logical Taps
# Tokens Seg 1
# Tokens Seg 2
3
[3,2]
2
1
4
[4,3]
3
1
5
[5,3]
3
2
6
[6,5]
5
1
7
[7,4]
4
3
7
[7,6]
6
1
A. Chow - Mar 14 2007
ASYNC 2007
20
Generating All Patterns for N ≤ 7 • N=3 • Taps = [3,2] X
X L
I
X L
X
X L
L
X L
L
L
X L
X L
L
DATA OUT
CTL OUT
STOP
A. Chow - Mar 14 2007
ASYNC 2007
21
Generating All Patterns for N ≤ 7 • N=4 • Taps = [4,3] X
X L
I
X L
X
X L
L
L
L
L
X L
X L
L
DATA OUT
CTL OUT
STOP
A. Chow - Mar 14 2007
ASYNC 2007
22
Generating All Patterns for N ≤ 7 • N=5 • Taps = [5,3] X
X L
I
X L
X
X L
L
L
L
L
X L
L
L
DATA OUT
CTL OUT
STOP
A. Chow - Mar 14 2007
ASYNC 2007
23
Generating All Patterns for N ≤ 7 • N=6 • Taps = [6,5] X
X L
I
X L
L
L
L
L
L
X L
X L
L
DATA OUT
CTL OUT
STOP
A. Chow - Mar 14 2007
ASYNC 2007
24
Generating All Patterns for N ≤ 7 • N = 7A • Taps = [7,4] X
X L
I
X
X L
L
L
L
L
L
L
L
L
DATA OUT
CTL OUT
STOP
A. Chow - Mar 14 2007
ASYNC 2007
25
Generating All Patterns for N ≤ 7 • N = 7B • Taps = [7,6] X
X L
I
X L
L
L
L
L
L
X L
X L
L
DATA OUT
CTL OUT
STOP
A. Chow - Mar 14 2007
ASYNC 2007
26
Throughput and I/O • Throughput varies for different patterns > Because token occupancy is different for each pattern
• May use the generator in synchronous systems > Take the output through async-to-clocked interfaces > Clock rate must be lower than minimum async throughput
A. Chow - Mar 14 2007
ASYNC 2007
27
Summary • Async design decouples number and distribution of logical bits from physical shift register structure • Exploit this orthogonality to let one FIFO circuit adopt multiple logical configurations • PRBS generator serves as an illustrative example > Can apply this idea to other circuits > Other examples: CRC generators, encoders, filters
A. Chow - Mar 14 2007
ASYNC 2007
28
Extension • Example: Cyclic Redundancy Checksum (CRC) generator
IN
1
2
3
4
5
OUT
CLK
A. Chow - Mar 14 2007
ASYNC 2007
29
Questions Alex Chow [email protected]
30
Outline • Pseudorandom bit sequences (PRBSs) • Traditional PRBS generators • An asynchronous implementation > Design > Properties
• Extension to other types of circuits
A. Chow - Mar 14 2007
ASYNC 2007
2
Properties & Applications of PRBSs • A statistically “random” bit sequence > Behaves like noise > Carries an equal number of 1's and 0's > Has near zero correlation with other PRBSs
• Useful for > Testing I/O channels > Cryptography > Spread-spectrum communication systems
A. Chow - Mar 14 2007
ASYNC 2007
3
Generating a PRBS Using a Linear Feedback Shift Register (LFSR)
• Next input bit is a linear function of the current state
Feedback Logic t1
t2
t3
tN OUT
CLK A. Chow - Mar 14 2007
ASYNC 2007
4
Generating a PRBS Using a Linear Feedback Shift Register (LFSR)
• Next input bit is a linear function of the current state • Feedback logic is a sum (XOR) of a subset of bits in the register
t1
t2
t3
tN OUT
CLK A. Chow - Mar 14 2007
ASYNC 2007
5
Feedback Tap Sequence • Not every tap sequence generates a PRBS • A PRBS must be a maximal-length sequence > An N-stage LFSR produces a PRBS of length 2N – 1 > The PRBS contains every N-bit pattern (except all 0's)
• Maximal tap sequence found using finite-field math
A. Chow - Mar 14 2007
ASYNC 2007
6
Feedback Tap Sequence Notation
• We list the positions of all tapped bits • Example: 5-stage LFSR with taps at positions 3,5 > Notation: N = 5, Taps = [5,3] > Produces a PRBS with length 25 – 1 = 31
1
2
3
4
5
OUT
CLK A. Chow - Mar 14 2007
ASYNC 2007
7
LFSR Logical Constraints • Properties of the PRBS strictly defined by LFSR topology, i.e. > Number of LFSR stages > Tap sequence (location and number of taps)
• Each LFSR circuit can produce only one PRBS
A. Chow - Mar 14 2007
ASYNC 2007
8
An Asynchronous PRBS Generator • Started as a “Friday project” • Replace shift register with asynchronous FIFO stages • We present a GasP implementation
A. Chow - Mar 14 2007
ASYNC 2007
9
Two-Tap PRBS Generator The Circuit L Feedback Logic
Tap 1 L
L
L
Tap 2 L
L
L
DATA OUT
CTL OUT
Data path Control path A. Chow - Mar 14 2007
ASYNC 2007
10
Two-Tap PRBS Generator GasP Control Elements Control merge
L
Feedback Logic
Tap 1 L
L
L
Tap 2 L
L
L
DATA OUT
CTL OUT
Control branch A. Chow - Mar 14 2007
ASYNC 2007
Data path Control path 11
Enforcing Proper Bit Sequence • LFSR uses global clock > Every stage contains valid data > Data moves in lock-step > Bit sequencing and synchronization implicitly enforced
• Async implementation requires explicit control > Not every stage contains valid data > Data bits may propagate autonomously > Must explicitly synchronize pairs of control tokens to
guarantee correct data sequencing
A. Chow - Mar 14 2007
ASYNC 2007
12
Two-Tap PRBS Generator Example
• Emulate 5-stage LFSR with taps = [5,3] X
X L
I
X L
L
L
L
X L
X L
L
L
DATA OUT
CTL OUT
STOP
Data bit Control token A. Chow - Mar 14 2007
ASYNC 2007
13
Two-Tap PRBS Generator Example
• Emulate 5-stage LFSR with taps = [5,3] X L
I
X L
L
L
X L
L
X L
L
L
DATA OUT
CTL OUT
Data bit Control token A. Chow - Mar 14 2007
ASYNC 2007
14
Two-Tap PRBS Generator Example
• Emulate 5-stage LFSR with taps = [5,3] X L
I
X L
L
X L
L
X L
L
X L
L
DATA OUT
CTL OUT
Data bit Control token A. Chow - Mar 14 2007
ASYNC 2007
15
Two-Tap PRBS Generator Example
• Emulate 5-stage LFSR with taps = [5,3] X
X L
Physical taps [8,4]
I
1L
2L
3L
4L
X
5L
X
6L
X
7L
8L
DATA OUT
CTL OUT
STOP
Data bit Control token A. Chow - Mar 14 2007
ASYNC 2007
16
Two-Tap PRBS Generator Example
• Emulate 5-stage LFSR with taps = [5,3] X
X L
Logical taps [5,3]
I
X L
1
L
2
L
3
L
X L
X L
L
4
L
5
DATA OUT
CTL OUT
STOP
Data bit Control token A. Chow - Mar 14 2007
ASYNC 2007
17
Physical & Logical Independence • LFSR: > Physical tap sequence = logical tap sequence
• Asynchronous implementation: > Logical tap sequence depends only on token distribution > Physical circuit structure need only enable logical tap
sequence, not match it
A. Chow - Mar 14 2007
ASYNC 2007
18
Configurability • Async control decouples logical bit distribution from physical circuit structure • One circuit can produce many different PRBSs
A. Chow - Mar 14 2007
ASYNC 2007
19
Generating Different PRBSs Example
• Construct a circuit to generate all two-tap maximallength patterns of order N ≤ 7 Order N
Logical Taps
# Tokens Seg 1
# Tokens Seg 2
3
[3,2]
2
1
4
[4,3]
3
1
5
[5,3]
3
2
6
[6,5]
5
1
7
[7,4]
4
3
7
[7,6]
6
1
A. Chow - Mar 14 2007
ASYNC 2007
20
Generating All Patterns for N ≤ 7 • N=3 • Taps = [3,2] X
X L
I
X L
X
X L
L
X L
L
L
X L
X L
L
DATA OUT
CTL OUT
STOP
A. Chow - Mar 14 2007
ASYNC 2007
21
Generating All Patterns for N ≤ 7 • N=4 • Taps = [4,3] X
X L
I
X L
X
X L
L
L
L
L
X L
X L
L
DATA OUT
CTL OUT
STOP
A. Chow - Mar 14 2007
ASYNC 2007
22
Generating All Patterns for N ≤ 7 • N=5 • Taps = [5,3] X
X L
I
X L
X
X L
L
L
L
L
X L
L
L
DATA OUT
CTL OUT
STOP
A. Chow - Mar 14 2007
ASYNC 2007
23
Generating All Patterns for N ≤ 7 • N=6 • Taps = [6,5] X
X L
I
X L
L
L
L
L
L
X L
X L
L
DATA OUT
CTL OUT
STOP
A. Chow - Mar 14 2007
ASYNC 2007
24
Generating All Patterns for N ≤ 7 • N = 7A • Taps = [7,4] X
X L
I
X
X L
L
L
L
L
L
L
L
L
DATA OUT
CTL OUT
STOP
A. Chow - Mar 14 2007
ASYNC 2007
25
Generating All Patterns for N ≤ 7 • N = 7B • Taps = [7,6] X
X L
I
X L
L
L
L
L
L
X L
X L
L
DATA OUT
CTL OUT
STOP
A. Chow - Mar 14 2007
ASYNC 2007
26
Throughput and I/O • Throughput varies for different patterns > Because token occupancy is different for each pattern
• May use the generator in synchronous systems > Take the output through async-to-clocked interfaces > Clock rate must be lower than minimum async throughput
A. Chow - Mar 14 2007
ASYNC 2007
27
Summary • Async design decouples number and distribution of logical bits from physical shift register structure • Exploit this orthogonality to let one FIFO circuit adopt multiple logical configurations • PRBS generator serves as an illustrative example > Can apply this idea to other circuits > Other examples: CRC generators, encoders, filters
A. Chow - Mar 14 2007
ASYNC 2007
28
Extension • Example: Cyclic Redundancy Checksum (CRC) generator
IN
1
2
3
4
5
OUT
CLK
A. Chow - Mar 14 2007
ASYNC 2007
29
Questions Alex Chow [email protected]
30
