A Design Strategy for VHF Filters with Digital ... - Semantic Scholar
A Design Strategy for VHF Filters with Digital Programmability A. Otín, S. Celma and C. Aldea Group of Electronics Design, GDE-CDAM University of Zaragoza Zaragoza, Spain e-mail: {aranotin, scelma, caldea}@unizar.es Abstract—In this paper we report 2nd and 3rd-order Gm-C filters based on fully-balanced pseudo-differential continuoustime transconductors for applications in low-voltage systems over the VHF range. By using a 0.35 μm standard CMOS process, low-pass filter approximations have been implemented with a cut-off frequency programmability over the 40-200 MHz range, which confirm the feasibility of the proposed strategy in applications such as data storage systems and IF strips. The filters consume less than 4.8 mW per pole at 45 MHz from a 2V supply. The measured dynamic range was better than 53 dB at THD of 1% for all filters. The maximum active chip area is 0.025 mm2 per pole.
I.
INTRODUCTION
The hard disk drive (HDD) has become in an important and extremely useful element in every information processing system. The trends in HDDs involve high user densities and data rates supported by current storage systems [1]. This demands complex read channel ICs, in particular, continuous-time filters with variable bandwidths, over a wide range (typically 1:5), to accommodate the different data rates required by constant density recording and servo processing [2]. Among the different continuous-time integrated filter strategies, the Gm-C approach [3, 4] is the preferred option, thanks to its acceptable performance over the VHF/UHF range. To achieve a digitally programmable continuous-time filter, which is compatible with low-cost digital CMOS processes and suitable with high frequency requirements, specific design techniques of building block based filters must be explored [5]. There are many well-known varying ways to implement a transconductor in CMOS technology. Current-mode pseudo-differential transconductors exhibit low-voltage, moderated linearity and very high frequency operation capability with high power efficiency [6, 7]. This approach has been adopted in a new design of transconductor cell with digital programmability [8, 9], serving as an excellent choice to implement high frequency filters with a trade-off between dynamic range and tuning capability. In this paper, different digitally programmable and continuously tunable 0.35µm CMOS technology filters with
a 2 V power supply are proposed: one 2nd-order biquad and two 3rd-order low-pass LC ladder filters (Butterworth and elliptical approximations). The programmability exhibited by the filters is achieved owing to the design of a generic programmable transconductor, which could be used in other higher order filter topologies. The proposed filters are made up of a parallel connection of unit folded-cascode cells specifically designed for wide programmability range. The tunability exhibited by the filters covers the 40-200 MHz range with a total harmonic distortion (THD) of less than 1% for 120μA differential signal (60% Ibias) throughout the whole operating frequency range in all filters. II.
TECHNOLOGICAL AND ARCHITECTURAL ISSUES
An optimal solution for digitally programmable analog filters in VHF/UHF range is to take advantage of currentmode pseudo-differential topologies and to provide them with digital programmability. Several high-performance continuous-time filters have been implemented to demonstrate the behavior pattern of the proposed transconductor cell. The realizations are based on two of the most popular type of structures, ladder filters and biquadratic based filters. The frequency of these filters ranges over the VHF band. The programmability of the filter is achieved by varying a digital word. On the other hand, a fine tuning of the proposed structure can be achieved as the transconductance value can be controlled by varying the bias current for a fixed digital word. Hence, discrete steps are swept maintaining the same dynamic range by varying the bias current, and a control over the DC-gain can be achieved by modifying the ratio between the bias currents in the transconductor cell. The quality factor (e.g. the pass-band ripple) of the filters is controlled by CMOS resistors, which are also employed to control the phase error over the whole frequency range [9]. A. Transconductor Cell The folded cascode circuit exhibits a substantial improvement in biasing flexibility, because of the increased
This work has been partially supported by DGA-FSE (PIP/187-2005) and MEC-FEDER (TIC2005-00285/MIC)
0-7803-9390-2/06/$20.00 ©2006 IEEE
1059
ISCAS 2006
drain-voltage of the transistors, at the cost of additional current sources and bias voltages. Another important benefit by using these stages is that avoiding the biasing constraints associated to the other cascode configurations, i.e., the gatesource voltages need not be kept small, results in smaller and simpler devices for a given bias current level, and larger unity-gain frequencies. This is the option we are going to use in this work and the fully-balanced pseudo-differential current-mode transconductance cell implemented by using the folded stage is shown in Fig. 1. In this approach, the use of a cascode output is not necessary because the DC gain is increased by providing positive feedback compensation for the signal current and boosting the input resistance of the integrator [10]. Theoretically, adjusting the equivalent negative resistance, the DC gain could be infinity but in practice, mismatching limits the dc gain. The use of pseudo-differential topologies requires a careful and efficient control over the common-mode behaviour of the circuit. It is worth noting that this structure not only stabilises the common-mode voltage, but also rejects the input common-mode signals by means of partial positive feedback [6, 7]. In order to reach the maximum frequency of operation with moderated power consumption, the integration capacitance is CI is constituted by the parasitic capacitors and an additional one implemented by using a double-poly capacitor. Nevertheless, MOS-C or metal-metal capacitors could be used depending on the CMOS process features. In this way, to control the operation frequency and reduce the phase error, a shunt connection is made at the input between a resistance (implemented with a transistor working in the linear region) and the integration capacitance CI. We then obtain a compensation scheme for the transconductor based on a RC circuit at the input. By means of a parallel connection of equal transconductors switched by a digital word, we guarantee that the dynamic range for each gm value and the total external node capacitances will be kept almost constant. The feasibility of the programmable array of transconductors has been proven obtaining frequency scaling as expected [8, 9]. I-O
I+i
gm
gm
gm
In consequence, we can conclude that by varying the digital word from 1 to 5, the expected linear dependence of the unity-gain frequency is obtained and the phase error is effectively reduced over all the programming range (phase error less than 3º). By driving the gates of cascode transistors with modulated digital voltages, we can obtain the desired transconductance with no switches in the signal path and power consumption proportional to the transconductance necessary in each frequency sub-range. HIGH PERFORMANCE FILTER IMPLEMENTATION
III.
The filter can be designed using either biquads or ladder filters. The dynamic range of the low-pass ladder filter is superior to the dynamic range of the biquadratic based lowpass filters. Furthermore, the ladder filter is less sensitive to the tolerances of the components, mainly in the filter passband. However, the ladder filter is not as versatile as the biquad and its tuning is more complicated. A. Active LC-Ladder Prototypes First, two different fully-balanced pseudo-differential low-pass 3rd-order filters, with Butterworth and elliptic approximations, were chosen to be tested. Both filters are derived from their doubly terminated LC ladder prototype in the current mode. The Gm-C implementation can be accomplished by substituting the terminating resistors in the prototype by diode-connected transconductors and the inductor by a gyrator. According to this idea, Fig. 2 shows the block diagram of the elliptic filter with resistive termination using a gyratorcapacitor combination. The Butterworth filter is described with the same block diagram except for the floating capacitor C2 and its respective compensation resistance which do not appear. The LC filter shows an inherent 6 dB loss and has been compensated by using a 2gm-stage in both filters. B. Cascade Approach Biquadratic second order sections are cascaded to obtain higher order structures. The filters obtained by using this approach show more modularity than LC-ladder counterparts. Another important benefit is the independent control over each section which leads to a more versatile implementation. The main disadvantage of this approach, however, is the high sensitivity to the tolerances of the components. Fig. 3 shows the block diagram of the biquad implementation.
IBIAS
R
C2
R
_
R _
MPi C
I
CI
+
VOUT Mi
R
I-i
Iin
VFN
gm
gm
2C1
_
+ gm
gm
IO
+ gm
gm _
_ +
2CL
_
2C3
gm _
R
+
Figure 1. Fully balanced pseudo-differential current-mode transconductance cell.
_
_ + 2C1
MNi
gm
R
R
VB
Vin
_ +
2C3
+
_
+
_
gm
2xgm
_ +
_ +
IOut
R C2
R
Figure 2. Active implementation: Butterworth (C2=0) and Elliptic (C2≠0).
1060
R _
+
Iin
2C1
gm _
_
+
R
gm
gm +
2C1
_
_
+
+
_ 2C2
_
+ gm
+
_
IOut +
R
Figure 3. Biquad active implementation.
IV.
RESULTS (a)
Three different Gm-C low-pass filters have been designed in a pure digital 0.35 μm double-well CMOS technology with a 2 V power supply. The maximum active area per pole is 0.025 mm2. A microphotograph of the chips is shown in Fig. 4. The filter frequency response obtained by the postlayout simulations for the prototypes is reported in Fig. 5. According to the nominal transconductance obtained with the proposed programmable cell, the filter capacitances were selected in order to obtain a nominal cut-off frequency of 42 MHz. To achieve a high cut-off frequency, the filter operates also on parasitic capacitances. This is possible since the parasitic capacitances are all at nodes where a capacitance is desired in the filter. The need for a high impedance node obtained with the folded-cascode transconductor disappears depending on how the cell is connected to the rest of the circuit.
(a)
(b) Figure 4. Microphotograph: (a) Elliptic filter, (b) Biquad.
(b) Figure 5. Cut-off frequency for several digital words: (a) Elliptic filter, (b) Biquad implementation.
In this way, we can simplify the structure of the programmable transconductor in the LC-ladder filter design and use a simpler folded stage, i.e., without the four-cascode stage positive feedback shown in Fig.1. Then, the only complete programmable transconductor cell is used to implement the gyrator and the others are implemented by using the simpler one. The biquad does not support this simplification. The illustrated cut-off frequencies are tuned from 42 to 215 MHz and from 45 to 230 MHz for the LC-ladder filters and biquad respectively, corresponding to the variation of the transconductance from 1gm to 5gm. In accordance, the power consumption is comprised between 3.7-18.6 and 4.8-24 mW respectively. Total harmonic distortion (THD) of the filters was measured with 1 MHz input signal and 42 MHz cut-off frequency. In this situation, a THD of less than 1% (-40 dB) is obtained for 120 μA differential signal (60% Ibias) throughout the whole operating frequency range in all structures. Table I summarizes the most important postlayout simulation results for the elliptic, Butterworth and biquad filters, referred to the LSB cut-off frequency (42 MHz for the LC-ladder filters and 50 MHz for the biquad). A. Comparative Analysis In this section we present a comparison between several programmable filters implemented with similar technologies. Conclusions can then be drawn about the proposed design and the benefits of this technique. The most relevant characteristics of the compared filters are summarized in Table II.
1061
TABLE I.
SIMULATION RESULTS FOR THE FILTERS 3rd-order Filters
systems are currently being designed for controlling the frequency and Q-factor.
Biquad
2 Volts
Power supply voltage Frequency range (-3dB)
42-215 MHz
45-230 MHz
Power dissipation/pole
3.7 – 18.6 mW
4.8 - 24 mW
< 197 nArms
168.93 nArms
Total rms input-referred noise Maximum input signal current at 1% THD Dynamic range (1% THD)
ACKNOWLEDGMENT This work has been partially supported by DGA-FSE (PIP/187-2005) and MEC-FEDER (TIC2005-00285/MIC). REFERENCES
120 μA
120 μA
[1]
53 dB
54 dB
[2]
The most striking feature worth pointing out is that the use of the proposed strategy means substantially lower chip area (0.025 mm2/pole) and power consumption (3.7 mW/pole) with dynamic ranges of 53 dB. The results obtained with this technique are extremely encouraging. Although it is only the qualifying round, post-layout simulation results have been presented and important benefits of the proposed technique are clearly identified, especially the use of a small active area. Nevertheless, to obtain further details on the specifications of the compared filters and a more detailed explanation of the background of these systems, the reader is referred to the original works [11-13] to draw additional conclusions. V.
CONCLUSIONS
This paper describes an approach for realizing digitally programmable CT filters compatible with the latest low-cost digital CMOS processes over the VHF/UHF range. The strategy followed is based on a fully-balanced pseudodifferential current-mode transconductor with discrete tunability. The apparent complexity inherent to discrete tuning is overcome taking into account that in modern communication systems, the digital circuit controls the filter bandwidth. Obviously, frequency span and resolution are dependent of the transconductance ratio and the digital word length. The use of pseudo-differential structures without the need for CMFB circuits clearly leads to obtain chip area and power consumption improvements with regard to other studies of the prior art. This work reports post-layout simulation results and the implementation microphotographs. Currently, the chips are being tested and for the conference the final specifications will be shown. Automatic tuning TABLE II.
CMOS Technology Power supply voltage: VCC Frequency range Area/pole Power /pole at the lowest frequency Maximum input signal at 1% THD Dynamic range
[3]
[4]
[5] [6] [7]
[8]
[9]
[10] [11]
[12]
[13]
E. Grochowski and R.F. Hoyt, “Future trends in hard disk drives”, IEEE Trans. Magnetics, vol. 32, 3,1850-1854, 1966. R. Castello, I. Bietti and F. Svelto, “High-frequency analog filters in deep-submicron CMOS technology”, Digest of Technical Papers, IEEE International Solid-State Circuits Conference, San Francisco, 74-75, 1999. P-H Lu, C-Y. Wu and M-K Tsai, "Design techniques for VHF/UHF high-Q tunable bandpass filters using simple CMOS inverter-based trans-resistance amplifier", IEEE JSSC, 31, 5, 719-725, 1996. J-C. Voghell and M. Sawan, “A current tunable fully differential transconductor dedicated for filtering applications”, Proc. 11th Int. Conference on Microelectronics, pp. 221-224, 1999. M. J. Deen and A. Fjeldly, “CMOS RF modeling characterization and applications”, World Scientific, London, 2002. R. H. Zele and D. Allstot, “Low-power CMOS continuous-time filters”, IEEE JSSC, vol. 31, n. 2, pp. 157-168, 1996. S. L. Smith and E. Sánchez-Sinencio, “Low voltage integrators for high-frequency CMOS filters using current mode techniques”, IEEE Transactions on Circuits and Systems-II, vol. 43, 1, pp. 39-48, 1996. A. Otín, S. Celma and C. Aldea, “Digitally programmable CMOS transconductor for very high frequency”, Microelectronics Reliability Journal, 44, 5, 869-875, 2004. A. Otín, S. Celma and C. Aldea, “A 0.18 μm CMOS 3rd-order Digitally Programmable Gm-C Filter for VHF Applications”, IEICE Transactions on Information and Systems, vol. E88-D, nº 7, pp. 15091510, July 2005. D. J. Allstot, “A precision variable-supply CMOS comparator”, IEEE JSSC, vol. 17, n. 6, pp. 1080-1087, 1982. S. Pavan and Y. Tsividis, “High frequency continuous time filters in digital CMOS processes”, Kluwer Academic Publishers, London, 2000. V. Gopinathan, M. Tarsia and D. Choi, “Design considerations and implementation of a programmable high-frequency continuous-time filter and variable-gain amplifier in submicrometer CMOS”, IEEE JSSC, 34, 12, 1698-1707, Dec. 1999. G. Bollati, S. Marchese, M. Demicheli and R. Castello, “An eightorder CMOS low-pass filter with 30-120 MHz tuning range and programmable boost”, IEEE JSSC, 36, 7, 1056-1066, July 2001.
COMPARATIVE ANALYSIS OF SEVERAL PROGRAMMABLE STRUCTURES This work 3rdorder filter
PAVAN [11] 4th order filter
GOPIN. [12] 7th order filter
BOLL. [13] 8th order filter
0.35 μm n-well
0.25 μm n-well
0.25 μm n-well
0.25 μm n-well
2 Volts
3.3 Volts
2.5 Volts
2.5 Volts
42 – 215 MHz 0.025 mm2 (double-poly)
60 - 350 MHz 0.038 mm2 (MOS-C)
30 - 100 MHz 0.43 mm2 (metal-metal C)
30 - 120 MHz 0.23 mm2 (MOS-C)
3.73 mW
17.5 mW
30 mW
15 mW
120 μA
380 mVpp
455 mVpp
200 mVpp
53 dB
54 dB
--------
45 dB
1062
I.
INTRODUCTION
The hard disk drive (HDD) has become in an important and extremely useful element in every information processing system. The trends in HDDs involve high user densities and data rates supported by current storage systems [1]. This demands complex read channel ICs, in particular, continuous-time filters with variable bandwidths, over a wide range (typically 1:5), to accommodate the different data rates required by constant density recording and servo processing [2]. Among the different continuous-time integrated filter strategies, the Gm-C approach [3, 4] is the preferred option, thanks to its acceptable performance over the VHF/UHF range. To achieve a digitally programmable continuous-time filter, which is compatible with low-cost digital CMOS processes and suitable with high frequency requirements, specific design techniques of building block based filters must be explored [5]. There are many well-known varying ways to implement a transconductor in CMOS technology. Current-mode pseudo-differential transconductors exhibit low-voltage, moderated linearity and very high frequency operation capability with high power efficiency [6, 7]. This approach has been adopted in a new design of transconductor cell with digital programmability [8, 9], serving as an excellent choice to implement high frequency filters with a trade-off between dynamic range and tuning capability. In this paper, different digitally programmable and continuously tunable 0.35µm CMOS technology filters with
a 2 V power supply are proposed: one 2nd-order biquad and two 3rd-order low-pass LC ladder filters (Butterworth and elliptical approximations). The programmability exhibited by the filters is achieved owing to the design of a generic programmable transconductor, which could be used in other higher order filter topologies. The proposed filters are made up of a parallel connection of unit folded-cascode cells specifically designed for wide programmability range. The tunability exhibited by the filters covers the 40-200 MHz range with a total harmonic distortion (THD) of less than 1% for 120μA differential signal (60% Ibias) throughout the whole operating frequency range in all filters. II.
TECHNOLOGICAL AND ARCHITECTURAL ISSUES
An optimal solution for digitally programmable analog filters in VHF/UHF range is to take advantage of currentmode pseudo-differential topologies and to provide them with digital programmability. Several high-performance continuous-time filters have been implemented to demonstrate the behavior pattern of the proposed transconductor cell. The realizations are based on two of the most popular type of structures, ladder filters and biquadratic based filters. The frequency of these filters ranges over the VHF band. The programmability of the filter is achieved by varying a digital word. On the other hand, a fine tuning of the proposed structure can be achieved as the transconductance value can be controlled by varying the bias current for a fixed digital word. Hence, discrete steps are swept maintaining the same dynamic range by varying the bias current, and a control over the DC-gain can be achieved by modifying the ratio between the bias currents in the transconductor cell. The quality factor (e.g. the pass-band ripple) of the filters is controlled by CMOS resistors, which are also employed to control the phase error over the whole frequency range [9]. A. Transconductor Cell The folded cascode circuit exhibits a substantial improvement in biasing flexibility, because of the increased
This work has been partially supported by DGA-FSE (PIP/187-2005) and MEC-FEDER (TIC2005-00285/MIC)
0-7803-9390-2/06/$20.00 ©2006 IEEE
1059
ISCAS 2006
drain-voltage of the transistors, at the cost of additional current sources and bias voltages. Another important benefit by using these stages is that avoiding the biasing constraints associated to the other cascode configurations, i.e., the gatesource voltages need not be kept small, results in smaller and simpler devices for a given bias current level, and larger unity-gain frequencies. This is the option we are going to use in this work and the fully-balanced pseudo-differential current-mode transconductance cell implemented by using the folded stage is shown in Fig. 1. In this approach, the use of a cascode output is not necessary because the DC gain is increased by providing positive feedback compensation for the signal current and boosting the input resistance of the integrator [10]. Theoretically, adjusting the equivalent negative resistance, the DC gain could be infinity but in practice, mismatching limits the dc gain. The use of pseudo-differential topologies requires a careful and efficient control over the common-mode behaviour of the circuit. It is worth noting that this structure not only stabilises the common-mode voltage, but also rejects the input common-mode signals by means of partial positive feedback [6, 7]. In order to reach the maximum frequency of operation with moderated power consumption, the integration capacitance is CI is constituted by the parasitic capacitors and an additional one implemented by using a double-poly capacitor. Nevertheless, MOS-C or metal-metal capacitors could be used depending on the CMOS process features. In this way, to control the operation frequency and reduce the phase error, a shunt connection is made at the input between a resistance (implemented with a transistor working in the linear region) and the integration capacitance CI. We then obtain a compensation scheme for the transconductor based on a RC circuit at the input. By means of a parallel connection of equal transconductors switched by a digital word, we guarantee that the dynamic range for each gm value and the total external node capacitances will be kept almost constant. The feasibility of the programmable array of transconductors has been proven obtaining frequency scaling as expected [8, 9]. I-O
I+i
gm
gm
gm
In consequence, we can conclude that by varying the digital word from 1 to 5, the expected linear dependence of the unity-gain frequency is obtained and the phase error is effectively reduced over all the programming range (phase error less than 3º). By driving the gates of cascode transistors with modulated digital voltages, we can obtain the desired transconductance with no switches in the signal path and power consumption proportional to the transconductance necessary in each frequency sub-range. HIGH PERFORMANCE FILTER IMPLEMENTATION
III.
The filter can be designed using either biquads or ladder filters. The dynamic range of the low-pass ladder filter is superior to the dynamic range of the biquadratic based lowpass filters. Furthermore, the ladder filter is less sensitive to the tolerances of the components, mainly in the filter passband. However, the ladder filter is not as versatile as the biquad and its tuning is more complicated. A. Active LC-Ladder Prototypes First, two different fully-balanced pseudo-differential low-pass 3rd-order filters, with Butterworth and elliptic approximations, were chosen to be tested. Both filters are derived from their doubly terminated LC ladder prototype in the current mode. The Gm-C implementation can be accomplished by substituting the terminating resistors in the prototype by diode-connected transconductors and the inductor by a gyrator. According to this idea, Fig. 2 shows the block diagram of the elliptic filter with resistive termination using a gyratorcapacitor combination. The Butterworth filter is described with the same block diagram except for the floating capacitor C2 and its respective compensation resistance which do not appear. The LC filter shows an inherent 6 dB loss and has been compensated by using a 2gm-stage in both filters. B. Cascade Approach Biquadratic second order sections are cascaded to obtain higher order structures. The filters obtained by using this approach show more modularity than LC-ladder counterparts. Another important benefit is the independent control over each section which leads to a more versatile implementation. The main disadvantage of this approach, however, is the high sensitivity to the tolerances of the components. Fig. 3 shows the block diagram of the biquad implementation.
IBIAS
R
C2
R
_
R _
MPi C
I
CI
+
VOUT Mi
R
I-i
Iin
VFN
gm
gm
2C1
_
+ gm
gm
IO
+ gm
gm _
_ +
2CL
_
2C3
gm _
R
+
Figure 1. Fully balanced pseudo-differential current-mode transconductance cell.
_
_ + 2C1
MNi
gm
R
R
VB
Vin
_ +
2C3
+
_
+
_
gm
2xgm
_ +
_ +
IOut
R C2
R
Figure 2. Active implementation: Butterworth (C2=0) and Elliptic (C2≠0).
1060
R _
+
Iin
2C1
gm _
_
+
R
gm
gm +
2C1
_
_
+
+
_ 2C2
_
+ gm
+
_
IOut +
R
Figure 3. Biquad active implementation.
IV.
RESULTS (a)
Three different Gm-C low-pass filters have been designed in a pure digital 0.35 μm double-well CMOS technology with a 2 V power supply. The maximum active area per pole is 0.025 mm2. A microphotograph of the chips is shown in Fig. 4. The filter frequency response obtained by the postlayout simulations for the prototypes is reported in Fig. 5. According to the nominal transconductance obtained with the proposed programmable cell, the filter capacitances were selected in order to obtain a nominal cut-off frequency of 42 MHz. To achieve a high cut-off frequency, the filter operates also on parasitic capacitances. This is possible since the parasitic capacitances are all at nodes where a capacitance is desired in the filter. The need for a high impedance node obtained with the folded-cascode transconductor disappears depending on how the cell is connected to the rest of the circuit.
(a)
(b) Figure 4. Microphotograph: (a) Elliptic filter, (b) Biquad.
(b) Figure 5. Cut-off frequency for several digital words: (a) Elliptic filter, (b) Biquad implementation.
In this way, we can simplify the structure of the programmable transconductor in the LC-ladder filter design and use a simpler folded stage, i.e., without the four-cascode stage positive feedback shown in Fig.1. Then, the only complete programmable transconductor cell is used to implement the gyrator and the others are implemented by using the simpler one. The biquad does not support this simplification. The illustrated cut-off frequencies are tuned from 42 to 215 MHz and from 45 to 230 MHz for the LC-ladder filters and biquad respectively, corresponding to the variation of the transconductance from 1gm to 5gm. In accordance, the power consumption is comprised between 3.7-18.6 and 4.8-24 mW respectively. Total harmonic distortion (THD) of the filters was measured with 1 MHz input signal and 42 MHz cut-off frequency. In this situation, a THD of less than 1% (-40 dB) is obtained for 120 μA differential signal (60% Ibias) throughout the whole operating frequency range in all structures. Table I summarizes the most important postlayout simulation results for the elliptic, Butterworth and biquad filters, referred to the LSB cut-off frequency (42 MHz for the LC-ladder filters and 50 MHz for the biquad). A. Comparative Analysis In this section we present a comparison between several programmable filters implemented with similar technologies. Conclusions can then be drawn about the proposed design and the benefits of this technique. The most relevant characteristics of the compared filters are summarized in Table II.
1061
TABLE I.
SIMULATION RESULTS FOR THE FILTERS 3rd-order Filters
systems are currently being designed for controlling the frequency and Q-factor.
Biquad
2 Volts
Power supply voltage Frequency range (-3dB)
42-215 MHz
45-230 MHz
Power dissipation/pole
3.7 – 18.6 mW
4.8 - 24 mW
< 197 nArms
168.93 nArms
Total rms input-referred noise Maximum input signal current at 1% THD Dynamic range (1% THD)
ACKNOWLEDGMENT This work has been partially supported by DGA-FSE (PIP/187-2005) and MEC-FEDER (TIC2005-00285/MIC). REFERENCES
120 μA
120 μA
[1]
53 dB
54 dB
[2]
The most striking feature worth pointing out is that the use of the proposed strategy means substantially lower chip area (0.025 mm2/pole) and power consumption (3.7 mW/pole) with dynamic ranges of 53 dB. The results obtained with this technique are extremely encouraging. Although it is only the qualifying round, post-layout simulation results have been presented and important benefits of the proposed technique are clearly identified, especially the use of a small active area. Nevertheless, to obtain further details on the specifications of the compared filters and a more detailed explanation of the background of these systems, the reader is referred to the original works [11-13] to draw additional conclusions. V.
CONCLUSIONS
This paper describes an approach for realizing digitally programmable CT filters compatible with the latest low-cost digital CMOS processes over the VHF/UHF range. The strategy followed is based on a fully-balanced pseudodifferential current-mode transconductor with discrete tunability. The apparent complexity inherent to discrete tuning is overcome taking into account that in modern communication systems, the digital circuit controls the filter bandwidth. Obviously, frequency span and resolution are dependent of the transconductance ratio and the digital word length. The use of pseudo-differential structures without the need for CMFB circuits clearly leads to obtain chip area and power consumption improvements with regard to other studies of the prior art. This work reports post-layout simulation results and the implementation microphotographs. Currently, the chips are being tested and for the conference the final specifications will be shown. Automatic tuning TABLE II.
CMOS Technology Power supply voltage: VCC Frequency range Area/pole Power /pole at the lowest frequency Maximum input signal at 1% THD Dynamic range
[3]
[4]
[5] [6] [7]
[8]
[9]
[10] [11]
[12]
[13]
E. Grochowski and R.F. Hoyt, “Future trends in hard disk drives”, IEEE Trans. Magnetics, vol. 32, 3,1850-1854, 1966. R. Castello, I. Bietti and F. Svelto, “High-frequency analog filters in deep-submicron CMOS technology”, Digest of Technical Papers, IEEE International Solid-State Circuits Conference, San Francisco, 74-75, 1999. P-H Lu, C-Y. Wu and M-K Tsai, "Design techniques for VHF/UHF high-Q tunable bandpass filters using simple CMOS inverter-based trans-resistance amplifier", IEEE JSSC, 31, 5, 719-725, 1996. J-C. Voghell and M. Sawan, “A current tunable fully differential transconductor dedicated for filtering applications”, Proc. 11th Int. Conference on Microelectronics, pp. 221-224, 1999. M. J. Deen and A. Fjeldly, “CMOS RF modeling characterization and applications”, World Scientific, London, 2002. R. H. Zele and D. Allstot, “Low-power CMOS continuous-time filters”, IEEE JSSC, vol. 31, n. 2, pp. 157-168, 1996. S. L. Smith and E. Sánchez-Sinencio, “Low voltage integrators for high-frequency CMOS filters using current mode techniques”, IEEE Transactions on Circuits and Systems-II, vol. 43, 1, pp. 39-48, 1996. A. Otín, S. Celma and C. Aldea, “Digitally programmable CMOS transconductor for very high frequency”, Microelectronics Reliability Journal, 44, 5, 869-875, 2004. A. Otín, S. Celma and C. Aldea, “A 0.18 μm CMOS 3rd-order Digitally Programmable Gm-C Filter for VHF Applications”, IEICE Transactions on Information and Systems, vol. E88-D, nº 7, pp. 15091510, July 2005. D. J. Allstot, “A precision variable-supply CMOS comparator”, IEEE JSSC, vol. 17, n. 6, pp. 1080-1087, 1982. S. Pavan and Y. Tsividis, “High frequency continuous time filters in digital CMOS processes”, Kluwer Academic Publishers, London, 2000. V. Gopinathan, M. Tarsia and D. Choi, “Design considerations and implementation of a programmable high-frequency continuous-time filter and variable-gain amplifier in submicrometer CMOS”, IEEE JSSC, 34, 12, 1698-1707, Dec. 1999. G. Bollati, S. Marchese, M. Demicheli and R. Castello, “An eightorder CMOS low-pass filter with 30-120 MHz tuning range and programmable boost”, IEEE JSSC, 36, 7, 1056-1066, July 2001.
COMPARATIVE ANALYSIS OF SEVERAL PROGRAMMABLE STRUCTURES This work 3rdorder filter
PAVAN [11] 4th order filter
GOPIN. [12] 7th order filter
BOLL. [13] 8th order filter
0.35 μm n-well
0.25 μm n-well
0.25 μm n-well
0.25 μm n-well
2 Volts
3.3 Volts
2.5 Volts
2.5 Volts
42 – 215 MHz 0.025 mm2 (double-poly)
60 - 350 MHz 0.038 mm2 (MOS-C)
30 - 100 MHz 0.43 mm2 (metal-metal C)
30 - 120 MHz 0.23 mm2 (MOS-C)
3.73 mW
17.5 mW
30 mW
15 mW
120 μA
380 mVpp
455 mVpp
200 mVpp
53 dB
54 dB
--------
45 dB
1062
