A Gm3 Cancellation Bias For 60GHz Doherty Power Amplifier
A Gm3 Cancellation Bias For 60GHz Doherty Power Amplifier Aaron Tan1, Kaixue Ma2, Zhi Hui Kong1 1 Virtus Lab, School of EEE, NTU, Singapore 2 School of Physical Electronics, UESTC, Chengdu, China 1 [email protected], 2 [email protected] Abstract—We present a 60GHz CMOS Doherty Power Amplifier (DPA) with a proposed wideband broadside coupler and a phaseshifter to adjust the phase difference between the two paths. The DPA achieves a gain of 8.5dB under a supply voltage of 1.2V, which allows the saturated output power to be about 14.5dBm. A peak PAE of 11% and output compression point of 10.8dBm were exhibited. Comparing to a balance power amplifier, the IMD3 improvement is approximately 9dB. The proposed design achieves the highest Figure of Merit (FoM) as compared to state of the art 60GHz DPA in CMOS process. Keywords-component; RF CMOS, Doherty Power Amplifier, Gm3 Cancellation
I.
Kiat Seng Yeo International Relations and Graduate Studies Singapore University of Technology and Design, Singapore [email protected]
A broadside coupler in a multi-layered CMOS process has been implemented and optimized to ensure about 0.4dB of over-coupling. The spread of the phase difference is also less than 2.2°. The pre-amplifiers are to enhance the gain of individual branches due to the transistors struggling for gain at the millimeter-wave frequencies. The carrier amplifier is biased at 0.3mA/µm for the highest fmax. Using that as a starting point, the peaking amplifier is biased below threshold voltage to serve two purposes; turn on after the input power reaches a favorable condition and act as a gm3 cancellation source for the carrier amplifier. 1
INTRODUCTION
Renewed interest in the conventional DPA [5] was seen with recent works on gigahertz frequency [6,7] that provide linearity enhancement without compromising its efficiency. Only one work at 60GHz [8] demonstrates the DPA in CMOS technology but its low PAE and output saturation power do not put it near its competitors of other PAs. We proposed a gm3 cancellation bias DPA with a 60GHz broadside coupler. A phase shifter was implemented to off-set the phase at the output of the carrier PA. DOHERTY POWER AMPLIFIER DESIGN
The block diagram of the DPA is shown in Figure 1. Two branches of power amplifiers with the main and peaking power amplifiers biased to cancel the gm3 coefficient [9].
gm1 (A/V), gm 2 (A/V 2), gm3 (A/V3)
Power amplifier (PA) being one of the most power hungry blocks in a transceiver, has received a great deal of attention by the research community, particularly at the millimeter-wave range of 57GHz to 66GHz band [1-4], which supports short range, high data rate applications due to oxygen absorption in the atmosphere and provides it immunity to interference and allows for high reusability.
II.
gm gm2 gm3
0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 0.2
0.4
0.6 0.8 Vgs (V)
1
1.2
Figure 2. Plots for Transconductances
From Figure 2, gm3 can be approximately cancelled if we pick the corresponding point for the Class C bias which has a negative correlation to the biasing point of Class AB. The phase difference of about 54° at 60GHz also has to be off-set to ensure the signals are constructively combined by a transmission line.
Figure 1. Block Diagram of DPA Figure 3. Schematic of Proposed DPA with Gm3 Cancellation Bias
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ISOCC 2015
III.
RESULTS OF INTEGRATED DPA
IV.
The schematic of the DPA is as shown in Figure 3. It achieves a gain of 8.5dB and a peak PAE of 11% seen from Figure 4(a) and 4(b). The Psat and P1dB are approximately 14.5dBm and 10.8dBm respectively from Figure 4(c). The power consumption of the entire circuit is 89.2mW. The IMD3 is improved by about 9dB compared to the balance PA at a higher output power level illustrated in Figure 4(d). At higher output power, the peaking amplifier turned on with linearizing effect to the overall DPA due to the gm3 cancellation biasing. 10
0
ACKNOWLEDGMENT The authors would like to thank GLOBALFOUNDRIES Singapore for providing the Process Design Kit. They would also like to thank Centre of Excellence in IC Design (VIRTUS), Nanyang Technological University, Singapore, for their support.
8
-20
6
PAE Power Gain 10
PAE (%)
Power Gain (dB)
S-Parameters (dB)
15
-10
4
-30 S11 S12 S21 S22
-40
-50
5
5.5
A 60GHz DPA with gm3 cancellation bias is presented. This proposed DPA achieves a gain of 8.5dB and a PAE of 11%. The demonstrated Psat is 14.5dBm and output referred compression point P1dB is 10.8dBm. The linearity of the DPA is compared to a balance PA and the improvement of 9dB can be seen. The FoM is comparable to other PAs in Table I. To the authors’ best knowledge, this DPA has the highest PAE and P1dB as compared to the only state of the art 60GHz CMOS DPA.
20
10
5 2
REFERENCES
6 6.5 Frequency (Hz)
0 -30
7
-20
-10 Pin (dBm)
10
0
10
0
[1]
x 10
(a)
(b) [2]
-25
15 Compression Curve 10
-30
Balance PA DPA
5 P 1dB
[3]
-35 IMD3 (dBc)
1st Order -5
P
out
(dBm)
0
-10
-9dB
-40
-45
[4]
-15
-50
-20
-25 -30
-20
-10 0 Pin (dBm)
10
20
-55 -10
(c)
-5
0 P out (dBm)
5
10
[5]
(d)
Figure 4. (a) S-Parameters of DPA (b) Power Gain and PAE of DPA (c) Output Power and Compression Point of DPA (d) IMD3 Comparison of DPA and Balance PA TABLE I.
PERFORMANCE COMPARISON WITH PUBLISHED 60GHZ CMOS PA This Work
[8]
[1]
[4]
[2]
[3]
Supply(V)
65nm DPA 1.2
0.13µm DPA 1.6
65nm PA 1
65nm PA 1.2
90nm PA 1.5
90nm PA 1.1
Gain(dB)
8.5
13.5
15.8
8.3
5.2
9.56
Psat(dBm) Peak PAE(%) P1dB(dBm)
14.5
7.8
11.5
11
9.3
11.48
11
3
11
7.1
7.4
10.2
10.8
7
2.5
9.7
6.4
8.04
19
12
23
13
9
17
References Process
FoM
CONCLUSION
[6]
[7]
[8]
[9]
W. L. Chan, J. R. Long, M. Spirito, and J. J. Pekarik, "A 60GHzband 1V 11.5dBm power amplifier with 11% PAE in 65nm CMOS," in Solid-State Circuits Conference - Digest of Technical Papers, 2009. ISSCC 2009. IEEE International, 2009, pp. 380-381,381a. Y. Terry, M. Q. Gordon, K. K. W. Tang, K. H. K. Yau, Y. Ming-Ta, P. Schvan, and S. P. Voinigescu, "Algorithmic Design of CMOS LNAs and PAs for 60-GHz Radio," Solid-State Circuits, IEEE Journal of, vol. 42, pp. 1044-1057, 2007. Z. Nan, S. Lingling, W. Jincai, L. Jun, L. Jia, S. Guodong, and L. He, "A 60GHz power amplifier using 90-nm RF-CMOS technology," in ASIC (ASICON), 2011 IEEE 9th International Conference on, 2011, pp. 933-936. F. Wei, Y. Hao, Y. Kiat Seng, L. Xiong, and L. Wei Meng, "A 44-to60GHz, 9.7dBm P1dB, 7.1% PAE power amplifier with 2D distributed power combining by metamaterial-based zero-phaseshifter in 65nm CMOS," in Microwave Symposium Digest (MTT), 2012 IEEE MTT-S International, 2012, pp. 1-3. W. H. Doherty, "A New High Efficiency Power Amplifier for Modulated Waves," Radio Engineers, Proceedings of the Institute of, vol. 24, pp. 1163-1182, 1936. A. Agah, B. Hanafi, H. Dabag, P. Asbeck, L. Larson, and J. Buckwalter, "A 45GHz Doherty power amplifier with 23% PAE and 18dBm output power, in 45nm SOI CMOS," in Microwave Symposium Digest (MTT), 2012 IEEE MTT-S International, 2012, pp. 1-3. V. Camarchia, J. Fang, J. Moreno Rubio, M. Pirola, and R. Quaglia, "7 GHz MMIC GaN Doherty Power Amplifier With 47% Efficiency at 7 dB Output Back-Off," Microwave and Wireless Components Letters, IEEE, vol. 23, pp. 34-36, 2013. B. Wicks, E. Skafidas, and R. Evans, "A 60-GHz fully-integrated Doherty power amplifier based on 0.13um CMOS process," in Radio Frequency Integrated Circuits Symposium, 2008. RFIC 2008. IEEE, 2008, pp. 69-72. Y. Youngoo, C. Jeonghyeon, S. Bumjae, and B. Kim, "A fully matched N-way Doherty amplifier with optimized linearity," Microwave Theory and Techniques, IEEE Transactions on, vol. 51, pp. 986-993, 2003.
FoM (ITRS) = Psat+Gain+20log(fc[GHz])+10log(PAE)-30dB
The FoM includes the important parameters of a PA and we modified it so that the numbers would give a relatively lower numbers for a clearer comparison.
-page number-
ISOCC 2015
I.
Kiat Seng Yeo International Relations and Graduate Studies Singapore University of Technology and Design, Singapore [email protected]
A broadside coupler in a multi-layered CMOS process has been implemented and optimized to ensure about 0.4dB of over-coupling. The spread of the phase difference is also less than 2.2°. The pre-amplifiers are to enhance the gain of individual branches due to the transistors struggling for gain at the millimeter-wave frequencies. The carrier amplifier is biased at 0.3mA/µm for the highest fmax. Using that as a starting point, the peaking amplifier is biased below threshold voltage to serve two purposes; turn on after the input power reaches a favorable condition and act as a gm3 cancellation source for the carrier amplifier. 1
INTRODUCTION
Renewed interest in the conventional DPA [5] was seen with recent works on gigahertz frequency [6,7] that provide linearity enhancement without compromising its efficiency. Only one work at 60GHz [8] demonstrates the DPA in CMOS technology but its low PAE and output saturation power do not put it near its competitors of other PAs. We proposed a gm3 cancellation bias DPA with a 60GHz broadside coupler. A phase shifter was implemented to off-set the phase at the output of the carrier PA. DOHERTY POWER AMPLIFIER DESIGN
The block diagram of the DPA is shown in Figure 1. Two branches of power amplifiers with the main and peaking power amplifiers biased to cancel the gm3 coefficient [9].
gm1 (A/V), gm 2 (A/V 2), gm3 (A/V3)
Power amplifier (PA) being one of the most power hungry blocks in a transceiver, has received a great deal of attention by the research community, particularly at the millimeter-wave range of 57GHz to 66GHz band [1-4], which supports short range, high data rate applications due to oxygen absorption in the atmosphere and provides it immunity to interference and allows for high reusability.
II.
gm gm2 gm3
0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 0.2
0.4
0.6 0.8 Vgs (V)
1
1.2
Figure 2. Plots for Transconductances
From Figure 2, gm3 can be approximately cancelled if we pick the corresponding point for the Class C bias which has a negative correlation to the biasing point of Class AB. The phase difference of about 54° at 60GHz also has to be off-set to ensure the signals are constructively combined by a transmission line.
Figure 1. Block Diagram of DPA Figure 3. Schematic of Proposed DPA with Gm3 Cancellation Bias
-page number-
ISOCC 2015
III.
RESULTS OF INTEGRATED DPA
IV.
The schematic of the DPA is as shown in Figure 3. It achieves a gain of 8.5dB and a peak PAE of 11% seen from Figure 4(a) and 4(b). The Psat and P1dB are approximately 14.5dBm and 10.8dBm respectively from Figure 4(c). The power consumption of the entire circuit is 89.2mW. The IMD3 is improved by about 9dB compared to the balance PA at a higher output power level illustrated in Figure 4(d). At higher output power, the peaking amplifier turned on with linearizing effect to the overall DPA due to the gm3 cancellation biasing. 10
0
ACKNOWLEDGMENT The authors would like to thank GLOBALFOUNDRIES Singapore for providing the Process Design Kit. They would also like to thank Centre of Excellence in IC Design (VIRTUS), Nanyang Technological University, Singapore, for their support.
8
-20
6
PAE Power Gain 10
PAE (%)
Power Gain (dB)
S-Parameters (dB)
15
-10
4
-30 S11 S12 S21 S22
-40
-50
5
5.5
A 60GHz DPA with gm3 cancellation bias is presented. This proposed DPA achieves a gain of 8.5dB and a PAE of 11%. The demonstrated Psat is 14.5dBm and output referred compression point P1dB is 10.8dBm. The linearity of the DPA is compared to a balance PA and the improvement of 9dB can be seen. The FoM is comparable to other PAs in Table I. To the authors’ best knowledge, this DPA has the highest PAE and P1dB as compared to the only state of the art 60GHz CMOS DPA.
20
10
5 2
REFERENCES
6 6.5 Frequency (Hz)
0 -30
7
-20
-10 Pin (dBm)
10
0
10
0
[1]
x 10
(a)
(b) [2]
-25
15 Compression Curve 10
-30
Balance PA DPA
5 P 1dB
[3]
-35 IMD3 (dBc)
1st Order -5
P
out
(dBm)
0
-10
-9dB
-40
-45
[4]
-15
-50
-20
-25 -30
-20
-10 0 Pin (dBm)
10
20
-55 -10
(c)
-5
0 P out (dBm)
5
10
[5]
(d)
Figure 4. (a) S-Parameters of DPA (b) Power Gain and PAE of DPA (c) Output Power and Compression Point of DPA (d) IMD3 Comparison of DPA and Balance PA TABLE I.
PERFORMANCE COMPARISON WITH PUBLISHED 60GHZ CMOS PA This Work
[8]
[1]
[4]
[2]
[3]
Supply(V)
65nm DPA 1.2
0.13µm DPA 1.6
65nm PA 1
65nm PA 1.2
90nm PA 1.5
90nm PA 1.1
Gain(dB)
8.5
13.5
15.8
8.3
5.2
9.56
Psat(dBm) Peak PAE(%) P1dB(dBm)
14.5
7.8
11.5
11
9.3
11.48
11
3
11
7.1
7.4
10.2
10.8
7
2.5
9.7
6.4
8.04
19
12
23
13
9
17
References Process
FoM
CONCLUSION
[6]
[7]
[8]
[9]
W. L. Chan, J. R. Long, M. Spirito, and J. J. Pekarik, "A 60GHzband 1V 11.5dBm power amplifier with 11% PAE in 65nm CMOS," in Solid-State Circuits Conference - Digest of Technical Papers, 2009. ISSCC 2009. IEEE International, 2009, pp. 380-381,381a. Y. Terry, M. Q. Gordon, K. K. W. Tang, K. H. K. Yau, Y. Ming-Ta, P. Schvan, and S. P. Voinigescu, "Algorithmic Design of CMOS LNAs and PAs for 60-GHz Radio," Solid-State Circuits, IEEE Journal of, vol. 42, pp. 1044-1057, 2007. Z. Nan, S. Lingling, W. Jincai, L. Jun, L. Jia, S. Guodong, and L. He, "A 60GHz power amplifier using 90-nm RF-CMOS technology," in ASIC (ASICON), 2011 IEEE 9th International Conference on, 2011, pp. 933-936. F. Wei, Y. Hao, Y. Kiat Seng, L. Xiong, and L. Wei Meng, "A 44-to60GHz, 9.7dBm P1dB, 7.1% PAE power amplifier with 2D distributed power combining by metamaterial-based zero-phaseshifter in 65nm CMOS," in Microwave Symposium Digest (MTT), 2012 IEEE MTT-S International, 2012, pp. 1-3. W. H. Doherty, "A New High Efficiency Power Amplifier for Modulated Waves," Radio Engineers, Proceedings of the Institute of, vol. 24, pp. 1163-1182, 1936. A. Agah, B. Hanafi, H. Dabag, P. Asbeck, L. Larson, and J. Buckwalter, "A 45GHz Doherty power amplifier with 23% PAE and 18dBm output power, in 45nm SOI CMOS," in Microwave Symposium Digest (MTT), 2012 IEEE MTT-S International, 2012, pp. 1-3. V. Camarchia, J. Fang, J. Moreno Rubio, M. Pirola, and R. Quaglia, "7 GHz MMIC GaN Doherty Power Amplifier With 47% Efficiency at 7 dB Output Back-Off," Microwave and Wireless Components Letters, IEEE, vol. 23, pp. 34-36, 2013. B. Wicks, E. Skafidas, and R. Evans, "A 60-GHz fully-integrated Doherty power amplifier based on 0.13um CMOS process," in Radio Frequency Integrated Circuits Symposium, 2008. RFIC 2008. IEEE, 2008, pp. 69-72. Y. Youngoo, C. Jeonghyeon, S. Bumjae, and B. Kim, "A fully matched N-way Doherty amplifier with optimized linearity," Microwave Theory and Techniques, IEEE Transactions on, vol. 51, pp. 986-993, 2003.
FoM (ITRS) = Psat+Gain+20log(fc[GHz])+10log(PAE)-30dB
The FoM includes the important parameters of a PA and we modified it so that the numbers would give a relatively lower numbers for a clearer comparison.
-page number-
ISOCC 2015
