A Heuristic Method for Statistical Digital Circuit Sizing
A Heuristic Method for Statistical Digital Circuit Sizing Stephen Boyd
Seung-Jean Kim Mark Horowitz
Microlithography’06 2/23/06
Dinesh Patil
Statistical variation in digital circuits
• growing in importance as devices shrink • modeling still open – many sources: environmental, process parameter variation, lithography – intrachip, interchip variation – distributions, correlations not well known, change as process matures
Microlithography’06 2/23/06
1
Statistical digital circuit sizing
• standard design approaches: margining, guardbanding, design over corners • statistical design explicitly takes statistical variation into account (combines circuit design with design for manufacturing, yield optimization, design centering, . . . ) • statistical design is very hard problem (even for small circuits) • this talk: a (relatively) simple heuristic method for statistical design that appears to work well
Microlithography’06 2/23/06
2
Outline
• A quick example • Digital circuit sizing: models and optimization • New method for statistical digital circuit sizing • Digital circuit sizing example • Conclusions and future work
Microlithography’06 2/23/06
3
A Quick Example
Example: Ladner-Fisher 32-bit adder
• 64 inputs, 33 outputs, 451 gates, 3214 paths, max depth 8 • simplified RC delay model • design variables: 451 scale factors for gates • cycle time Tcycle is max path delay • minimize cycle time subject to limits on area, min/max scale factor
Microlithography’06 2/23/06
4
Optimization results (no statistical variation) path delays with optimized PSfrag replacements
& uniform scale factors (same total area)
# of paths
4000
2000
0 0
Microlithography’06 2/23/06
optimal
20
uniform
40 60 path delay
80
100
5
Statistical variation in gate delay PSfrag replacements
• simple Pelgrom model; larger gates have less (relative) variation in delay • min sized gate has 10% variation
probability
x=5
x=2 x=1 1
Microlithography’06 2/23/06
2
3
4 delay
5
6
7
6
Effects of statistical variation on nominal optimal design Tcycle PDF estimated via Monte Carlo PSfrag replacements
Q.95 (Tcycle )
cycle time PDF
nominal Tcycle
45
Microlithography’06 2/23/06
47
49 51 cycle time
53
55
7
Why isn’t Tcycle PDF centered around nominal value?
• Tcycle is max of 3214 random path delays • max of RVs behaves differently from sum of RVs – in sum, negative and positive deviations tend to cancel out; PDF is centered, has smaller relative variation – in max, large deviation of any leads to large value; PDF is shifted, skewed to right, has large relative deviation
Microlithography’06 2/23/06
8
PSfrag replacements
PDF of sum of random variables i=1 Xi ,
Xi ∼ N (1, 0.1) independent
PDF
Z=
PM
M =1 1
PDF
0.5
1.5 M = 10
10
PDF
5
15 M = 100
50
Microlithography’06 2/23/06
100
150
9
PSfrag replacements
PDF of max of random variables Z = max{X1, . . . , XM }, Xi ∼ N (1, 0.1) independent PDF
M =1
PDF
M = 10
PDF
M = 100
0.5
Microlithography’06 2/23/06
1
1.5
10
Simple worst-case design
• use slow model for all gates, e.g., 1.2Di • gives same design • can we do better?
Microlithography’06 2/23/06
11
Statistically robust design via new method
distribution of cycle time
samereplacements circuit, uncertainty PSfrag
model, and constraints
robust design
nominal optimal design
46
Microlithography’06 2/23/06
47
48
50 49 cycle time
51
52
53
12
Statistically robust design via new method
nominal optimal robust
nominal delay 45.9 46.5
ED 49.4 47.6
σD 0.91 0.29
Q.95(D) 51.1 48.1
• same circuit, uncertainty model, and constraints • compared to nominal optimal design, some gates are upsized, others are downsized
Microlithography’06 2/23/06
13
Nominal vs. statistical robust designs 4000
# of paths
PSfrag replacements
2000
0 0
20
40
60
path delay
Microlithography’06 2/23/06
14
path delay std. dev.
Path delay mean/std. dev. scatter plots 3
path delay std. dev.
PSfrag replacements 0 10
3
0 10
Microlithography’06 2/23/06
nominal optimal design
mean path delay
50
robust design
mean path delay
50
15
Area/delay trade-off analysis 15000 PSfrag replacements
Amax
11000
7000
robust design
nominal optimal design
3000 45
Microlithography’06 2/23/06
55 nominal cycle time
65
16
Area/delay trade-off analysis 15000 PSfrag replacements
Amax
11000
robust design
nominal optimal design
7000
3000 45
Microlithography’06 2/23/06
55 95% cycle time
65
17
Digital Circuit Sizing: Models
RA RBinput flip flops RC
Gate scaling combinational logic block
1 4
in
CX CY
output flip flops
6 out
2 5
7
3
clock
• combinational logic; circuit topology & gate types given • gate sizes (scale factors xi ≥ 1) to be determined • scale factors affect total circuit area, power and delay Microlithography’06 2/23/06
18
PSfrag replacements Ri
RC gate delay model Vdd Ciin Ciin
Ri Ciint
CiL
• input & intrinsic capacitances, driving resistance, load capacitance Ciin
= C¯iinxi,
Ciint
= C¯iintxi,
¯ i/xi, Ri = R
CiL
=
X
Cjin
j∈FO(i)
• RC gate delay:
Microlithography’06 2/23/06
Di = 0.69Ri(CiL + Ciint) 19
Path and circuit delay 1 PSfrag replacements
4
6
5
7
2
3
• delay of a path: sum of delays of gates on path • circuit delay (cycle time): maximum delay over all paths
Microlithography’06 2/23/06
20
Area & power
• total circuit area: A = x1A¯1 + · · · + xnA¯n • total power is P = Pdyn + Pstat – dynamic power Pdyn =
n X
2 fi(CiL + Ciint)Vdd
i=1
fi is gate switching frequency – static (leakage) power Pstat =
n X
IileakVdd
i=1
Iileak is leakage current (average over input states)
Microlithography’06 2/23/06
21
Parameters used in example • model parameters: gate type INV NAND2 NOR2 AOI21 OAI21
C¯ in 3 4 5 6 6
C¯ int 3 6 6 7 7
¯ R 0.48 0.48 0.48 0.48 0.48
A¯ 3 8 10 17 16
• time unit is τ , delay of min-size inverter (0.69 · 0.48 · 3 = 1) • area (total width) unit is width of NMOS in min-size inverter
Microlithography’06 2/23/06
22
Statistical variation in threshold voltage
• we focus on statistical variation in threshold voltage Vth (can also model variations in other parameters, e.g., tox, Leff , . . . ) • Pelgrom model:
¯Vth x−1/2 σVth = σ
where σ 2Vth is Vth variance for unit scaled gate • larger gates have less Vth variation
Microlithography’06 2/23/06
23
Statistical gate delay model • alpha-power law model: Vdd D∝ (Vdd − Vth)α (α ≈ 1.3) • for small variation in Vth, ∂D −0.5 σV = α(Vdd − Vth)−1σ ¯ x D σD ≈ V th th ∂Vth
• gate scaling affects mean delay and relative variation differently • relative variation decreases as gate scale factor increases: σD /D ∝ x−0.5 Microlithography’06 2/23/06
24
Statistical variation in gate delay PSfrag replacements
10% relative variation for min sized gate (σD /D = 0.1) inverter driving CL = 4
probability
x=5
x=2 x=1 1
Microlithography’06 2/23/06
2
3
4 delay
5
6
7
25
Statistical variation in gate delay inverter driving CL = 4
PSfrag replacements
10τ
delay
µ + 3σ µ
5τ
µ − 3σ
0
Microlithography’06 2/23/06
1
2
3 scale factor
4
5
26
Statistical leakage power model • leakage current (V0 ≈ 0.04)
I leak ∝ xe−Vth/V0
• linearization does not give accurate prediction of E I leak, σI leak • exact values for Vth Gaussian: EI
leak
=
2 2 leak,nom σ Vth /(2V0 x) I e ,
σI leak =
σ 2V /(V02 x) e th
−1
1/2
E I leak
I leak,nom is leakage current when statistical variation is ignored
Microlithography’06 2/23/06
27
Effects of statistical variation on leakage power Vth ∼ N (V¯th, 0.15V¯th), V¯th = 0.25, V0 = 0.04 x=1
PDF
PSfrag replacements
x=2
x=5
I leak ∝ xe−Vth/V0
Microlithography’06 2/23/06
28
Statistical variation in leakage power 1.7
E I leak /I leak,nom
PSfrag replacements
1 1
Microlithography’06 2/23/06
2
3 scale factor
4
5
29
Digital Circuit Sizing: Optimization
Basic gate scaling problem (no statistical variation) minimize D subject to P ≤ P max, A ≤ Amax 1 ≤ xi, i = 1, . . . , n a geometric program (GP); can be solved efficiently extensions/variations: • minimize area, power, or some combination
• maximize clock frequency subject to area, power limits
• add other constraints
• optimal trade-off of area, power, delay
Microlithography’06 2/23/06
30
Statistical parameter variation • now model gate delay & power as random variables • circuit performance measures P , D become random variables P, D • distributions of P, D depend on gate scalings xi can estimate PDFs of P, D via Monte Carlo
frequency
• for fixed design, PSfrag replacements
45
Microlithography’06 2/23/06
cycle time D
53
31
Statistical design • measure random performance measures by 95% quantile (say) minimize Q.95(D) A ≤ Amax subject to Q.95(P) ≤ P max, 1 ≤ xi, i = 1, . . . , n • extremely difficult stochastic optimization problem; almost no analytic/exact results • but, simple heuristic method works well
Microlithography’06 2/23/06
32
The New Method
Statistical power constraint • total power is sum of gate powers EP =
n X
E Pi
i=1
• if n is large and P1, . . . , Pm are independent (enough), P≈
n X
E Pi
i=1
• can use E P ≤ P max as reasonable approximation of Q.95(P) ≤ P max Microlithography’06 2/23/06
33
Surrogate gate delay • define surrogate gate delays PSfrag replacements
˜ i(x) = Di(x) + κiσi(x) D
κiσi(x) is margin on gate delay (κi is typically 2)
gate delay
µ + κσ µ
scale factor
• gives more margin to smaller gates Microlithography’06 2/23/06
34
Interpretation of gate delay margins • margins κiσi(x) take statistical gate delay variation into account • κi related to Prob (Di ≤ µi + κiσi) – Chebyshev inequality: κ2i Prob (Di ≤ µi + κiσi) ≥ 1 + κ2i – if Di is Gaussian 1 Prob (Di ≤ µi + κiσi) = √ 2π
Microlithography’06 2/23/06
Z
∞
e
−t2 /2
dt
κi
35
Heuristic for statistical design
• use modified (leakage) power model taking into account statistical variation ˜ i(x) = Di(x) + κiσi(x) • use surrogate gate delays D • now solve resulting (deterministic) gate scaling problem • verify statistical performance via Monte Carlo analysis (can update κi’s and repeat)
Microlithography’06 2/23/06
36
Digital Circuit Sizing Example
Statistically robust design via new method
distribution of cycle time
samereplacements circuit, uncertainty PSfrag
model, and constraints
robust design
nominal optimal design
46
Microlithography’06 2/23/06
47
48
50 49 cycle time
51
52
53
37
path delay std. dev.
Path delay mean/std. dev. scatter plots 3
path delay std. dev.
PSfrag replacements 0 10
3
0 10
Microlithography’06 2/23/06
nominal optimal design
mean path delay
50
robust design
mean path delay
50
38
PSfrag replacements
Comparison of nominal optimal and robust designs
# of gates
400 nominal optimal design
0 1
2
8
16
32
4 8 scale factor
16
32
4
# of gates
400 robust design
0 1
Microlithography’06 2/23/06
2
39
Comparison of nominal optimal and robust designs PSfrag replacements
scale factor (robust design)
32 16 8 4 2 1
4 2 16 1 8 scale factor (nominal optimal design)
Microlithography’06 2/23/06
32
40
Effect of margin coefficients
95% cycle time
PSfrag replacements
52
50
48
46 0
1
2
3
4
5
κ
Microlithography’06 2/23/06
41
Sensitivity to model assumptions
question: how sensitive is robust design to our model of process variation? • distribution shape
• correlation between gates
• Pelgrom model of variance vs. scale factor
answer: not very
Microlithography’06 2/23/06
42
PSfrag replacements
Simulation with uniform gate delay distributions distribution of cycle time
robust design
nominal optimal design
46
47
48
49 50 cycle time
51
52
53
compared with Gaussian gate delays: nominal optimal design not quite as bad; robust design still quite good
Microlithography’06 2/23/06
43
Simulation with correlated gate delays
PSfrag replacements
connected gates have delays that are 30% correlated
distribution of cycle time
robust design
nominal optimal design
46
47
48
49 50 cycle time
51
52
53
nominal optimal not as bad; but robust design still quite good Microlithography’06 2/23/06
44
Conclusions and Future Work
Conclusions
• statistically robust design is subtle; cannot be done by hand • exact or direct methods will not work well – computationally intractable – depend on details of statistical models • heuristic method is relatively simple, scales well, gives good designs – reduces problem to a deterministic one
Microlithography’06 2/23/06
45
References • Boyd, Kim, and Mohan, DATE Tutorial 2005 Geometric programming and its applications to EDA problems • Boyd, Kim, Patil, and Horowitz, SPIE ML 2006 A heuristic method for statistical digital circuit sizing • Kim, Boyd, Patil, and Horowitz, Optimization and Engineering, 2006 A heuristic for optimizing stochastic activity networks with applications to statistical digital circuit sizing • Boyd, Kim, Patil, and Horowitz, Operations Research, 2005 Digital circuit optimization via geometric programming • Patil, Yun, Kim, Cheung, Horowitz, and Boyd, ISQED 2005 A new method for design of robust digital circuits all available from www.stanford.edu/∼boyd/research.html
Microlithography’06 2/23/06
46
References (continued)
• Mani, Devgan, Orshansky, DAC 2005 An efficient algorithm for statistical minimization of total power under timing yield constraints • Satish, Ravindran, Moskewicz, Chinnery, and Keutzer, UCB tech. report, 2005 Evaluating the effectiveness of statistical gate sizing for power optimization • Bhardwaj and Vrudhula, DAC 2005 Leakage minimization of nano-scale circuits in the presence of systematic and random variations
Microlithography’06 2/23/06
47
Seung-Jean Kim Mark Horowitz
Microlithography’06 2/23/06
Dinesh Patil
Statistical variation in digital circuits
• growing in importance as devices shrink • modeling still open – many sources: environmental, process parameter variation, lithography – intrachip, interchip variation – distributions, correlations not well known, change as process matures
Microlithography’06 2/23/06
1
Statistical digital circuit sizing
• standard design approaches: margining, guardbanding, design over corners • statistical design explicitly takes statistical variation into account (combines circuit design with design for manufacturing, yield optimization, design centering, . . . ) • statistical design is very hard problem (even for small circuits) • this talk: a (relatively) simple heuristic method for statistical design that appears to work well
Microlithography’06 2/23/06
2
Outline
• A quick example • Digital circuit sizing: models and optimization • New method for statistical digital circuit sizing • Digital circuit sizing example • Conclusions and future work
Microlithography’06 2/23/06
3
A Quick Example
Example: Ladner-Fisher 32-bit adder
• 64 inputs, 33 outputs, 451 gates, 3214 paths, max depth 8 • simplified RC delay model • design variables: 451 scale factors for gates • cycle time Tcycle is max path delay • minimize cycle time subject to limits on area, min/max scale factor
Microlithography’06 2/23/06
4
Optimization results (no statistical variation) path delays with optimized PSfrag replacements
& uniform scale factors (same total area)
# of paths
4000
2000
0 0
Microlithography’06 2/23/06
optimal
20
uniform
40 60 path delay
80
100
5
Statistical variation in gate delay PSfrag replacements
• simple Pelgrom model; larger gates have less (relative) variation in delay • min sized gate has 10% variation
probability
x=5
x=2 x=1 1
Microlithography’06 2/23/06
2
3
4 delay
5
6
7
6
Effects of statistical variation on nominal optimal design Tcycle PDF estimated via Monte Carlo PSfrag replacements
Q.95 (Tcycle )
cycle time PDF
nominal Tcycle
45
Microlithography’06 2/23/06
47
49 51 cycle time
53
55
7
Why isn’t Tcycle PDF centered around nominal value?
• Tcycle is max of 3214 random path delays • max of RVs behaves differently from sum of RVs – in sum, negative and positive deviations tend to cancel out; PDF is centered, has smaller relative variation – in max, large deviation of any leads to large value; PDF is shifted, skewed to right, has large relative deviation
Microlithography’06 2/23/06
8
PSfrag replacements
PDF of sum of random variables i=1 Xi ,
Xi ∼ N (1, 0.1) independent
Z=
PM
M =1 1
0.5
1.5 M = 10
10
5
15 M = 100
50
Microlithography’06 2/23/06
100
150
9
PSfrag replacements
PDF of max of random variables Z = max{X1, . . . , XM }, Xi ∼ N (1, 0.1) independent PDF
M =1
M = 10
M = 100
0.5
Microlithography’06 2/23/06
1
1.5
10
Simple worst-case design
• use slow model for all gates, e.g., 1.2Di • gives same design • can we do better?
Microlithography’06 2/23/06
11
Statistically robust design via new method
distribution of cycle time
samereplacements circuit, uncertainty PSfrag
model, and constraints
robust design
nominal optimal design
46
Microlithography’06 2/23/06
47
48
50 49 cycle time
51
52
53
12
Statistically robust design via new method
nominal optimal robust
nominal delay 45.9 46.5
ED 49.4 47.6
σD 0.91 0.29
Q.95(D) 51.1 48.1
• same circuit, uncertainty model, and constraints • compared to nominal optimal design, some gates are upsized, others are downsized
Microlithography’06 2/23/06
13
Nominal vs. statistical robust designs 4000
# of paths
PSfrag replacements
2000
0 0
20
40
60
path delay
Microlithography’06 2/23/06
14
path delay std. dev.
Path delay mean/std. dev. scatter plots 3
path delay std. dev.
PSfrag replacements 0 10
3
0 10
Microlithography’06 2/23/06
nominal optimal design
mean path delay
50
robust design
mean path delay
50
15
Area/delay trade-off analysis 15000 PSfrag replacements
Amax
11000
7000
robust design
nominal optimal design
3000 45
Microlithography’06 2/23/06
55 nominal cycle time
65
16
Area/delay trade-off analysis 15000 PSfrag replacements
Amax
11000
robust design
nominal optimal design
7000
3000 45
Microlithography’06 2/23/06
55 95% cycle time
65
17
Digital Circuit Sizing: Models
RA RBinput flip flops RC
Gate scaling combinational logic block
1 4
in
CX CY
output flip flops
6 out
2 5
7
3
clock
• combinational logic; circuit topology & gate types given • gate sizes (scale factors xi ≥ 1) to be determined • scale factors affect total circuit area, power and delay Microlithography’06 2/23/06
18
PSfrag replacements Ri
RC gate delay model Vdd Ciin Ciin
Ri Ciint
CiL
• input & intrinsic capacitances, driving resistance, load capacitance Ciin
= C¯iinxi,
Ciint
= C¯iintxi,
¯ i/xi, Ri = R
CiL
=
X
Cjin
j∈FO(i)
• RC gate delay:
Microlithography’06 2/23/06
Di = 0.69Ri(CiL + Ciint) 19
Path and circuit delay 1 PSfrag replacements
4
6
5
7
2
3
• delay of a path: sum of delays of gates on path • circuit delay (cycle time): maximum delay over all paths
Microlithography’06 2/23/06
20
Area & power
• total circuit area: A = x1A¯1 + · · · + xnA¯n • total power is P = Pdyn + Pstat – dynamic power Pdyn =
n X
2 fi(CiL + Ciint)Vdd
i=1
fi is gate switching frequency – static (leakage) power Pstat =
n X
IileakVdd
i=1
Iileak is leakage current (average over input states)
Microlithography’06 2/23/06
21
Parameters used in example • model parameters: gate type INV NAND2 NOR2 AOI21 OAI21
C¯ in 3 4 5 6 6
C¯ int 3 6 6 7 7
¯ R 0.48 0.48 0.48 0.48 0.48
A¯ 3 8 10 17 16
• time unit is τ , delay of min-size inverter (0.69 · 0.48 · 3 = 1) • area (total width) unit is width of NMOS in min-size inverter
Microlithography’06 2/23/06
22
Statistical variation in threshold voltage
• we focus on statistical variation in threshold voltage Vth (can also model variations in other parameters, e.g., tox, Leff , . . . ) • Pelgrom model:
¯Vth x−1/2 σVth = σ
where σ 2Vth is Vth variance for unit scaled gate • larger gates have less Vth variation
Microlithography’06 2/23/06
23
Statistical gate delay model • alpha-power law model: Vdd D∝ (Vdd − Vth)α (α ≈ 1.3) • for small variation in Vth, ∂D −0.5 σV = α(Vdd − Vth)−1σ ¯ x D σD ≈ V th th ∂Vth
• gate scaling affects mean delay and relative variation differently • relative variation decreases as gate scale factor increases: σD /D ∝ x−0.5 Microlithography’06 2/23/06
24
Statistical variation in gate delay PSfrag replacements
10% relative variation for min sized gate (σD /D = 0.1) inverter driving CL = 4
probability
x=5
x=2 x=1 1
Microlithography’06 2/23/06
2
3
4 delay
5
6
7
25
Statistical variation in gate delay inverter driving CL = 4
PSfrag replacements
10τ
delay
µ + 3σ µ
5τ
µ − 3σ
0
Microlithography’06 2/23/06
1
2
3 scale factor
4
5
26
Statistical leakage power model • leakage current (V0 ≈ 0.04)
I leak ∝ xe−Vth/V0
• linearization does not give accurate prediction of E I leak, σI leak • exact values for Vth Gaussian: EI
leak
=
2 2 leak,nom σ Vth /(2V0 x) I e ,
σI leak =
σ 2V /(V02 x) e th
−1
1/2
E I leak
I leak,nom is leakage current when statistical variation is ignored
Microlithography’06 2/23/06
27
Effects of statistical variation on leakage power Vth ∼ N (V¯th, 0.15V¯th), V¯th = 0.25, V0 = 0.04 x=1
PSfrag replacements
x=2
x=5
I leak ∝ xe−Vth/V0
Microlithography’06 2/23/06
28
Statistical variation in leakage power 1.7
E I leak /I leak,nom
PSfrag replacements
1 1
Microlithography’06 2/23/06
2
3 scale factor
4
5
29
Digital Circuit Sizing: Optimization
Basic gate scaling problem (no statistical variation) minimize D subject to P ≤ P max, A ≤ Amax 1 ≤ xi, i = 1, . . . , n a geometric program (GP); can be solved efficiently extensions/variations: • minimize area, power, or some combination
• maximize clock frequency subject to area, power limits
• add other constraints
• optimal trade-off of area, power, delay
Microlithography’06 2/23/06
30
Statistical parameter variation • now model gate delay & power as random variables • circuit performance measures P , D become random variables P, D • distributions of P, D depend on gate scalings xi can estimate PDFs of P, D via Monte Carlo
frequency
• for fixed design, PSfrag replacements
45
Microlithography’06 2/23/06
cycle time D
53
31
Statistical design • measure random performance measures by 95% quantile (say) minimize Q.95(D) A ≤ Amax subject to Q.95(P) ≤ P max, 1 ≤ xi, i = 1, . . . , n • extremely difficult stochastic optimization problem; almost no analytic/exact results • but, simple heuristic method works well
Microlithography’06 2/23/06
32
The New Method
Statistical power constraint • total power is sum of gate powers EP =
n X
E Pi
i=1
• if n is large and P1, . . . , Pm are independent (enough), P≈
n X
E Pi
i=1
• can use E P ≤ P max as reasonable approximation of Q.95(P) ≤ P max Microlithography’06 2/23/06
33
Surrogate gate delay • define surrogate gate delays PSfrag replacements
˜ i(x) = Di(x) + κiσi(x) D
κiσi(x) is margin on gate delay (κi is typically 2)
gate delay
µ + κσ µ
scale factor
• gives more margin to smaller gates Microlithography’06 2/23/06
34
Interpretation of gate delay margins • margins κiσi(x) take statistical gate delay variation into account • κi related to Prob (Di ≤ µi + κiσi) – Chebyshev inequality: κ2i Prob (Di ≤ µi + κiσi) ≥ 1 + κ2i – if Di is Gaussian 1 Prob (Di ≤ µi + κiσi) = √ 2π
Microlithography’06 2/23/06
Z
∞
e
−t2 /2
dt
κi
35
Heuristic for statistical design
• use modified (leakage) power model taking into account statistical variation ˜ i(x) = Di(x) + κiσi(x) • use surrogate gate delays D • now solve resulting (deterministic) gate scaling problem • verify statistical performance via Monte Carlo analysis (can update κi’s and repeat)
Microlithography’06 2/23/06
36
Digital Circuit Sizing Example
Statistically robust design via new method
distribution of cycle time
samereplacements circuit, uncertainty PSfrag
model, and constraints
robust design
nominal optimal design
46
Microlithography’06 2/23/06
47
48
50 49 cycle time
51
52
53
37
path delay std. dev.
Path delay mean/std. dev. scatter plots 3
path delay std. dev.
PSfrag replacements 0 10
3
0 10
Microlithography’06 2/23/06
nominal optimal design
mean path delay
50
robust design
mean path delay
50
38
PSfrag replacements
Comparison of nominal optimal and robust designs
# of gates
400 nominal optimal design
0 1
2
8
16
32
4 8 scale factor
16
32
4
# of gates
400 robust design
0 1
Microlithography’06 2/23/06
2
39
Comparison of nominal optimal and robust designs PSfrag replacements
scale factor (robust design)
32 16 8 4 2 1
4 2 16 1 8 scale factor (nominal optimal design)
Microlithography’06 2/23/06
32
40
Effect of margin coefficients
95% cycle time
PSfrag replacements
52
50
48
46 0
1
2
3
4
5
κ
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Sensitivity to model assumptions
question: how sensitive is robust design to our model of process variation? • distribution shape
• correlation between gates
• Pelgrom model of variance vs. scale factor
answer: not very
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PSfrag replacements
Simulation with uniform gate delay distributions distribution of cycle time
robust design
nominal optimal design
46
47
48
49 50 cycle time
51
52
53
compared with Gaussian gate delays: nominal optimal design not quite as bad; robust design still quite good
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Simulation with correlated gate delays
PSfrag replacements
connected gates have delays that are 30% correlated
distribution of cycle time
robust design
nominal optimal design
46
47
48
49 50 cycle time
51
52
53
nominal optimal not as bad; but robust design still quite good Microlithography’06 2/23/06
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Conclusions and Future Work
Conclusions
• statistically robust design is subtle; cannot be done by hand • exact or direct methods will not work well – computationally intractable – depend on details of statistical models • heuristic method is relatively simple, scales well, gives good designs – reduces problem to a deterministic one
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References • Boyd, Kim, and Mohan, DATE Tutorial 2005 Geometric programming and its applications to EDA problems • Boyd, Kim, Patil, and Horowitz, SPIE ML 2006 A heuristic method for statistical digital circuit sizing • Kim, Boyd, Patil, and Horowitz, Optimization and Engineering, 2006 A heuristic for optimizing stochastic activity networks with applications to statistical digital circuit sizing • Boyd, Kim, Patil, and Horowitz, Operations Research, 2005 Digital circuit optimization via geometric programming • Patil, Yun, Kim, Cheung, Horowitz, and Boyd, ISQED 2005 A new method for design of robust digital circuits all available from www.stanford.edu/∼boyd/research.html
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References (continued)
• Mani, Devgan, Orshansky, DAC 2005 An efficient algorithm for statistical minimization of total power under timing yield constraints • Satish, Ravindran, Moskewicz, Chinnery, and Keutzer, UCB tech. report, 2005 Evaluating the effectiveness of statistical gate sizing for power optimization • Bhardwaj and Vrudhula, DAC 2005 Leakage minimization of nano-scale circuits in the presence of systematic and random variations
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