a high-speed low-power rail-to-rail buffer amplifier for lcd application
A HIGH-SPEED LOW-POWER RAIL-TO-RAIL BUFFER AMPLIFIER FOR LCD APPLICATION Chih-Wen Lu Department of Electrical Engineering National Chi Nan University Puli, Taiwan, R.O.C. email: [email protected]
Peter H. Xiao New Vision Microelectronics Inc. email: [email protected]
Abstract
Some output buffers were proposed and demonstrated to reduce the power consumption in recent years. For examples, A high-speed low-power rail-to-rail class-B buffer amplifier, which is suitable for liquid crystal display Yu et al [4] proposed a class-B output buffer for flat-panelapplications, is proposed. The summing circuit is biased by the display column driver, for which a comparator was used in the constant current sources to applicable different supply negative feedback path to eliminate the quiescent current in the voltages. The buffer draws little current while static but has a output stage. Weng et al. [5] proposed a compact, low-power, large driving capability while transient. The circuit achieves the large driving capability by employing simple comparators and rail-to-rail class-B output buffer for driving the large to sense the transients of the input to turn on the output stages, column line capacitance of LCDs, where a nonlinear element which are statically off in the stable state. This increases the in feedback path is modified from the current-mirror amplifier speed of the circuit without increasing static power to obtain the area and power advantages. Lu [2] proposed a consumption too much. An experimental prototype output high-speed driving scheme and a compact high-speed lowbuffer implemented in a 0.35-µm CMOS technology demonstrates that the circuit can operate under a wide power power rail-to-rail class-B buffer amplifier, which are suitable supply range. Quiescent currents of 5.4 µA and 7.4 µA are for both of the small- and large-size liquid crystal display measured for power supplies of 3.3 V and 8 V, respectively. applications. This buffer amplifier employs a double cascode The buffer exhibits the settling time of 1.5 µs for a voltage current mirror as the load of the rail-to-rail differential pairs. swing of 0.1 ~ (VDD – 0.1) V under a 600 pF capacitance load. Since the cascode current mirror is a self-bias configuration, it The area of this buffer is 29.3 × 86.3µm 2 . cannot be operated under a wide range of power supply. An LCD driver should applicable to different power supplies [7]. Keywords: Buffer Amplifier, LCD, Column Driver. In this work, a buffer amplifier, which can be operated under a wide range of power supply, is proposed.
1. Introduction
2. Proposed Buffer Amplifier
As Liquid-crystal displays (LCDs) are recently installed in notebook type personal computers and compact desktop personal computers and monitors are becoming larger and higher definition, there is a big demand of developing lowpower dissipation, high resolution, small settling time and high-speed LCD driver [1-6]. An LCD driver is generally composed of column drivers, gate drivers, a timing controller, and a reference source. The column drivers are especially important to achieving high-speed driving, high resolution and low-power dissipation [1-3]. A column driver generally includes registers, data latches, digital-to-analog converters (DAC’s) and output buffers. Among those, the output buffers determine the speed, resolution, voltage swing and power dissipation of the column drivers [2, 5]. Due to the thousands of output buffer amplifiers built into a single chip, the buffer should occupy a small die area, and its static power consumption should be small. The output buffer should offer an almost rail-to-rail voltage driving which can accommodate higher gray levels. Also, the settling time should be smaller than the horizontal scanning time.
1-4244-0038-4 2006 IEEE CCECE/CCGEI, Ottawa, May 2006
Fig. 1 shows the configuration of the proposed rail-to-rail buffer amplifier. The connected points are labeled with the alphabets A ~ H. As a buffer, “output” is connected to the inverting input (in-) and the input signal is applied to the noninverting terminal (in+). The capacitive load is connected to the output. This buffer consists of a bias stage (Mb1~Mb8 and Rb), a rail-to-rail differential amplifier (M1~M8), a current summer (M9~M20), comparators (M21~M24), and the output transistors (M25 and M26). The rail-to-rail differential pairs M3~M4 and M7~M8, which are biased by the constant current sources M1~M2 and M5~M6, are actively loaded by the current summer. The current summer, which is biased by the constant current sources (M9~M12) to applicable different supply voltages, is used to add the currents of the rail-to-rail differential amplifiers and then transfer the current to voltages for the comparators. The comparators are used to amplify the voltage difference of two inputs. Then the outputs of the comparators turn on/off the transistors of the output stages.
60
VDD
2I M1 2I M2
A
A
B
Mb1 Mb2 I
I B
2I M14
M13 E M15
in+
M3 I
Mb3 Mb4
G
I C
I H
M23
M16
in-
M4
M21
F
voltage of M22 is pulled down to a very low level. Similarly, due to the mismatch design, M23 stays in the triode region and M24 goes to the saturation region. The drain voltage of M23 is close to VDD. This makes the output transistors M25 and M26 cut off from the output node and consume no power in the stable state. When the input voltage, in+, is reduced, the currents in M3 and M8 will be increased, but the currents in M4 and M7 will be decreased. The gate voltages of M14 and M20 will be increased and the gate voltages of M21~M24 will be decreased. As a result, M21 will go into the triode region and M22 will go into the saturation region. The drain voltage of M22 will increase to turn on M26. Then M26 starts to discharge the output node. However, M25 is still in the cut off region. When the output voltage reaches the level that the voltage difference between the input and output is almost zero, M26 stops discharging the output node. Since the gate voltages of M26 can reach a value of VDD, M26 can be turned to fully “on” to discharge the output at a maximal speed. Similarly, when the input voltage, in+, is increased, M26 is still cut off from the output, but the gate voltage of M25 is reduced and M25 starts to charge the output load until the output voltage almost equal to the input voltage. The gate voltage of M25 can be pulled down to a very low level, so M25 can charge the output load at a maximal speed.
M25
M10 I M9
D
C
output
Mb5 Mb6 D
E
F
in+
M7
M8
Mb7 Mb8 Rb
A I
I
M11 I M12
in- B
M26 M17
C D
M6 2I M5
M18 G
H
M19
M20 2I
Bias Circuit
Differential Pairs
M22
M24
2I
First-Stage Amplifier
Comparators Output Transistors
Fig. 1 Schematic of the proposed class-B buffer amplifier. In order to obtain a large driving capability during the transient state but draw little current while static, the aspect ratios of the buffer are designed as: W W W W (1) = = 2 = 2 L L L 1 2 b2 L b4 W L W L W L W L
W W W = = 2 = 2 L L 5 6 b5 L b 7 W W W = = = 9 L 10 L b5 L b 7
W W W = = = 11 L 12 L b2 L b 4 W W W = = 2 = 2 13 L 14 L 15 L 16 W W W W = = 2 = 2 L 19 L 20 L 17 L 18 1 W 1 W W W < and > L 21 2 L 14 L 22 2 L 20 1 W 1 W W W > and < L 23 2 L 14 L 24 2 L 20
(2)
3. Experimental Results
(3)
The proposed output buffer amplifier was fabricated using a 0.35-µm CMOS technology. The die photograph is shown in Fig. 2. The area of the buffer is only 29.3 × 86.3µm 2 . Quiescent currents of 5.4 µA and 7.4 µA are measured for power supplies of 3.3 V and 8 V, respectively. Fig. 3 (a) and (b) show the measured results of the output with the input of a large dynamic range of a 20 KHz triangular wave of the proposed buffer amplifier loaded with a large size capacitor of 600 pF for power supplies of 3.3 V and 8 V, respectively. The upper traces are the input waveforms and the lower ones are the measured output waveforms. They can be seen that the outputs basically follow the inputs. Fig. 4 (a) and (b) show the step responses of the same buffer loaded with a capacitance of 600 pF with the voltage swings of 3.1 V and 7.8 V for power supplies of 3.3 V and 8 V, respectively. The upper traces are the input waveform and the lower ones are the measured output waveforms. The settling times for the output to settle to within ±5 mV of the final voltage are only 1.5 µs for both the supply voltages of 3.3 V and 8 V. The performance of the proposed buffer is summarized in Table 1. Compared with the previous buffers, the proposed circuit is superior in supply voltage range, input/output voltage range, area, quiescent power consumption and settling time.
(4) (5) (6) (7) (8)
In the stable state, the output voltage is equal to the input voltage. The currents flowing in all transistors of the differential pairs are I where I is the current flowing in the bias stage. The currents flowing in the constant current sources of M9~M12 are also I. Then the currents flowing in M13~M14 and M19~M20 have twice the current in the bias stage, i.e., 2I. Since M13~M20 are two cascode current mirrors, the drain voltage of M14 is equal to that of M13 and the drain voltage of M20 is equal to that of M19. The currents flowing in the current mirrors are mirrored to the comparators. The aspect ratio of M21 is designed to be smaller than half that of M14 and the W/L of M22 is larger than half that of M20, this causes M21 to be in the saturation region but M22 to go out of the saturation region and be in the triode region. Then the drain
4. Conclusions In this work, a high-speed low-power rail-to-rail class-B buffer amplifier, which is suitable for LCD applications, is
61
proposed. An experimental prototype output buffer implemented in a 0.35-µm CMOS technology demonstrates that the circuit can operate under a wide power supply range. Quiescent currents of 5.4 µA and 7.4 µA are measured for power supplies of 3.3 V and 8 V, respectively. The buffer exhibits the settling time of 1.5 µs for a voltage swing of 0.1 ~ (VDD – 0.1) V under a 600 pF capacitance load. The area of this buffer is 29.3 × 86.3µm 2 . Compared with the previous buffers, the performance of the proposed circuit is superior in supply voltage range, input/output voltage range, area, quiescent power consumption and settling time. The measured data do show that the proposed output buffer circuit is very suitable for LCD applications.
(b) Fig. 3 The measured results of the output with the input of a large dynamic range of a 20 KHz triangular wave of the proposed buffer amplifier loaded with a large size capacitor of 600 pF for power supplies of (a) 3.3 V and (b) 8 V, respectively.
Fig. 2 Die photograph of the proposed buffer amplifier.
(a)
(a)
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With Power Control Based on the Number of Colors Selected,” IEEE Journal of Solid-State Circuits, Vol. 38, No.3, March, pp. 503-510, 2003. [4] Pang-Cheng Yu and Jiin-Chuan Wu, “A Class-B Output Buffer for Flat-Panel-Display Column Driver,” IEEE Journal of Solid-State Circuits, Vol. 34, No.1, Jan. pp. 116-119, 1999. [5] Ming-Chan Weng and Jiin-Chuan Wu, “A Compact LowPower Rail-to-Rail Class-B Buffer for LCD Column Driver,” IEICE Trans. Electron., Vol. E85-C, No. 8 August, pp. 1659-1663, 2002. [6] Tetsuro Itakura and Hironori Minamizaki, “A Two-GainStage Amplifier without an On-Chip Miller Capacitor in an LCD Driver IC,” IEICE Trans. Fundamentals, Vol. E85-A, No. 8 August, pp. 1913-1920, 2002. [7] TFT-LCD source drivers NT39360, NT3982, and NT3994. Novatek [Online] Available: http://www.novatek.com.tw/.
(b) Fig. 4 The step responses of the proposed buffer loaded with a capacitance of 600 pF with the voltage swings of 3.1 V and 7.8 V for power supplies of (a) 3.3 V and (b) 8 V, respectively. Table 1 Performance Summary. This work
Weng’s Yu’s buffer Lu’s buffer [5] [4] buffer [2] Process 0.35 µm 0.35 µm 0.8 µm 0.35 µm technology CMOS CMOS CMOS CMOS VDD (V) 3.3 ~ 8 3.3 5 3.3 Input/ouput 0.1 ~ 0.05 ~ 1~5 0 ~ 3.3 range (V) (VDD – 0.1) 3.25 (80% of (100% of (100% of (97% of VDD) VDD) VDD) VDD) Quiescent 5.4 (VDD = 7.4 24 7 current 3.3 V) 7.4 (VDD = (µA) 8 V) Settling 1.5 for CL = 8 for CL = 8 for CL = 2.4 (rise) 600 pF 600 pF 2.3 (fall) time (µs) 600 pF for CL = 600 pF Active area 29.3 × 86.3 86 × 73.5 230 × 140 46.5 × 57 (µm2)
References [1] Chih-Wen Lu and Chung Len Lee, “A Low Power High Speed Class-AB Buffer Amplifier for Flat Panel Display Application,” IEEE Transactions on VLSI Systems, Vol 10, No. 2, pp. 163-168, April 2002. [2] Chih-Wen Lu, “High-Speed Driving Scheme and Compact High-Speed Low-Power Rail-to-Rail Class-B Buffer Amplifier for LCD Applications,” IEEE Journal of SolidState Circuits, vol. 39, pp. 1938-1947, November, 2004. [3] Tetsuro Itaku, Hironori Minamizaki, Tetsuya Satio, and Tadashi Kuroda, “A 402-Output TFT-LCD Driver IC
63
Peter H. Xiao New Vision Microelectronics Inc. email: [email protected]
Abstract
Some output buffers were proposed and demonstrated to reduce the power consumption in recent years. For examples, A high-speed low-power rail-to-rail class-B buffer amplifier, which is suitable for liquid crystal display Yu et al [4] proposed a class-B output buffer for flat-panelapplications, is proposed. The summing circuit is biased by the display column driver, for which a comparator was used in the constant current sources to applicable different supply negative feedback path to eliminate the quiescent current in the voltages. The buffer draws little current while static but has a output stage. Weng et al. [5] proposed a compact, low-power, large driving capability while transient. The circuit achieves the large driving capability by employing simple comparators and rail-to-rail class-B output buffer for driving the large to sense the transients of the input to turn on the output stages, column line capacitance of LCDs, where a nonlinear element which are statically off in the stable state. This increases the in feedback path is modified from the current-mirror amplifier speed of the circuit without increasing static power to obtain the area and power advantages. Lu [2] proposed a consumption too much. An experimental prototype output high-speed driving scheme and a compact high-speed lowbuffer implemented in a 0.35-µm CMOS technology demonstrates that the circuit can operate under a wide power power rail-to-rail class-B buffer amplifier, which are suitable supply range. Quiescent currents of 5.4 µA and 7.4 µA are for both of the small- and large-size liquid crystal display measured for power supplies of 3.3 V and 8 V, respectively. applications. This buffer amplifier employs a double cascode The buffer exhibits the settling time of 1.5 µs for a voltage current mirror as the load of the rail-to-rail differential pairs. swing of 0.1 ~ (VDD – 0.1) V under a 600 pF capacitance load. Since the cascode current mirror is a self-bias configuration, it The area of this buffer is 29.3 × 86.3µm 2 . cannot be operated under a wide range of power supply. An LCD driver should applicable to different power supplies [7]. Keywords: Buffer Amplifier, LCD, Column Driver. In this work, a buffer amplifier, which can be operated under a wide range of power supply, is proposed.
1. Introduction
2. Proposed Buffer Amplifier
As Liquid-crystal displays (LCDs) are recently installed in notebook type personal computers and compact desktop personal computers and monitors are becoming larger and higher definition, there is a big demand of developing lowpower dissipation, high resolution, small settling time and high-speed LCD driver [1-6]. An LCD driver is generally composed of column drivers, gate drivers, a timing controller, and a reference source. The column drivers are especially important to achieving high-speed driving, high resolution and low-power dissipation [1-3]. A column driver generally includes registers, data latches, digital-to-analog converters (DAC’s) and output buffers. Among those, the output buffers determine the speed, resolution, voltage swing and power dissipation of the column drivers [2, 5]. Due to the thousands of output buffer amplifiers built into a single chip, the buffer should occupy a small die area, and its static power consumption should be small. The output buffer should offer an almost rail-to-rail voltage driving which can accommodate higher gray levels. Also, the settling time should be smaller than the horizontal scanning time.
1-4244-0038-4 2006 IEEE CCECE/CCGEI, Ottawa, May 2006
Fig. 1 shows the configuration of the proposed rail-to-rail buffer amplifier. The connected points are labeled with the alphabets A ~ H. As a buffer, “output” is connected to the inverting input (in-) and the input signal is applied to the noninverting terminal (in+). The capacitive load is connected to the output. This buffer consists of a bias stage (Mb1~Mb8 and Rb), a rail-to-rail differential amplifier (M1~M8), a current summer (M9~M20), comparators (M21~M24), and the output transistors (M25 and M26). The rail-to-rail differential pairs M3~M4 and M7~M8, which are biased by the constant current sources M1~M2 and M5~M6, are actively loaded by the current summer. The current summer, which is biased by the constant current sources (M9~M12) to applicable different supply voltages, is used to add the currents of the rail-to-rail differential amplifiers and then transfer the current to voltages for the comparators. The comparators are used to amplify the voltage difference of two inputs. Then the outputs of the comparators turn on/off the transistors of the output stages.
60
VDD
2I M1 2I M2
A
A
B
Mb1 Mb2 I
I B
2I M14
M13 E M15
in+
M3 I
Mb3 Mb4
G
I C
I H
M23
M16
in-
M4
M21
F
voltage of M22 is pulled down to a very low level. Similarly, due to the mismatch design, M23 stays in the triode region and M24 goes to the saturation region. The drain voltage of M23 is close to VDD. This makes the output transistors M25 and M26 cut off from the output node and consume no power in the stable state. When the input voltage, in+, is reduced, the currents in M3 and M8 will be increased, but the currents in M4 and M7 will be decreased. The gate voltages of M14 and M20 will be increased and the gate voltages of M21~M24 will be decreased. As a result, M21 will go into the triode region and M22 will go into the saturation region. The drain voltage of M22 will increase to turn on M26. Then M26 starts to discharge the output node. However, M25 is still in the cut off region. When the output voltage reaches the level that the voltage difference between the input and output is almost zero, M26 stops discharging the output node. Since the gate voltages of M26 can reach a value of VDD, M26 can be turned to fully “on” to discharge the output at a maximal speed. Similarly, when the input voltage, in+, is increased, M26 is still cut off from the output, but the gate voltage of M25 is reduced and M25 starts to charge the output load until the output voltage almost equal to the input voltage. The gate voltage of M25 can be pulled down to a very low level, so M25 can charge the output load at a maximal speed.
M25
M10 I M9
D
C
output
Mb5 Mb6 D
E
F
in+
M7
M8
Mb7 Mb8 Rb
A I
I
M11 I M12
in- B
M26 M17
C D
M6 2I M5
M18 G
H
M19
M20 2I
Bias Circuit
Differential Pairs
M22
M24
2I
First-Stage Amplifier
Comparators Output Transistors
Fig. 1 Schematic of the proposed class-B buffer amplifier. In order to obtain a large driving capability during the transient state but draw little current while static, the aspect ratios of the buffer are designed as: W W W W (1) = = 2 = 2 L L L 1 2 b2 L b4 W L W L W L W L
W W W = = 2 = 2 L L 5 6 b5 L b 7 W W W = = = 9 L 10 L b5 L b 7
W W W = = = 11 L 12 L b2 L b 4 W W W = = 2 = 2 13 L 14 L 15 L 16 W W W W = = 2 = 2 L 19 L 20 L 17 L 18 1 W 1 W W W < and > L 21 2 L 14 L 22 2 L 20 1 W 1 W W W > and < L 23 2 L 14 L 24 2 L 20
(2)
3. Experimental Results
(3)
The proposed output buffer amplifier was fabricated using a 0.35-µm CMOS technology. The die photograph is shown in Fig. 2. The area of the buffer is only 29.3 × 86.3µm 2 . Quiescent currents of 5.4 µA and 7.4 µA are measured for power supplies of 3.3 V and 8 V, respectively. Fig. 3 (a) and (b) show the measured results of the output with the input of a large dynamic range of a 20 KHz triangular wave of the proposed buffer amplifier loaded with a large size capacitor of 600 pF for power supplies of 3.3 V and 8 V, respectively. The upper traces are the input waveforms and the lower ones are the measured output waveforms. They can be seen that the outputs basically follow the inputs. Fig. 4 (a) and (b) show the step responses of the same buffer loaded with a capacitance of 600 pF with the voltage swings of 3.1 V and 7.8 V for power supplies of 3.3 V and 8 V, respectively. The upper traces are the input waveform and the lower ones are the measured output waveforms. The settling times for the output to settle to within ±5 mV of the final voltage are only 1.5 µs for both the supply voltages of 3.3 V and 8 V. The performance of the proposed buffer is summarized in Table 1. Compared with the previous buffers, the proposed circuit is superior in supply voltage range, input/output voltage range, area, quiescent power consumption and settling time.
(4) (5) (6) (7) (8)
In the stable state, the output voltage is equal to the input voltage. The currents flowing in all transistors of the differential pairs are I where I is the current flowing in the bias stage. The currents flowing in the constant current sources of M9~M12 are also I. Then the currents flowing in M13~M14 and M19~M20 have twice the current in the bias stage, i.e., 2I. Since M13~M20 are two cascode current mirrors, the drain voltage of M14 is equal to that of M13 and the drain voltage of M20 is equal to that of M19. The currents flowing in the current mirrors are mirrored to the comparators. The aspect ratio of M21 is designed to be smaller than half that of M14 and the W/L of M22 is larger than half that of M20, this causes M21 to be in the saturation region but M22 to go out of the saturation region and be in the triode region. Then the drain
4. Conclusions In this work, a high-speed low-power rail-to-rail class-B buffer amplifier, which is suitable for LCD applications, is
61
proposed. An experimental prototype output buffer implemented in a 0.35-µm CMOS technology demonstrates that the circuit can operate under a wide power supply range. Quiescent currents of 5.4 µA and 7.4 µA are measured for power supplies of 3.3 V and 8 V, respectively. The buffer exhibits the settling time of 1.5 µs for a voltage swing of 0.1 ~ (VDD – 0.1) V under a 600 pF capacitance load. The area of this buffer is 29.3 × 86.3µm 2 . Compared with the previous buffers, the performance of the proposed circuit is superior in supply voltage range, input/output voltage range, area, quiescent power consumption and settling time. The measured data do show that the proposed output buffer circuit is very suitable for LCD applications.
(b) Fig. 3 The measured results of the output with the input of a large dynamic range of a 20 KHz triangular wave of the proposed buffer amplifier loaded with a large size capacitor of 600 pF for power supplies of (a) 3.3 V and (b) 8 V, respectively.
Fig. 2 Die photograph of the proposed buffer amplifier.
(a)
(a)
62
With Power Control Based on the Number of Colors Selected,” IEEE Journal of Solid-State Circuits, Vol. 38, No.3, March, pp. 503-510, 2003. [4] Pang-Cheng Yu and Jiin-Chuan Wu, “A Class-B Output Buffer for Flat-Panel-Display Column Driver,” IEEE Journal of Solid-State Circuits, Vol. 34, No.1, Jan. pp. 116-119, 1999. [5] Ming-Chan Weng and Jiin-Chuan Wu, “A Compact LowPower Rail-to-Rail Class-B Buffer for LCD Column Driver,” IEICE Trans. Electron., Vol. E85-C, No. 8 August, pp. 1659-1663, 2002. [6] Tetsuro Itakura and Hironori Minamizaki, “A Two-GainStage Amplifier without an On-Chip Miller Capacitor in an LCD Driver IC,” IEICE Trans. Fundamentals, Vol. E85-A, No. 8 August, pp. 1913-1920, 2002. [7] TFT-LCD source drivers NT39360, NT3982, and NT3994. Novatek [Online] Available: http://www.novatek.com.tw/.
(b) Fig. 4 The step responses of the proposed buffer loaded with a capacitance of 600 pF with the voltage swings of 3.1 V and 7.8 V for power supplies of (a) 3.3 V and (b) 8 V, respectively. Table 1 Performance Summary. This work
Weng’s Yu’s buffer Lu’s buffer [5] [4] buffer [2] Process 0.35 µm 0.35 µm 0.8 µm 0.35 µm technology CMOS CMOS CMOS CMOS VDD (V) 3.3 ~ 8 3.3 5 3.3 Input/ouput 0.1 ~ 0.05 ~ 1~5 0 ~ 3.3 range (V) (VDD – 0.1) 3.25 (80% of (100% of (100% of (97% of VDD) VDD) VDD) VDD) Quiescent 5.4 (VDD = 7.4 24 7 current 3.3 V) 7.4 (VDD = (µA) 8 V) Settling 1.5 for CL = 8 for CL = 8 for CL = 2.4 (rise) 600 pF 600 pF 2.3 (fall) time (µs) 600 pF for CL = 600 pF Active area 29.3 × 86.3 86 × 73.5 230 × 140 46.5 × 57 (µm2)
References [1] Chih-Wen Lu and Chung Len Lee, “A Low Power High Speed Class-AB Buffer Amplifier for Flat Panel Display Application,” IEEE Transactions on VLSI Systems, Vol 10, No. 2, pp. 163-168, April 2002. [2] Chih-Wen Lu, “High-Speed Driving Scheme and Compact High-Speed Low-Power Rail-to-Rail Class-B Buffer Amplifier for LCD Applications,” IEEE Journal of SolidState Circuits, vol. 39, pp. 1938-1947, November, 2004. [3] Tetsuro Itaku, Hironori Minamizaki, Tetsuya Satio, and Tadashi Kuroda, “A 402-Output TFT-LCD Driver IC
63
