A jitter insensitive continuous-time sigma-delta ... - IEEE Xplore
A Jitter Insensitive Continuous-Time Σ∆ Modulator Using Transmission Lines L. Hernández1, P. Rombouts2, E. Prefasi1 , S. Paton1, M. Garcia1, C. Lopez1 1Universidad 2 ELIS,
Carlos III de Madrid, Madrid, Spain Ghent University, Gent, Belgium identical properties as a discrete time counterpart [5]. This way a modulator with a large insensitivity toward jitter and excess loop delay is obtained. In this work, di coefficients are chosen such that the CTSD modulator is equivalent to the ideal second-order lowpass discrete time modulator. Mathematically this can be written as:
Abstract This work presents a prototype low pass continuous time sigma delta modulator which uses transmission lines in its loop filter rather than capacitive integrators. As has been shown in prior theoretical work, such a structure allows to desensitize the modulator against clock jitter and excess loop delay. The prototype single-bit modulator was designed for an oversampling ratio of 128. Clocked at 53.7 MHz it achieves a peak SNR of 67 dB. In an experiment with an excessive clock jitter of 1% of the clock period, the SNDR is degraded by only 5dB compared to the case without jitter. This is 15dB better than an equivalent modulator with capacitive integrators.
NTF (z )
2
( (
) )
(2)
NTF (s ) = e d 3 H + d 3 (d 1 + d 2 )H + d 1 d 1 d 3 − 1 This yields the values d1=1 , d2=3 , d3=1/4. Coefficient d3 may be neglected in our single-bit design. − sT
−1
2
fs=1/Ts x(t)
1. Introduction Continuous time sigma delta (CTSD) modulators are nowadays a proven technology for high speed A/D converter implementation [1]. However, CTSD modulators are more sensitive to circuit impairments than switched capacitor implementations. Some of the performance limiting factors of CTSD modulators are clock jitter and excess loop delay [1], [2], [3]. In [4] a delay linear system is proposed to implement the loop filter of a CTSD modulator. This linear system may process a sequence of pulses, such as the feedback DAC signal of the modulator, into another sequence of similar pulses. This property is used in [5] to desensitize the CTSD modulator from jitter and excess loop delay. In this work, we present a CMOS implementation of the modulator proposed in [5]. In this proof-of-concept single-bit modulator, off-chip transmission lines are used to implement the delays. A future design could employ on-chip resonators, such as integrated transmission lines or MEMS devices. The presented work describes the circuit design and the measurements that demonstrate the usefulness of the overall concept.
+
+
H
y(n)
+
H
d3
d2
d1
z-1
Figure 1. System level diagram of a 2nd order modulator implemented with transmission lines.
Now we will focus on the circuit implementation of fig. 1 using transmission lines. A circuit that exactly mimics the behavior of the system of figure 1 is shown in figure 2 [5]. It is implemented with transmission lines, transconductors and a current feedback DAC. Ir z-1 -Ir fs=1/T v1(t)
v(t) gm1= 1/Zo
R1=ZO
v2(t) gm2= 1/Zo
λ/4
2. CTSD modulators with transmission lines Figure 1 shows the system level diagram of the CTSD modulator with transmission lines [5]. The blocks named H implement the following transfer function: 1 + e − sT (1) H (s ) = 1 − e − sT This transfer function is proportional to the impedance of an open circuit transmission line, where T corresponds to the delay of the transmission line. If this delay T is equal to the period of the sampling clock, this diagram can be used to implement a CTSD modulator that has nearly
0-7803-8715-5/04/$20.00 ©2004 IEEE.
= NTF (s ) , NTF (z ) = (1 − z −1 )
z − 1 = e − sT
ZL open
R2=3ZO
y[n]
λ/4
ZL open
Figure 2. Conceptual circuit implementation of a CTSD modulator with transmission lines.
The combination of a transconductor and the transmission line produces the same transfer function as blocks H in fig. 1. The previously defined di coefficients, are implemented by adding series resistors to the transmission lines. The appropriate values of these resistors and the transconductors are expressed in Table I. Here fs corresponds to the sampling frequency, Z0 to
109
the characteristic impedance of the line and ViMAX to the maximum input level. gm1 gm2 R1 R2 Ir λ
any theoretical SNR degradation, if a NRZ feedback pulse is used. 3. Circuit Design The system block diagram and parameters defined in the previous section were used as the start point of a CMOS circuit design. For this proof-of-concept circuit, a conservative 0.6u standard CMOS process and a power supply of 3.3 Volt were selected. A clock frequency of 50 MHz was targeted .
1/Z0 1/Z0 Z0 3Z0 ViMAX/Z0 v/2fs
Table I In [5] it was shown that transconductors require a bandwidth of 2.5fs to ensure that the intersymbol interference between the feedback DAC pulses will produce a noise power below the quantization noise, when moderate jitter is present. Time domain simulations on the state variables of fig. 1 have defined the saturation values for the transconductors. These values are shown in figure 3, considering an ideal transconductor and an open loop gain limited to 120dB at DC to account for transmission line losses.
V1,V2/Vimax
10
V1/Vimax
0 0,3
0,4
0,5
0,6
0,7
0,8
0,9
ESD prot.
digital interface
gm2
sync. latch
clk
A block diagram of the chip is shown on figure 4. It consists of a first input transconductor, a second transconductor, a comparator, a synchronization latch, a 1bit DAC and a digital interface block. Essentially it is a fully differential implementation of the modulator shown on figure 2. The transmission lines and their series resistors are not implemented on-chip. This way, the output of each transconductor is connected to an ESDprotected bond pad. The most demanding building block of the entire circuit is the input transconductor. This block should be at least as linear as the linearity of the overall modulator. The reason for this is that this transconductor performs the voltage-to-current conversion of the input signal prior to entering the feedback loop. Hence, non-linearity of this transconductor is not attenuated by the operation of the loop. For the same reason, this input transconductor does only require the bandwidth of the input signal instead of 2.5 times the sampling frequency, as stated in the previous section, which only applies to transconductor gm2. Figure 5 depicts the simplified schematic of this first transconductor. It is based on source degeneration of the input differential pair transistors similar to what was used in [6]. For enhanced linearity, the operational amplifiers A1 and A2 are added at the inputs. These amplifiers are implemented as simple NMOS differential pairs with active loads. The resistor R is a 1kΩ linear resistor which is available in the target process. This value was a compromise between noise and power consumption. Note that this does not correspond to the value of Table 1. However, as explained above, the first transconductor is outside the loop and hence this deviation from the theory only results in a gain error of the overall modulator. Amplifiers A3-A4 are added to achieve an adequate output impedance [7]. It turned out that the equivalent amplifiers for the NMOS cascodes
15
0,2
ESD prot.
ESD prot.
clk Figure 4. Block diagram of the CMOS chip.
20
0,1
ESD prot.
1bit DAC
V2/Vimax
5
to off-chip transmission line and series resistor
gm1
30
25
to off-chip transmission line and series resistor
1
Vi/Vimax
Figure 3. Dynamic range of the state variables
Using the graph of fig. 3, we may estimate the maximum current provided by transconductor gm2 and its maximum input voltage. For an input tone of –4dBfs, the maximum current delivered by gm2 is 1.74Ir and the maximum amplitude at the transmission line V1(t) is 1.1Vi MAX. We can also note that the value of V2(t) peaks at 9.7ViMAX for the same input level. To compare this value with a standard second order sigma-delta modulator we should multiply V2(t) by d3. To bring this down to a reasonable level, the loop filter must be scaled in this single-bit design. It must be noted that the parameters of the analog components of this design are independent of the sampling clock, as long as the clock frequency has to fit only with the length of the external transmission lines. In the case of a standard CTSD modulator, most of the architecture coefficients are related to the sampling frequency, which forces to define such parameter in the design process. In this case, only the bandwidth requirements of the transconductors and the maximum operating frequency of the sampler and DAC set the bounds for the clock rate. Also, the modulator requires a certain excess loop delay to operate. This excess loop delay may vary between 0 to one full clock cycle without
110
The values of the circuit parameters that have been chosen for the design are in Table III. Z0 50Ω R1 50Ω R2 150Ω Ir 300µA Table III
could be removed. This is due to the fact that relatively long channels were used for these current source transistors, that are outside the main signal path.
Figure 5. Simplified schematic of the first transconductor.
Since the circuit is differential, it requires a common mode feedback to stabilize the output common mode voltage. The circuit [8], shown on figure 6, was used to set the common mode level.
Figure 7. Chip micro photograph
To test the chip, four pieces of RG-178 coaxial cable were used as off chip resonators, trimmed to the clock frequency. The test setup consisted of a PCB board with current references, analog single ended to differential drivers and an interface to a logic analyzer. The modulator was tested by applying sinusoidal signals at its input. Here, typically an input frequency of fs/512 was used. The peak SNR occurs for a -4dBfs input. Using a clock generator with a nominal rms jitter of 0.1% the nominal clock period, a SNR of 67dB was measured for an OSR of 128. For this case the measured SNR has been plotted vs. the input signal level in figure 8, which demonstrates a dynamic range of 69 dB.
Figure 6. Simplified schematic of the first transconductor’s common mode feedback.
The second transconductor (gm2 on fig. 4) is implemented as a simple differential pair without source degeneration nor auxiliary amplifiers. This is possible because nonlinearity of this block is attenuated by the operation of the loop. Due to the simplicity of this block, it also achieves high bandwidth. The comparator is implemented as a simple pre-amplifier to avoid kickback and a two stage regenerative latch. The synchronization latch is strobed slightly after the comparator latch [8]. The digital block groups 8 consecutive output bits in a single 8-bit word to reduce the clock rate of the output digital pads. Also a direct digital output is provided for testing at low clock rates. This block is composed of a shift register, that makes the serial to parallel conversion, a parallel loadable register, that captures every 8-bit word, and a ring counter that controls the block and generates the output signals. A full SPICE transistor-level simulation of the chip predicted a SNR of 72.9 dB for a -4dBfs tone test signal, considering an OSR of 128.
90
SNR(dB)
70 50 30 10 -10 -70
-60
-50
-40
-30
-20
-10
0
dBFs
Figure 8. Measured SNR vs. input signal level.
4. Implementation and measurements A photograph of the prototype chip is shown in figure 7. The lay-out of each block and the final floor planning has been completed taking into consideration the pad routing to minimize the parasitic capacitance at the transmission line connections. The chip measures 4 mm2 including the pad ring.
The SNR loss against the simulated behavior (72.9dB) is mainly due to 1/f noise in the first transconductor. To demonstrate the robustness against clock jitter of the architecture, the clock jitter was increased until it was the dominant source of the in band noise. The FFT of the measured data has been plotted in figure 9 when the
111
modulator is clocked at 53.7MHz and a test tone of – 10dBfs is applied. The dotted trace shows the FFT of the measured data using the nominal jitter of the clock generator (18ps rms, 0.1% of the clock period T) which produces a SNDR of 62.4dB. The solid trace shows the FFT of the captured data with a clock jitter variance of 186ps rms (1% of T), which produces a SNDR of 57.7dB, only 5dB below the nominal case. For comparison purposes, the dashed trace shows the simulated output of an equivalent continuous-time sigma-delta modulator implemented with ideal integrators using the same test signal and clock jitter variance of 1% of T. In this case, the SNDR is a mere 43.3dB. As it can be seen, the spectral density of the in band noise caused by this level of jitter variance is 15dB larger in the integrator-based modulator than in the case of the transmission line modulator. dBfs
Figure 10. Oscilloscope capture of the first transconductor output voltage.
0
5. Conclusion We have demonstrated the feasibility of CTSD modulation with transmission lines. The prototype second-order modulator was clocked at 53.7 MHz and achieves 67dB peak SNR at an oversampling ratio of 128. When an excessive clock jitter of 1% of the clock period is applied, the modulator SNDR is degraded by 5dB only. This is 15dB better than a conventional CTSD modulator with capacitive integrators.
-10 -20 -30 -40 -50 -60
6. References [1] J. Cherry, W. Snelgrove, “Continuous-Time DeltaSigma Modulators for High-Speed A/D Conversion”, Kluwer Academic Publishers, Boston, MA, 1999. [2] Gerfers, F., Ortmanns, M., Samid, L., Manoli, Y., “Implementation of a 1.5V low-power clock-jitter insensitive continuous-time Sigma-Delta modulator” Int. Symp. On Circuits and Systems, 2002, Volume: 2 , 2629 May 2002 Page(s): II-652 -II-655 vol.2 [3] Luschas S., H. S. Lee, “High-speed Sigma-Delta modulators with reduced timing jitter sensitivity”, Transactions on Circuits and Systems II, Volume: 49 Issue: 11 , Nov. 2002 , Page(s): 712 -720 [4] L. Hernandez, S. Patón, “Continuous Time SigmaDelta modulators with transmission line resonators and improved jitter and excess loop delay performance”, ISCAS 2003. [5] L. Hernandez, “Continuous-Time Sigma-Delta Modulators with Reduced Timing Jitter Sensitivity Based on Time-Delays”, Electronics Letters, Volume: 39 Issue: 14 , 10 July 2003 , Page(s): 1039 -1041 [6] Z.-Y. Chang, D. Macq, D. Haspeslagh, P. Spruyt and B. Goffart, “A CMOS Analog Front-End Circuit for an FDM-Based ADSL System,” IEEE J. of Solid-State Circuits, vol. 30, pp. 1449-1456, Dec. 1995. [7] E. Sackinger and W. Guggenbuhl, “A High-Swing, High-Impedance MOS Cascode Circuit”, IEEE J. SolidState Circuits, vol. 25, No. 2, pp. 289--298, Feb. 1990. [8] D. Johns and K. Martin, “Analog Integrated Circuit Design”, 1997, John Wiley & Sons. This work has been funded by project TIC-2000-0371 of the Spanish ministry of science and technology (CICYT).
-70 -80 -90 -100 6.6KHz
66.5KHz
665KHz
6.6MHz
f
Figure 9. Measured output spectrum for the CTSD modulator with delays and simulated output spectrum for an equivalent integrator based CTSD modulator for a clock jitter of σ=1%Ts.
The pads of the external transmission lines allow to observe the time domain waveform at the transmission line connection. The feedback DAC signal in the transmission line has a staircase shape with flat top pulses, which is the reason for a lesser jitter sensitivity. This situation is depicted in Figure 10 which shows the measured voltage across gm1 (v1(t)) in the upper trace and the clock in the lower trace. In this measurement, the modulator input was grounded (idle channel) and the clock was set to 9MHz. As may be seen, this signal is composed of staircase-like ramps corresponding to accumulated square DAC pulses. At 3.3 Volt supply voltage, power consumption was measured as 30mW analog and 16.5 mW digital. Since the circuit’s goal was to demonstrate the feasibility and the jitter insensitivity of CTSD modulation with transmission lines, no attempt was done to obtain a power efficient design.
112
Carlos III de Madrid, Madrid, Spain Ghent University, Gent, Belgium identical properties as a discrete time counterpart [5]. This way a modulator with a large insensitivity toward jitter and excess loop delay is obtained. In this work, di coefficients are chosen such that the CTSD modulator is equivalent to the ideal second-order lowpass discrete time modulator. Mathematically this can be written as:
Abstract This work presents a prototype low pass continuous time sigma delta modulator which uses transmission lines in its loop filter rather than capacitive integrators. As has been shown in prior theoretical work, such a structure allows to desensitize the modulator against clock jitter and excess loop delay. The prototype single-bit modulator was designed for an oversampling ratio of 128. Clocked at 53.7 MHz it achieves a peak SNR of 67 dB. In an experiment with an excessive clock jitter of 1% of the clock period, the SNDR is degraded by only 5dB compared to the case without jitter. This is 15dB better than an equivalent modulator with capacitive integrators.
NTF (z )
2
( (
) )
(2)
NTF (s ) = e d 3 H + d 3 (d 1 + d 2 )H + d 1 d 1 d 3 − 1 This yields the values d1=1 , d2=3 , d3=1/4. Coefficient d3 may be neglected in our single-bit design. − sT
−1
2
fs=1/Ts x(t)
1. Introduction Continuous time sigma delta (CTSD) modulators are nowadays a proven technology for high speed A/D converter implementation [1]. However, CTSD modulators are more sensitive to circuit impairments than switched capacitor implementations. Some of the performance limiting factors of CTSD modulators are clock jitter and excess loop delay [1], [2], [3]. In [4] a delay linear system is proposed to implement the loop filter of a CTSD modulator. This linear system may process a sequence of pulses, such as the feedback DAC signal of the modulator, into another sequence of similar pulses. This property is used in [5] to desensitize the CTSD modulator from jitter and excess loop delay. In this work, we present a CMOS implementation of the modulator proposed in [5]. In this proof-of-concept single-bit modulator, off-chip transmission lines are used to implement the delays. A future design could employ on-chip resonators, such as integrated transmission lines or MEMS devices. The presented work describes the circuit design and the measurements that demonstrate the usefulness of the overall concept.
+
+
H
y(n)
+
H
d3
d2
d1
z-1
Figure 1. System level diagram of a 2nd order modulator implemented with transmission lines.
Now we will focus on the circuit implementation of fig. 1 using transmission lines. A circuit that exactly mimics the behavior of the system of figure 1 is shown in figure 2 [5]. It is implemented with transmission lines, transconductors and a current feedback DAC. Ir z-1 -Ir fs=1/T v1(t)
v(t) gm1= 1/Zo
R1=ZO
v2(t) gm2= 1/Zo
λ/4
2. CTSD modulators with transmission lines Figure 1 shows the system level diagram of the CTSD modulator with transmission lines [5]. The blocks named H implement the following transfer function: 1 + e − sT (1) H (s ) = 1 − e − sT This transfer function is proportional to the impedance of an open circuit transmission line, where T corresponds to the delay of the transmission line. If this delay T is equal to the period of the sampling clock, this diagram can be used to implement a CTSD modulator that has nearly
0-7803-8715-5/04/$20.00 ©2004 IEEE.
= NTF (s ) , NTF (z ) = (1 − z −1 )
z − 1 = e − sT
ZL open
R2=3ZO
y[n]
λ/4
ZL open
Figure 2. Conceptual circuit implementation of a CTSD modulator with transmission lines.
The combination of a transconductor and the transmission line produces the same transfer function as blocks H in fig. 1. The previously defined di coefficients, are implemented by adding series resistors to the transmission lines. The appropriate values of these resistors and the transconductors are expressed in Table I. Here fs corresponds to the sampling frequency, Z0 to
109
the characteristic impedance of the line and ViMAX to the maximum input level. gm1 gm2 R1 R2 Ir λ
any theoretical SNR degradation, if a NRZ feedback pulse is used. 3. Circuit Design The system block diagram and parameters defined in the previous section were used as the start point of a CMOS circuit design. For this proof-of-concept circuit, a conservative 0.6u standard CMOS process and a power supply of 3.3 Volt were selected. A clock frequency of 50 MHz was targeted .
1/Z0 1/Z0 Z0 3Z0 ViMAX/Z0 v/2fs
Table I In [5] it was shown that transconductors require a bandwidth of 2.5fs to ensure that the intersymbol interference between the feedback DAC pulses will produce a noise power below the quantization noise, when moderate jitter is present. Time domain simulations on the state variables of fig. 1 have defined the saturation values for the transconductors. These values are shown in figure 3, considering an ideal transconductor and an open loop gain limited to 120dB at DC to account for transmission line losses.
V1,V2/Vimax
10
V1/Vimax
0 0,3
0,4
0,5
0,6
0,7
0,8
0,9
ESD prot.
digital interface
gm2
sync. latch
clk
A block diagram of the chip is shown on figure 4. It consists of a first input transconductor, a second transconductor, a comparator, a synchronization latch, a 1bit DAC and a digital interface block. Essentially it is a fully differential implementation of the modulator shown on figure 2. The transmission lines and their series resistors are not implemented on-chip. This way, the output of each transconductor is connected to an ESDprotected bond pad. The most demanding building block of the entire circuit is the input transconductor. This block should be at least as linear as the linearity of the overall modulator. The reason for this is that this transconductor performs the voltage-to-current conversion of the input signal prior to entering the feedback loop. Hence, non-linearity of this transconductor is not attenuated by the operation of the loop. For the same reason, this input transconductor does only require the bandwidth of the input signal instead of 2.5 times the sampling frequency, as stated in the previous section, which only applies to transconductor gm2. Figure 5 depicts the simplified schematic of this first transconductor. It is based on source degeneration of the input differential pair transistors similar to what was used in [6]. For enhanced linearity, the operational amplifiers A1 and A2 are added at the inputs. These amplifiers are implemented as simple NMOS differential pairs with active loads. The resistor R is a 1kΩ linear resistor which is available in the target process. This value was a compromise between noise and power consumption. Note that this does not correspond to the value of Table 1. However, as explained above, the first transconductor is outside the loop and hence this deviation from the theory only results in a gain error of the overall modulator. Amplifiers A3-A4 are added to achieve an adequate output impedance [7]. It turned out that the equivalent amplifiers for the NMOS cascodes
15
0,2
ESD prot.
ESD prot.
clk Figure 4. Block diagram of the CMOS chip.
20
0,1
ESD prot.
1bit DAC
V2/Vimax
5
to off-chip transmission line and series resistor
gm1
30
25
to off-chip transmission line and series resistor
1
Vi/Vimax
Figure 3. Dynamic range of the state variables
Using the graph of fig. 3, we may estimate the maximum current provided by transconductor gm2 and its maximum input voltage. For an input tone of –4dBfs, the maximum current delivered by gm2 is 1.74Ir and the maximum amplitude at the transmission line V1(t) is 1.1Vi MAX. We can also note that the value of V2(t) peaks at 9.7ViMAX for the same input level. To compare this value with a standard second order sigma-delta modulator we should multiply V2(t) by d3. To bring this down to a reasonable level, the loop filter must be scaled in this single-bit design. It must be noted that the parameters of the analog components of this design are independent of the sampling clock, as long as the clock frequency has to fit only with the length of the external transmission lines. In the case of a standard CTSD modulator, most of the architecture coefficients are related to the sampling frequency, which forces to define such parameter in the design process. In this case, only the bandwidth requirements of the transconductors and the maximum operating frequency of the sampler and DAC set the bounds for the clock rate. Also, the modulator requires a certain excess loop delay to operate. This excess loop delay may vary between 0 to one full clock cycle without
110
The values of the circuit parameters that have been chosen for the design are in Table III. Z0 50Ω R1 50Ω R2 150Ω Ir 300µA Table III
could be removed. This is due to the fact that relatively long channels were used for these current source transistors, that are outside the main signal path.
Figure 5. Simplified schematic of the first transconductor.
Since the circuit is differential, it requires a common mode feedback to stabilize the output common mode voltage. The circuit [8], shown on figure 6, was used to set the common mode level.
Figure 7. Chip micro photograph
To test the chip, four pieces of RG-178 coaxial cable were used as off chip resonators, trimmed to the clock frequency. The test setup consisted of a PCB board with current references, analog single ended to differential drivers and an interface to a logic analyzer. The modulator was tested by applying sinusoidal signals at its input. Here, typically an input frequency of fs/512 was used. The peak SNR occurs for a -4dBfs input. Using a clock generator with a nominal rms jitter of 0.1% the nominal clock period, a SNR of 67dB was measured for an OSR of 128. For this case the measured SNR has been plotted vs. the input signal level in figure 8, which demonstrates a dynamic range of 69 dB.
Figure 6. Simplified schematic of the first transconductor’s common mode feedback.
The second transconductor (gm2 on fig. 4) is implemented as a simple differential pair without source degeneration nor auxiliary amplifiers. This is possible because nonlinearity of this block is attenuated by the operation of the loop. Due to the simplicity of this block, it also achieves high bandwidth. The comparator is implemented as a simple pre-amplifier to avoid kickback and a two stage regenerative latch. The synchronization latch is strobed slightly after the comparator latch [8]. The digital block groups 8 consecutive output bits in a single 8-bit word to reduce the clock rate of the output digital pads. Also a direct digital output is provided for testing at low clock rates. This block is composed of a shift register, that makes the serial to parallel conversion, a parallel loadable register, that captures every 8-bit word, and a ring counter that controls the block and generates the output signals. A full SPICE transistor-level simulation of the chip predicted a SNR of 72.9 dB for a -4dBfs tone test signal, considering an OSR of 128.
90
SNR(dB)
70 50 30 10 -10 -70
-60
-50
-40
-30
-20
-10
0
dBFs
Figure 8. Measured SNR vs. input signal level.
4. Implementation and measurements A photograph of the prototype chip is shown in figure 7. The lay-out of each block and the final floor planning has been completed taking into consideration the pad routing to minimize the parasitic capacitance at the transmission line connections. The chip measures 4 mm2 including the pad ring.
The SNR loss against the simulated behavior (72.9dB) is mainly due to 1/f noise in the first transconductor. To demonstrate the robustness against clock jitter of the architecture, the clock jitter was increased until it was the dominant source of the in band noise. The FFT of the measured data has been plotted in figure 9 when the
111
modulator is clocked at 53.7MHz and a test tone of – 10dBfs is applied. The dotted trace shows the FFT of the measured data using the nominal jitter of the clock generator (18ps rms, 0.1% of the clock period T) which produces a SNDR of 62.4dB. The solid trace shows the FFT of the captured data with a clock jitter variance of 186ps rms (1% of T), which produces a SNDR of 57.7dB, only 5dB below the nominal case. For comparison purposes, the dashed trace shows the simulated output of an equivalent continuous-time sigma-delta modulator implemented with ideal integrators using the same test signal and clock jitter variance of 1% of T. In this case, the SNDR is a mere 43.3dB. As it can be seen, the spectral density of the in band noise caused by this level of jitter variance is 15dB larger in the integrator-based modulator than in the case of the transmission line modulator. dBfs
Figure 10. Oscilloscope capture of the first transconductor output voltage.
0
5. Conclusion We have demonstrated the feasibility of CTSD modulation with transmission lines. The prototype second-order modulator was clocked at 53.7 MHz and achieves 67dB peak SNR at an oversampling ratio of 128. When an excessive clock jitter of 1% of the clock period is applied, the modulator SNDR is degraded by 5dB only. This is 15dB better than a conventional CTSD modulator with capacitive integrators.
-10 -20 -30 -40 -50 -60
6. References [1] J. Cherry, W. Snelgrove, “Continuous-Time DeltaSigma Modulators for High-Speed A/D Conversion”, Kluwer Academic Publishers, Boston, MA, 1999. [2] Gerfers, F., Ortmanns, M., Samid, L., Manoli, Y., “Implementation of a 1.5V low-power clock-jitter insensitive continuous-time Sigma-Delta modulator” Int. Symp. On Circuits and Systems, 2002, Volume: 2 , 2629 May 2002 Page(s): II-652 -II-655 vol.2 [3] Luschas S., H. S. Lee, “High-speed Sigma-Delta modulators with reduced timing jitter sensitivity”, Transactions on Circuits and Systems II, Volume: 49 Issue: 11 , Nov. 2002 , Page(s): 712 -720 [4] L. Hernandez, S. Patón, “Continuous Time SigmaDelta modulators with transmission line resonators and improved jitter and excess loop delay performance”, ISCAS 2003. [5] L. Hernandez, “Continuous-Time Sigma-Delta Modulators with Reduced Timing Jitter Sensitivity Based on Time-Delays”, Electronics Letters, Volume: 39 Issue: 14 , 10 July 2003 , Page(s): 1039 -1041 [6] Z.-Y. Chang, D. Macq, D. Haspeslagh, P. Spruyt and B. Goffart, “A CMOS Analog Front-End Circuit for an FDM-Based ADSL System,” IEEE J. of Solid-State Circuits, vol. 30, pp. 1449-1456, Dec. 1995. [7] E. Sackinger and W. Guggenbuhl, “A High-Swing, High-Impedance MOS Cascode Circuit”, IEEE J. SolidState Circuits, vol. 25, No. 2, pp. 289--298, Feb. 1990. [8] D. Johns and K. Martin, “Analog Integrated Circuit Design”, 1997, John Wiley & Sons. This work has been funded by project TIC-2000-0371 of the Spanish ministry of science and technology (CICYT).
-70 -80 -90 -100 6.6KHz
66.5KHz
665KHz
6.6MHz
f
Figure 9. Measured output spectrum for the CTSD modulator with delays and simulated output spectrum for an equivalent integrator based CTSD modulator for a clock jitter of σ=1%Ts.
The pads of the external transmission lines allow to observe the time domain waveform at the transmission line connection. The feedback DAC signal in the transmission line has a staircase shape with flat top pulses, which is the reason for a lesser jitter sensitivity. This situation is depicted in Figure 10 which shows the measured voltage across gm1 (v1(t)) in the upper trace and the clock in the lower trace. In this measurement, the modulator input was grounded (idle channel) and the clock was set to 9MHz. As may be seen, this signal is composed of staircase-like ramps corresponding to accumulated square DAC pulses. At 3.3 Volt supply voltage, power consumption was measured as 30mW analog and 16.5 mW digital. Since the circuit’s goal was to demonstrate the feasibility and the jitter insensitivity of CTSD modulation with transmission lines, no attempt was done to obtain a power efficient design.
112
