A Low Phase Noise 20 GHz Voltage Control Oscillator using 0.18-μm ...
A Low Phase Noise 20 GHz Voltage Control Oscillator using 0.18-μm CMOS Technology Z. M. Yang, H. L. Kao*, Y. C. Chang and M. T. Chen
H. M. Chang and C. H. Wu
Department of Electronic Engineering Chang Gung University Tao-Yuan, Taiwan *[email protected]
Department of MicroElectronics Engineering Chung Hua University Hsinchu, Taiwan
Abstract—A low phase noise, small power dissipation and small sized K-band cascode differential voltage-controlled oscillator (VCO) with capacitive feedback topology using 0.18 μm CMOS technology is described. The VCO operated can be tuned between 19.1 GHz and 20.9 GHz and has low phase noise of -108.67 dBc/Hz at a 1 MHz offset. The output power of the 20.7 GHz is about -21.12 dBm. The Figure of merit (FOM) is -186.2 dBc/Hz and the power-frequency tuning-normalized figure-of-merit (PFTN) is -8.89 dB. The power consumption of the VCO was 10.8 mW from a 1.8 V power supply with only 0.46 mm2 chip area. Keywords-phase noise, tuning range, FOM, PFTN, K-band, CMOS, voltage control oscillators (VCOs).
I.
INTRODUCTION
The fully-integrated CMOS technology operating into millimeter-wave frequencies have been attention to its low cost and high integration, even when the Si substrate has higher loss than III-V circuits. The high data rate, low power and low cost is required for the wireless and communication systems to push the systems toward higher operating frequencies. Intensive effort has been made to develop RF integrated circuit at the range of few tens of gigahertz using CMOS process [1]-[8]. The voltage-controlled oscillator (VCO) is an important element of a wireless transceiver. However, it is difficult to design a 0.18 μm CMOS VCO with good performance above 10 GHz due to the lack of high-Q inductor and high flicker noise of the MOSFETs. The challenges for VCO circuits include wide frequency range, low phase noise degradation, low power consumption and small die size. Within CMOS technology several different VCO circuit approaches have been proposed to overcome these issues. The VCO using transformers [9], coplanar lines [10], and micro-machined inductors [11] can achieve high Q factor to improve the phase noise. The capacitive feedback topology of cross-coupled VCO [6] is used to improve the phase noise and output swing. In this paper, we proposed a 20 GHz cascode differential VCO using capacitive feedback with a transformer and an inductor fabricated in a 0.18 μm CMOS technology. Here CMOS technology is attractive due to the rapid down-scaling of the device size, continuously increasing cut-off frequencies [12][13], improving inductor Q-factors [14]-[17], low cost, highlevel integration [12]-[17], as well as the potential for Systemon-Chip (SoC) solutions. Our proposed K-band VCO circuit
operates in the 20 GHz bands achieve phase noise of -108.67 dc/Hz and tuning range of 1.8 GHz. The low power consumption of 20 GHz VCO circuit is 10.8 mW with only 0.46 mm2 chip size. The performance of our K-band VCO design compares well with the best reported data in the literature [6]-[10]. II.
CIRCUIT DESIGN
Fig. 1 illustrates our design of a 20 GHz LC tank cascade differential VCO architecture, using 0.18 μm CMOS technology. The circuit schematic is of a cascode differential oscillator and the capacitive feedback topology. The symmetric components are identical. The cascode differential architecture is implemented with negative conductance circuit to improving the phase noise performance and reducing the power dissipation of the VCO circuit. The capacitive feedback topology is used to determinate the oscillating frequency. These two approach of our propose 20 GHz VCO can achieve low noise, high output power, wide tuning range.
Fig. 1. Schematic of the ADS-designed cascode differential VCO circuit which uses TSMC’s 0.18μm RF CMOS technology.
A. Cascode connection circuit The half circuit and its small signal circuit of the proposed cascode differential VCO is shown in Fig. 2. The M1 is the input transistor and M3 is the common gate transistor stack on M1. The voltage gain of the cascode amplifier without capacitors is given by [18]
Av = − g m1Qin × GP = and
1 1 1 , = − g m ,eff × ≈ − g m ,eff × GT GT Gp Rs 1 , = 2 R s (Q + 1) (ωL / 2) 2
Q=
1 GT
CT , L/2
where gm1 is the transconductance of M1, Qin is the Q factor of the input circuit, gm,eff is the effective transconductance of the amplifier, GT is the total conductance including M3 and equivalent parallel inductor (L1/2). The conductance of the inductor is Gp which dominates the GT. The Rs is the series equivalent resistance of L1/2 and Q is the quality factor of the inductor. The CT is the total capacitance at the drain of M3.
GT = G N + G P =
As GT is reduced, the Av and Q of cascode connection are increased. Thus the phase noise is improved proportional to voltage amplitude and quality factor. B. Capacitive feedback circuit The capacitive feedback is composed of C1 and CT which including the varactor of Cv1. The small signal model of the VCO without stacked transistor M3 is shown in Fig. 3. The proposed capacitive feedback VCO topology is similar to a Colpitts oscillator. The oscillating frequency and the unity loop gain are given as
ωo =
gm =
and
1 . RT
Small signal circuit of the capacitive feedback circuit.
From the part A and B, we used cascode differential topology and capacitive feedback technique to achieved high frequency, low phase noise and high gain.
(a)
III.
(b) Fig. 2. (a) Half circuit and (b) small signal circuit of the cascode differential VCO. The negative conductance generated by C3 and Cgs3 is
GN =
C1 + CT C1CT LD
The phase noise can be improved by using the capacitive feedback circuit [6]. However, the large value of C2/C1 reduces the oscillating frequency. Therefore, the oscillating frequency and phase noise is trade-off for the high frequency design.
Fig. 3.
− ω 2 C 3 C gs 3
ω 2 C 3 C gs 3 Rs . − g m3 (ωL / 2) 2
.
g m3
Therefore, the total conductance at the drain of M3 is
MEASUREMENT RESULTS
A 0.18 μm 1P6M Si CMOS process with a 2-μm-thick top metal interconnected is used to implement the 20 GHz voltage control oscillator. The k-band CMOS VCO was simulated using Advance Design System (ADS) software. The ground shielding is required for the layout due to the lossy Si substrate. Fig. 3 shows the layout and the chip micrograph of the fabricated VCO whose size is 0.608 × 0.753 mm2 including the the probe pads. The K-band VCO was tested on wafer – the spectral density of the circuit being measured with a spectrum analyzer. The total power consumption of 20 GHz VCO circuit is 10.8 mW under a supply voltage of 1.8V. The proposed 20 GHz VCO was tuned from 19.1 GHz to 20.9 GHz as shown in Fig. 4, indicating a tuning rage of 1.8 GHz (near 8.7% tuning rage) with tuning voltage varying from
0 to 4V. The output spectrum of our proposed VCO is shown in Fig. 5. The center frequency is 20.7 GHz with -21.12 dBm output power. Fig. 6 shows the measured phase noise at 1 MHz offset operating at a controlled voltage of 2.75 V. The lowest phase noise is about -108.67 dBc/Hz at 1 MHz offset from the 20.7 GHz carrier frequency.
where L{foffset} is the measured phase noise at the offset frequency foffset from the carrier frequency fo. PDC is the VCO power consumption in mW and ftune is the tuning range. Larger |FOM| and PFTN values correspond to better oscillators. The FOMs of our circuit were -186 dBc/Hz at 1 MHz offset. The PFTN were -8.42 dB at 1 MHz offset.
Transformer
Inductor
Fig.3. Chip layout of the cascode differential VCO circuit.
21.5
Frequency (GHz)
Fig. 4.
Harmonic characteristic of the cascode differential VCO
Fig. 5.
Measured phase noise of the cascode differential VCO
circuit.
21.0 20.5 20.0 19.5 19.0 18.5
0
1
2
3
4
Vcontrol (V) Fig. 4.
circuit.
The tuning range of the cascode differential VCO
Two important parameters to compare the performance of VCOs at different frequencies are the figure of merit (FOM) and power-frequency tuning-normalized figure-of-merit (PFTN) are defined as [3]
FOM = L{ f offset } − 20 log(
fo
P ) + 10 log( DC ) f offset 1 mW
and
PFTN = log(
f kT ) + 20 log( tune ) − L{ f offset } PDC f offset
circuit.
Table 1 summarizes the measured performance of our VCO and includes other reported performances for comparison. Our k-band VCO achieved a wide tuning range, low power, small size, and small phase noise degradation which compares well or better with other published reports [3]-[6].
Table 1. Comparison of VCO circuit performance: published and this work.
Ref
Ref[3]
Ref[4]
Ref[5]
0.18 μm
0.18 μm
0.18 μm
0.18 μm
0.18 μm
fo
Phase Noise (dBc/Hz) Output power (dBm)
25.1 GHz 3.01 GHz (12%) -99.94 @ 1MHz -4.2
20.9 GHz 2.17 GHz (10.4%) -111.67 @1 MHz -6.83
24.2 GHz 1.45 GHz (6%) -118.6 @ 10MHz -8.89
19.9 GHz 510 MHz (2.6%) -111 @1 MHz -3
20.7GHz 1.8 GHz (8.7%) -108.67 @1 MHz -21.12
PDC (mW)
11
40.32
14.5
39
10.8
FOM (dBc/Hz)
-177.5
-181.5
-175
-181.06
-184.65
PFTN (dB)
-14.7
-11.5
-23.6
-24.6
-10.38
0.544
0.973
0.55
0.55
0.457
2
Chip Area (mm ) IV.
CONCLUSIONS
A fully integrated CMOS differential VCO shows good circuit performance in terms of phase noise and tuning range. The circuit was fabricated in a 0.18 μm CMOS process. This 20 GHz VCO exhibited a -108.67 dBc/Hz phase noise at a 1 MHz offset and 8.7 % tuning range. The power consumption of the VCO was only 10.8 mW, while the total die size was only 0.46 mm2. The fabricated VCO demonstrated low power, small size, little phase noise degradation and a wide tuning range.
[7]
[8]
[9]
[10] [11]
ACKNOWLEDGMENT The authors wish to thank the Chip Implemental Center (CIC) of the National Science Council in Taiwan for their help. This work was partially supported by NSC (98-2221-E-182024) and CGU (UERPD290061) of Taiwan. REFERENCES
[2]
[3]
[4]
[5]
[6]
This work
Process (μm)
Tuning Range
[1]
Ref[6]
J. Gil, S. S. Song, H. Lee, and H. Shin, “A -119.2 dBc/Hz at 1MHz, 1.5 mW, fully integrated, 2.5-GHz, CMOS VCO using helical inductors,” in IEEE Microwave & Wireless Components Lett., Vol. 13, No. 11, pp. 457-459, Nov. 2003. Y. A. Eken, and J. P. Uyemura, “A 5.9-GHz voltage-controlled ring oscillator in 0.18 μm CMOS,” in IEEE J. Solid-State Circuits, Vol. 39, No. 1, pp. 230-233, Jan. 2004. D. Ozis, N. M. Neihart, and D. J. Allstot, “Differential VCO and passive frequency doubler in 0.18 mm CMOS for 24 GHz applications,” in IEEE RF IC Symp. Dig., 2006. S. Ko, J.-G. Kim, T. Song, E. Yoom, and S. Hong, “20 GHz integrated CMOS frequency sources with a quadrature VCO using transformers,” in IEEE RF IC Symp. Dig., 2004. A. W.L. Ng, G. C.T. Leung, K.-C. Kwok, L. L.K. Leung, H. C. Luong, “A1V 24GHz 17.5mW PLL in 0.18 μm CMOS,” International SolidState Circuits, session 8, pp. 158-160, Feb. 2005. H. H. Hsieh and L. H. Lu, “A Low-Phase-Noise K-Band CMOS VCO,” in IEEE Microwave & Wireless Components Lett., Vol. 16, No. 10, pp. 552-554, Oct. 2006.
[12] [13]
[14]
[15]
[16]
[17]
[18]
D. Leenaerts, C. Dijkmans, and M. Thompson, “A 0.18 μm CMOS 2.45 GHz, low-power quadrature VCO with 15 % tuning range,” in IEEE RF IC Symp. Dig., pp. 67-70, 2002. J. Bhattacharjee, D. Mukherjee, E. Gebara, S. Nuttinck, and J. Laskar, “A 5.8 GHz fully integrated low power low phase noise CMOS LC VCO for WLAN applications,” in IEEE MTT-S Int. Microwave Symp. Dig., 2002, pp. 585-588. N. J. Oh, and S.-G. Lee, “11-GHz CMOS differential VCO with backgate transformer feedback,” in IEEE Microwave & Wireless Components Lett., Vol. 15, No. 11, pp. 733-735, Oct. 2005. H. Krishnaswamy and H. Hashemi, “A 26 GHz coplanar stripline-based current sharing CMOS oscillator,” in IEEE RF IC Symp. Dig., 2005. T.-P. Wang, R.-L. Liu, H.-Y. Chang, L.-H. Lu, and H. Wang, “A 22GHz push-push CMOS oscillator using micromachined inductors, “IEEE Microwave & Wireless Components Lett., Vol. 15, No. 12, pp. 7859-861, Dec. 2005. R. Aparicio and A. Hajimiri, “Circular-geometry oscillators,” in IEEE Int. Solid-State Circuit Conf. (ISSCC) Dig. Tech., pp. 378-379, 2004. H. L. Kao, A. Chin, J. M. Lai, C. F. Lee, K. C. Chiang and S. P. McAlister, “Modeling RF MOSFETs after electrical stress using lownoise microstrip line layout,” in IEEE RF IC Symp. Dig., 2005, pp.157160. H. L. Kao, A. Chin, B. F. Hung, J. M. Lai, C. F. Lee, M.-F. Li, G. S. Samudra, C. Zhu, Z. L. Xia and J. F. Kang, “Strain-induced very low noise RF MOSFETs on flexible plastic substrate,” in Symp. on VLSI Tech., 2005, pp. 160-161. D. S. Yu, K. T. Chan, A. Chin, S. P. McAlister, C. Zhu, M. F. Li, and D.-L. Kwong, “Narrow-Band Band-pass Filters on Silicon Substrates at 30 GHz,” in IEEE MTT-S Int. Microwave Symp. Dig., 2004, vol. 3, pp. 1467-1470. K. T. Chan, A. Chin, S. P. McAlister, C. Y. Chang, V. Liang, J. K. Chen, S. C. Chien, D. S. Duh, and W. J. Lin, “Low RF loss and noise of transmission lines on Si substrates using an improved ion implantation process,” in IEEE MTT-S Int. Microwave Symp. Dig., 2003, vol. 2, pp. 963-966. K. T. Chan, A. Chin, C. M. Kwei, D. T. Shien, and W. J. Lin “Transmission line noise from Standard and proton-implanted Si,” in IEEE MTT-S Int. Microwave Symp. Dig., 2001, vol. 2, pp. 763-766. C.-Y. Wu and S.-Y. Hsiao, “The Design of a 3-V 900 MHz CMOS Bandpass Amplifier,” in IEEE J. Solid-State Circuits, Vol. 32, No. 2, pp. 159-168, Feb. 1997.
H. M. Chang and C. H. Wu
Department of Electronic Engineering Chang Gung University Tao-Yuan, Taiwan *[email protected]
Department of MicroElectronics Engineering Chung Hua University Hsinchu, Taiwan
Abstract—A low phase noise, small power dissipation and small sized K-band cascode differential voltage-controlled oscillator (VCO) with capacitive feedback topology using 0.18 μm CMOS technology is described. The VCO operated can be tuned between 19.1 GHz and 20.9 GHz and has low phase noise of -108.67 dBc/Hz at a 1 MHz offset. The output power of the 20.7 GHz is about -21.12 dBm. The Figure of merit (FOM) is -186.2 dBc/Hz and the power-frequency tuning-normalized figure-of-merit (PFTN) is -8.89 dB. The power consumption of the VCO was 10.8 mW from a 1.8 V power supply with only 0.46 mm2 chip area. Keywords-phase noise, tuning range, FOM, PFTN, K-band, CMOS, voltage control oscillators (VCOs).
I.
INTRODUCTION
The fully-integrated CMOS technology operating into millimeter-wave frequencies have been attention to its low cost and high integration, even when the Si substrate has higher loss than III-V circuits. The high data rate, low power and low cost is required for the wireless and communication systems to push the systems toward higher operating frequencies. Intensive effort has been made to develop RF integrated circuit at the range of few tens of gigahertz using CMOS process [1]-[8]. The voltage-controlled oscillator (VCO) is an important element of a wireless transceiver. However, it is difficult to design a 0.18 μm CMOS VCO with good performance above 10 GHz due to the lack of high-Q inductor and high flicker noise of the MOSFETs. The challenges for VCO circuits include wide frequency range, low phase noise degradation, low power consumption and small die size. Within CMOS technology several different VCO circuit approaches have been proposed to overcome these issues. The VCO using transformers [9], coplanar lines [10], and micro-machined inductors [11] can achieve high Q factor to improve the phase noise. The capacitive feedback topology of cross-coupled VCO [6] is used to improve the phase noise and output swing. In this paper, we proposed a 20 GHz cascode differential VCO using capacitive feedback with a transformer and an inductor fabricated in a 0.18 μm CMOS technology. Here CMOS technology is attractive due to the rapid down-scaling of the device size, continuously increasing cut-off frequencies [12][13], improving inductor Q-factors [14]-[17], low cost, highlevel integration [12]-[17], as well as the potential for Systemon-Chip (SoC) solutions. Our proposed K-band VCO circuit
operates in the 20 GHz bands achieve phase noise of -108.67 dc/Hz and tuning range of 1.8 GHz. The low power consumption of 20 GHz VCO circuit is 10.8 mW with only 0.46 mm2 chip size. The performance of our K-band VCO design compares well with the best reported data in the literature [6]-[10]. II.
CIRCUIT DESIGN
Fig. 1 illustrates our design of a 20 GHz LC tank cascade differential VCO architecture, using 0.18 μm CMOS technology. The circuit schematic is of a cascode differential oscillator and the capacitive feedback topology. The symmetric components are identical. The cascode differential architecture is implemented with negative conductance circuit to improving the phase noise performance and reducing the power dissipation of the VCO circuit. The capacitive feedback topology is used to determinate the oscillating frequency. These two approach of our propose 20 GHz VCO can achieve low noise, high output power, wide tuning range.
Fig. 1. Schematic of the ADS-designed cascode differential VCO circuit which uses TSMC’s 0.18μm RF CMOS technology.
A. Cascode connection circuit The half circuit and its small signal circuit of the proposed cascode differential VCO is shown in Fig. 2. The M1 is the input transistor and M3 is the common gate transistor stack on M1. The voltage gain of the cascode amplifier without capacitors is given by [18]
Av = − g m1Qin × GP = and
1 1 1 , = − g m ,eff × ≈ − g m ,eff × GT GT Gp Rs 1 , = 2 R s (Q + 1) (ωL / 2) 2
Q=
1 GT
CT , L/2
where gm1 is the transconductance of M1, Qin is the Q factor of the input circuit, gm,eff is the effective transconductance of the amplifier, GT is the total conductance including M3 and equivalent parallel inductor (L1/2). The conductance of the inductor is Gp which dominates the GT. The Rs is the series equivalent resistance of L1/2 and Q is the quality factor of the inductor. The CT is the total capacitance at the drain of M3.
GT = G N + G P =
As GT is reduced, the Av and Q of cascode connection are increased. Thus the phase noise is improved proportional to voltage amplitude and quality factor. B. Capacitive feedback circuit The capacitive feedback is composed of C1 and CT which including the varactor of Cv1. The small signal model of the VCO without stacked transistor M3 is shown in Fig. 3. The proposed capacitive feedback VCO topology is similar to a Colpitts oscillator. The oscillating frequency and the unity loop gain are given as
ωo =
gm =
and
1 . RT
Small signal circuit of the capacitive feedback circuit.
From the part A and B, we used cascode differential topology and capacitive feedback technique to achieved high frequency, low phase noise and high gain.
(a)
III.
(b) Fig. 2. (a) Half circuit and (b) small signal circuit of the cascode differential VCO. The negative conductance generated by C3 and Cgs3 is
GN =
C1 + CT C1CT LD
The phase noise can be improved by using the capacitive feedback circuit [6]. However, the large value of C2/C1 reduces the oscillating frequency. Therefore, the oscillating frequency and phase noise is trade-off for the high frequency design.
Fig. 3.
− ω 2 C 3 C gs 3
ω 2 C 3 C gs 3 Rs . − g m3 (ωL / 2) 2
.
g m3
Therefore, the total conductance at the drain of M3 is
MEASUREMENT RESULTS
A 0.18 μm 1P6M Si CMOS process with a 2-μm-thick top metal interconnected is used to implement the 20 GHz voltage control oscillator. The k-band CMOS VCO was simulated using Advance Design System (ADS) software. The ground shielding is required for the layout due to the lossy Si substrate. Fig. 3 shows the layout and the chip micrograph of the fabricated VCO whose size is 0.608 × 0.753 mm2 including the the probe pads. The K-band VCO was tested on wafer – the spectral density of the circuit being measured with a spectrum analyzer. The total power consumption of 20 GHz VCO circuit is 10.8 mW under a supply voltage of 1.8V. The proposed 20 GHz VCO was tuned from 19.1 GHz to 20.9 GHz as shown in Fig. 4, indicating a tuning rage of 1.8 GHz (near 8.7% tuning rage) with tuning voltage varying from
0 to 4V. The output spectrum of our proposed VCO is shown in Fig. 5. The center frequency is 20.7 GHz with -21.12 dBm output power. Fig. 6 shows the measured phase noise at 1 MHz offset operating at a controlled voltage of 2.75 V. The lowest phase noise is about -108.67 dBc/Hz at 1 MHz offset from the 20.7 GHz carrier frequency.
where L{foffset} is the measured phase noise at the offset frequency foffset from the carrier frequency fo. PDC is the VCO power consumption in mW and ftune is the tuning range. Larger |FOM| and PFTN values correspond to better oscillators. The FOMs of our circuit were -186 dBc/Hz at 1 MHz offset. The PFTN were -8.42 dB at 1 MHz offset.
Transformer
Inductor
Fig.3. Chip layout of the cascode differential VCO circuit.
21.5
Frequency (GHz)
Fig. 4.
Harmonic characteristic of the cascode differential VCO
Fig. 5.
Measured phase noise of the cascode differential VCO
circuit.
21.0 20.5 20.0 19.5 19.0 18.5
0
1
2
3
4
Vcontrol (V) Fig. 4.
circuit.
The tuning range of the cascode differential VCO
Two important parameters to compare the performance of VCOs at different frequencies are the figure of merit (FOM) and power-frequency tuning-normalized figure-of-merit (PFTN) are defined as [3]
FOM = L{ f offset } − 20 log(
fo
P ) + 10 log( DC ) f offset 1 mW
and
PFTN = log(
f kT ) + 20 log( tune ) − L{ f offset } PDC f offset
circuit.
Table 1 summarizes the measured performance of our VCO and includes other reported performances for comparison. Our k-band VCO achieved a wide tuning range, low power, small size, and small phase noise degradation which compares well or better with other published reports [3]-[6].
Table 1. Comparison of VCO circuit performance: published and this work.
Ref
Ref[3]
Ref[4]
Ref[5]
0.18 μm
0.18 μm
0.18 μm
0.18 μm
0.18 μm
fo
Phase Noise (dBc/Hz) Output power (dBm)
25.1 GHz 3.01 GHz (12%) -99.94 @ 1MHz -4.2
20.9 GHz 2.17 GHz (10.4%) -111.67 @1 MHz -6.83
24.2 GHz 1.45 GHz (6%) -118.6 @ 10MHz -8.89
19.9 GHz 510 MHz (2.6%) -111 @1 MHz -3
20.7GHz 1.8 GHz (8.7%) -108.67 @1 MHz -21.12
PDC (mW)
11
40.32
14.5
39
10.8
FOM (dBc/Hz)
-177.5
-181.5
-175
-181.06
-184.65
PFTN (dB)
-14.7
-11.5
-23.6
-24.6
-10.38
0.544
0.973
0.55
0.55
0.457
2
Chip Area (mm ) IV.
CONCLUSIONS
A fully integrated CMOS differential VCO shows good circuit performance in terms of phase noise and tuning range. The circuit was fabricated in a 0.18 μm CMOS process. This 20 GHz VCO exhibited a -108.67 dBc/Hz phase noise at a 1 MHz offset and 8.7 % tuning range. The power consumption of the VCO was only 10.8 mW, while the total die size was only 0.46 mm2. The fabricated VCO demonstrated low power, small size, little phase noise degradation and a wide tuning range.
[7]
[8]
[9]
[10] [11]
ACKNOWLEDGMENT The authors wish to thank the Chip Implemental Center (CIC) of the National Science Council in Taiwan for their help. This work was partially supported by NSC (98-2221-E-182024) and CGU (UERPD290061) of Taiwan. REFERENCES
[2]
[3]
[4]
[5]
[6]
This work
Process (μm)
Tuning Range
[1]
Ref[6]
J. Gil, S. S. Song, H. Lee, and H. Shin, “A -119.2 dBc/Hz at 1MHz, 1.5 mW, fully integrated, 2.5-GHz, CMOS VCO using helical inductors,” in IEEE Microwave & Wireless Components Lett., Vol. 13, No. 11, pp. 457-459, Nov. 2003. Y. A. Eken, and J. P. Uyemura, “A 5.9-GHz voltage-controlled ring oscillator in 0.18 μm CMOS,” in IEEE J. Solid-State Circuits, Vol. 39, No. 1, pp. 230-233, Jan. 2004. D. Ozis, N. M. Neihart, and D. J. Allstot, “Differential VCO and passive frequency doubler in 0.18 mm CMOS for 24 GHz applications,” in IEEE RF IC Symp. Dig., 2006. S. Ko, J.-G. Kim, T. Song, E. Yoom, and S. Hong, “20 GHz integrated CMOS frequency sources with a quadrature VCO using transformers,” in IEEE RF IC Symp. Dig., 2004. A. W.L. Ng, G. C.T. Leung, K.-C. Kwok, L. L.K. Leung, H. C. Luong, “A1V 24GHz 17.5mW PLL in 0.18 μm CMOS,” International SolidState Circuits, session 8, pp. 158-160, Feb. 2005. H. H. Hsieh and L. H. Lu, “A Low-Phase-Noise K-Band CMOS VCO,” in IEEE Microwave & Wireless Components Lett., Vol. 16, No. 10, pp. 552-554, Oct. 2006.
[12] [13]
[14]
[15]
[16]
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