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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 49, NO. 11, NOVEMBER 2014
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A Multiphase Buck Converter With a Rotating Phase-Shedding Scheme For Efficient Light-Load Control Youngkook Ahn, Inho Jeon, and Jeongjin Roh, Senior Member, IEEE
Abstract—Mobile devices need to minimize their power consumption in order to maximize battery runtime, except during short extremely busy periods. This requirement makes dc-dc converters usually operate in standby mode or under light-load conditions. Therefore, implementation of an efficient regulation scheme under a light load is a key aspect of dc-dc converter design. This paper presents a multiphase buck converter with a rotating phase-shedding scheme for efficient light-load control. The converter includes four phases operating in an interleaved manner in order to supply high current with low output ripple. The multiphase converter implements a rotating phase-shedding scheme to distribute the switching activity concentrated on a single phase, resulting in a distribution of the aging effects among the phases instead of a single phase. The proposed multiphase buck converter was fabricated using a 0.18 µm bipolar CMOS DMOS process. The supply voltage ranges from 2.7 V to 5 V, and the maximum allowable output current is 4.5 A. Index Terms—Efficient light-load control, multiphase dc-dc converter, PFM control, rotating phase shedding.
I. INTRODUCTION
T
HE EMERGENCE of smart phones, tablet PCs, and other advanced devices has led to the rapid growth of the smart mobile market. The performance of smart mobile devices depends entirely on their application processor (AP). Smart mobile devices are required to have significant processing power in order to support their multiple functions. Since most smart devices are operated with batteries, managing power consumption while meeting the requirements of each function has been considered one of the most crucial issues in designing smart mobile devices. In the past, processing performance was improved simply by raising the clock speed. However, this approach puts constraints on performance due to additional heat generation and power consumption. Multi-core processors have recently emerged due to advancements in very-large-scale integration
Manuscript received March 15, 2014; revised June 30, 2014 and September 12, 2014; accepted September 20, 2014. Date of current version October 24, 2014. This work was supported in part by the Ministry of Knowledge Economy, Korea, under the University ITRC support program supervised by the National IT Industry Promotion Agency (NIPA-2014-H0301-14-1007), and supported in part by the Industrial Core Technology Development Program (10049095, “Development of Fusion Power Management Platforms and Solutions for Smart Connected Devices”) funded by the Ministry of Trade, Industry and Energy. The authors are with the Department of Electrical Engineering, Hanyang University, Ansan 426-791, Korea (e-mail: [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/JSSC.2014.2360400
technology. Theses multi-core platforms are becoming dominant in providing sufficient processing power and flexibility to smart mobile devices. A high-performance AP has a system-level power management unit that efficiently manages power utilization and reduces unnecessary power consumption. Representative system-level technologies include power gating and dynamic voltage and frequency scaling [1]. These technologies, which decrease unnecessary leakage and dynamic power, are widely used for processors that require high performance. The APs of smart mobile devices are required to have high-performance dc-dc converters as well as system-level power management techniques in order to support high current density and other stringent power constraints. The inductor-type switching dc-dc converters are widely and advantageously used because of their high efficiency and high power capability. However, there are limitations in terms of current driving capability and thermal management when only a single-phase dc-dc converter is used for a high-performance AP. Comparison of single-phase and multiphase dc-dc converters confirm that the latter are beneficial due to higher current driving capability, a smaller output voltage ripple, a faster transient response, and improved thermal management. Therefore, multiphase dc-dc converters are good candidates for smart mobile devices that require greater performance. Several advanced studies about multiphase dc-dc converters have been conducted. The design and analysis of a fully integrated multiphase buck converter with on-chip filter inductors and capacitors are presented in [2]. A high-frequency multiphase hysteretic dc-dc converter using a delay-locked loop for automatic synchronization of the remaining phases and elimination of external synchronization is reported in [3]. In [4], [5], a four-phase converter with off-chip air-core inductors on package is introduced. A highly integrated step-up multiphase converter with a high-voltage-tolerant digitally assisted controller is presented in [6]. A 100 MHz four-phase fully integrated buck converter equipped with standard package bondwire inductors and a flying capacitor topology for chip-area reduction is proposed in [7]. A pseudo-ramp current balance technique is presented for a voltage-mode dual-phase buck converter in [8]. A phase-shedding technique for adjusting the operational phase number according to the load current condition is introduced to enhance the light-load efficiency of high-power multiphase converters in [9]. A two-phase, four-segment dc-dc converter employing phase-shedding/segmentation and a resonance gate driver is proposed to improve light-load efficiency in [10].
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Fig. 1. Average load profile of a typical smartphone.
Fig. 3. Block diagram of peak current control.
Fig. 2. Conventional operation of the multiphase converter with phase shedding: (a) heavy load and (b) light load.
Fig. 1 shows a typical load profile of a smartphone [11]. As shown in Fig. 1, the smart mobile device usually operates in standby mode or under light-load conditions, except during short busy periods. Therefore, additional power management is required to reduce unnecessary power consumption under light-load conditions when a multiphase dc-dc converter is used as a power management circuit for smart mobile devices. The phase-shedding technique can help improve the efficiency of multiphase dc-dc converters over a wide load range [9], [10]. The number of operating phases decreases when the load current is reduced, and a single phase will be connected eventually to the load system during a light-load condition. Inasmuch as mobile electronic devices usually operate in standby mode or under light-load conditions, as shown in Fig. 1, the switching stress of only one phase in the multiphase dc-dc converter increases compared to other phases, resulting in phase imbalance and long-term reliability issues. This issue can cause degradation in the system’s performance with respect to voltage ripple, current capability, and thermal dissipation, which are advantages of the multiphase converter topology. This paper presents a multiphase dc-dc converter for the efficient light-load control and verifies its operation through circuit implementation and measurements. The converter has four phases for high current capability, and its output is stepped
Fig. 4. Waveforms on the and the rest of the phases ( F,
degradations of power transistors between PH0 , , , nH, MHz).
down to a low voltage level. The converter also implements both pulse width modulation (PWM) and pulse frequency modulation (PFM) for high efficiency in a wide load range. This work proposes a rotating phase-shedding scheme for the distribution of the switching stress into all four phases instead of only one phase under light-load conditions. Section II explains the proposed rotating phase-shedding scheme. Section III presents the circuit details of the proposed multiphase converter. The measurement results are given in Section IV, and the conclusion is presented in Section V. II. A MULTIPHASE BUCK CONVERTER WITH A ROTATING PHASE-SHEDDING SCHEME A. Reliability Issue of Previous Phase-Shedding Scheme CMOS devices are affected by many reliability mechanisms such as negative bias temperature instability (NBTI), hot car-
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Fig. 5. Proposed rotating phase-shedding scheme under light-load conditions: (a) block diagram and (b) its waveforms.
Fig. 6. Simulation results of stress time versus PMOS threshold voltage in PH0: (a) a multiphase buck converter, (b) illustration of aging simulation, (c) aging , and (d) aging curves for ( F, nH, MHz). curves for
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rier injection (HCI), and time-dependent dielectric breakdown (TDDB) [12], [13]. The increased threshold voltage of the PMOS transistor is a common aging effect due to the applied voltage stress [13]. Increased due to NBTI and HCI stresses in a switching dc-dc converter is directly related to the increased on-resistance of the power transistors. Fig. 2 illustrates the conventional operation of a multiphase converter with phase shedding under heavy- and light-load conditions. As explained in [9], [10], the phase-shedding technique can maximize the multiphase converter’s efficiency by adjusting the number of operating phases depending on the load current. Power is supplied to the output through the switching activity of PH0 only at the light-load conditions as shown in Fig. 2(b). The heavy use of PH0 can lead to acceleration of the aging effect on PH0 compared to other phases. The potential phase imbalance and long-term reliability of the multiphase converter will result from the heavy use of only one phase. The current mode control has been widely used to design dc-dc converters [14]. The basic current-mode controller and its variations [15]–[18] can be used for the current sharing in multiphase converters. The current-sensing circuit is a basic building block of these controllers by the nature of the current-mode control. Fig. 3 shows the block diagram of the peak current control used in this work. A peak current mode control, which has the advantages of a simple design and little effect on device parameters, is one of the popular methods for current sharing among the phases [19]. The conventional phase-shedding scheme, however, causes intensive stress and aging only on PH0 at the lightload condition. Since the aging effect introduces an increased threshold voltage of the transistor, the matching of each phase in the multiphase converter will be destroyed by the heavy use of the single phase. The effect of the mismatch is simulated in Fig. 4. The increase in the threshold voltage from the aging effect could be as large as 100 mV or 200 mV for the heavily used phase, and Fig. 4 shows the results of unbalanced inductor current from the mismatch of each phase. The usual current sensing circuits [15], [16] have a sensing MOSFET in parallel with the PMOS power transistor, and the sensing MOSFET is always in a deep triode region, which means that it always experiences high stress without recovery time. Therefore, following a long aging effect on the heavily used phase, the current sensing accuracy also degrades. The large increase in the threshold voltage of the single switching phase in the conventional phase-shedding scheme also implies the degradation of the power conversion efficiency. Therefore, the switching activity needs to be distributed for the phase balance as well as the long-term reliability of multiphase converters. B. Proposed Rotating Phase-Shedding Scheme Fig. 5 shows a conceptual block diagram of a rotating phase-shedding scheme for distribution of switching activity under light-load conditions. Balanced control of the phases under light-load conditions is achieved by rotating all phases in sequence, which is possible by sequentially enabling only one phase, as shown in Fig. 5(b). When the converter begins PFM operation under a light load, the controller selects one switching phase and shuts down the other three phases. This sequential operation means that the proposed approach can distribute switching stress over all the phases for phase balance
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 49, NO. 11, NOVEMBER 2014
Fig. 7. Efficiency degradation under PFM operation (at mV, mV, , and
).
without degrading the output voltage regulation characteristics. The main purpose of the proposed rotating phase-shedding scheme is to distribute the aging effect of the transistors, so the mismatch problem of the off-chip components cannot be alleviated. The inductors and capacitors are off-chip components, and the proposed technique does not solve the mismatches from these off-chip components. Fig. 6 shows the comparison of the aging effects from the conventional and proposed schemes. Both two-phase and fourphase converters are simulated. The MOSFET model reliability analysis (MOSRA) tool in HSPICE [20] is used for aging analysis of the power transistor. The PMOS threshold voltage is increased by the aging effect [12], and the aging effect is determined by several factors such as the voltage conversion ratio and the load current. Since the voltage level across the inductor determines the slope of the inductor current, the low inductor voltage implies a longer PMOS turn-on time for the peak current controller in Fig. 3. This longer on-time of the PMOS transistor means that the stress time will be longer than the recovery time. More load current also implies that the switching period in Fig. 5(b) becomes longer and the shutdown period becomes shorter. The transient time in the simulation indicates the cycle time for one rotation of all four phases. If load current increases, more switching activity at the PFM mode will be required to supply the increased load current, and the rotation cycle of the four phases will become shorter, as shown in the simulation. During the shutdown period, all power transistors are turned off, and this recovery time alleviates the aging effect. The threshold voltage of the PMOS transistor before aging is mV. When only single phase is switching, as in the conventional scheme, the variation of is as large as 230 mV through the period of five years as shown in Fig. 6. The rotating phase shedding distributes the stress among the phases, and the is also equally distributed among the phases. The variation depends on the complex function of several factors for the aging and recovery effects [13], [20], and the four-phase converter shows smaller than the two-phase converter. It can also be expected that the implementation of more than four phases will further reduce the variation.
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Fig. 8. Block diagram of the four-phase dc-dc converter.
The largest variation of in Fig. 6 is used as a simulation condition for Fig. 7. The difference of 76.8 mV in causes difference in efficiency degradation under light-load conditions (PFM mode). The conventional scheme shows a maximum of 2.5% decrease in efficiency due to the higher turn-on resistance caused by the aging effect. The proposed scheme shows a maximum of 0.86% decrease in efficiency by the distribution of the aging effect. Therefore, we can expect the mitigated light-load efficiency degradation, as well as the balanced PWM operation that was discussed in Fig. 4. If the load current is increased further, the operation mode changes to PWM mode and all phases turn-on to supply large load current. The threshold voltages of unused three phases in the conventional scheme increase less than those in the proposed distribution scheme, which implies that the overall conversion efficiency shows insignificant differences at PWM mode. III. CIRCUIT IMPLEMENTATION A. Four-Phase dc-dc Buck Converter Fig. 8 shows the proposed multiphase dc-dc buck converter, which includes four single-phase modulators that are controlled
in an interleaved manner. A peak current control is used for current sharing among the phases [19]. Each phase in the proposed converter consists of power switches, a gate driver, a current-sensing circuit [16] for peak current control, and circuits for PWM/PFM mode operation. Each phase is controlled by enable signals generated by the phase-rotation circuit. The converter operates in PWM mode under a heavy load condition. Here, all phases are modulated with a phase difference of 90 . The load located at the output is supplied with large currents through four inductors . and are configured as off-chip resistors for easy control of the output voltage during the test. An error signal , which is the difference between and , is applied equally to each phase. The comparator located in PH0 generates a reset signal by comparing to a summed signal . The rest of the phases conduct the same action for generating reset signals, but each has a phase difference of 90 . When the load current gradually decreases and the buck converter operates under light-load conditions, the mode decision circuit changes the operation mode of the converter from PWM to PFM. Once the mode is changed to PFM, the remaining phases, except one active phase, are disabled to reduce power loss. Unnecessary
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Fig. 9. Block diagram of the PFM-mode buck converter.
blocks are also powered down during the PFM operation. From this point, a single-phase buck converter regulates the output voltage. Unlike the conventional phase-shedding architecture, each phase in the proposed multiphase buck converter sequentially operates, using the phase-rotation control under a light load. Therefore, the switching stress concentrated on PH0 can be distributed over all the phases. B. Control Circuits With decreasing load current, the proposed multiphase converter automatically enters into PFM mode. The switching activity of the buck converter depends on the load current condition at PFM mode. Fig. 9 illustrates a simplified block diagram of a PFM-mode buck converter. When the multiphase converter operates in the pre-determined light-load state, the PWM/PFM detector converts the mode signal from high to low after certain intervals determined by an internal counter. The PFM control monitors and regulates the output voltage; the monitoring includes both switching and shutdown periods during the PFM operation. When the converter enters the switching period, the output voltage is controlled by peak current control, which determines the reset timing of the SR latch by comparing the sensing voltage to the peak current threshold, as shown in Fig. 9. The shutdown period begins when the output voltage rises above the high boundary voltage . During the shutdown period, the PFM control turns off both PMOS and NMOS power switches. The PFM control circuit in Fig. 9 generates the signal, which determines the switching and shutdown periods. The repeat of the switching and shutdown periods in PFM mode regulates the buck converter’s output voltage within the boundary.
Fig. 10 shows the phase-rotation circuit and its corresponding waveforms. The proposed converter sequentially transmits to each phase using signals generated by the phase-rotation circuit in Fig. 10(a). Therefore, each phase can share the switching period in sequence for distributed switching activity, as shown in Fig. 10(b). Fig. 11 illustrates the circuit that generates clock signals required for the proposed four-phase buck converter. In the designed converter, each phase operates at a switching frequency of 2 MHz. To make this possible, the four-phase clock generator includes a clock generator that generates 8 MHz and digital logics. The short pulse circuit in Fig. 11 generates the set clock signal of 2 MHz, which is required for each phase of the multiphase converter. During the shutdown period in PFM mode, the clock circuit is also powered down to minimize quiescent current by using the signal from the circuit in Fig. 9. Differences usually occur in control mechanisms and hardware implementation of PWM controllers, especially depending on voltage mode or current mode [14]. Each voltage mode or current mode also has slight variations in control hardware. However, the PFM controllers usually have a relatively simple mechanism, and Fig. 10 and Fig. 11 show most of the extra hardware needed to implement the rotating phase-shedding scheme. If the gate driver circuit for power switches is poorly designed with a CMOS tapered buffer [21], a huge shoot-through current, which is an unwanted power loss in dc-dc converters, will flow through PMOS and NMOS power transistors during each switching transition. Therefore, a gate driver with dead-time delay is needed to reduce shoot-though current loss. Fig. 12 shows the gate driver circuit used in each phase of the proposed multiphase converter. Since the CMOS tapered buffer [21] would have series of large inverters, the switching noise
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Fig. 10. (a) Phase-rotation circuit and (b) its corresponding waveforms.
Fig. 11. Four-phase clock generator.
and shoot-through current would be higher than the designed gate driver. In Fig. 12(a), when rises due to fast path through M1, also rises though the slow path of M1 and
falls due to the fast path through M4, M2. When also falls using the slow path through M3 and M4 as shown in Fig. 12(b). Here, the size of M2 and M3 can be adjusted to
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Fig. 12. Gate driver circuit: (a) charging, (b) discharging, (c) dead-time control, and (d) simulation results.
Fig. 13. Layout and micrograph of a chip.
control the dead-time delays. Fig. 12(c) shows the dead-time control circuit. The simulated waveforms of the gate driver are displayed in Fig. 12(d). The gate driving signals and with dead-time delays are generated so that the PMOS and NMOS power transistors do not turn on simultaneously, avoiding a large shoot-through current. IV. MEASUREMENT RESULTS The multiphase dc-dc buck converter is designed and fabricated using a 0.18 bipolar CMOS DMOS (BCD) process. A buck converter includes four phases for high current capability. For efficient light-load control, the proposed converter employs the rotating phase-shedding scheme in PFM mode. Fig. 13 displays the layout and the micrograph of the proposed
Fig. 14. (a) Evaluation board and (b) cross-section of a QFN package on a PCB.
converter. The entire silicon area, including the bonding pads, is . Fig. 14 shows an evaluation board and the cross-section of a quad-flat-no-leads (QFN) package on a printed circuit board (PCB). The fabricated converter was packaged using a QFN package. As the converter can supply large currents to load circuits, thermal management is crucial for ensuring the converter’s desired performance. The QFN package used for the proposed converter includes a thermal pad at the center. Additionally, multiple thermal vias on the PCB are required for smooth heat dissipation of the chip, as illustrated in Fig. 14(b). For easier achievement of a high-power supply and better thermal management, a 1-oz board is used. The switching stress concentrated on PH0 under light-load conditions, as shown in Fig. 2, is distributed by having each phase in the proposed converter sequentially perform the
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TABLE I SUMMARY OF PERFORMANCE
Fig. 15. Measured waveforms of SW nodes in PFM mode.
Fig. 16. Measured load regulation waveform.
switching activity using the rotating phase-shedding scheme. Fig. 15 displays the waveform of SW nodes in each phase during the operation of the proposed multiphase buck converter in PFM mode. The waveform shows that the switching operation of the proposed converter is not limited to under a light-load condition but is distributed from to by using the phase-rotation circuit in Fig. 10(a). Fig. 16 shows the measured output voltage waveform of the converter with respect to the variation in the load current; the load current varies between 150 mA and 3.7 A, with , , and MHz. The voltage waveform shows both PWM and PFM operations depending on the load current level. The PFM operation has both switching period and shutdown period, as shown in Fig. 10(b), and the waveform in Fig. 16 clearly verifies these periods. The measured waveform shows that the output voltage of the proposed converter is well controlled under wide load current changes. Fig. 16 also shows that the applied rotating phase-shedding scheme does not influence transient characteristics of the converter. Table I outlines the performance of the fabricated chip. The proposed converter has four phases to enable a high current supply and a dual mode (PWM/PFM) operation to improve the
light-load efficiency. The input voltage ranges from 2.7 V to 5 V, and each phase operates at a switching frequency of 2 MHz. The maximum allowable output current is 4.5 A. The load regulation is 4.83 mV/A at a load range of 0.3 A to 4.5 A. The line regulation is 0.78 mV/V at a supply voltage variation of 2.3 V. Fig. 17 illustrates the measured power conversion efficiencies. For each conversion state, the peak efficiencies are measured as 86.5% and 91.6%. The measurement results also show significant improvement of efficiencies by using the PFM operation in the light load conditions. This work and prior studies are compared in Table II. All dc-dc converters presented in [3], [5], [7], [8], [10] were fabricated using CMOS processes. Most studies use high switching frequencies for LC filter size reduction and a fast response, and have comparable output current capabilities. Hysteretic, unlatched PWM, and voltage-mode (VM) control techniques are used for output regulations. Moreover, multiphase topologies are used for high current driving capability and low output voltage ripples. In [7], [10], phase-shedding schemes are used to improve light-load efficiencies. In [8], the switching frequency of 600 kHz is used for each phase and maximum load current is 2 A. The proposed current-mode (CM) converter includes four phases and can provide a high output current of 4.5 A. The converter has a single battery voltage range and high efficiency, over 90%. Unlike other studies, this work includes both PWM and PFM controls for high efficiency in a wide load range and implements a rotating phase-shedding scheme for phase balance and long-term reliability of the multiphase converter. V. CONCLUSION This paper presents a multiphase CM buck converter for APs that require high current at low battery voltage. The proposed converter includes four phases that enable a high current capability, and it has a dual mode function to increase heavyand light-load efficiencies. The controller implements a rotating phase-shedding scheme to alleviate a potential phase imbalance issue caused by concentrated switching stress on one phase only under light-load conditions. The switching stress is distributed by having each phase sequentially perform a switching activity
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Fig. 17. Measured efficiencies: (a)
,
, (b)
,
.
TABLE II PERFORMANCE COMPARISON OF INTEGRATED MULTIPHASE BUCK CONVERTERS
in PFM mode. The functionality of the proposed converter with a rotating phase-shedding scheme is verified through circuit implementation and measurement results. REFERENCES [1] W. Kim, D. Brooks, and G.-Y. Wei, “A fully-integrated 3-level DC-DC converter for nanosecond-scale DVFS,” IEEE J. Solid-State Circuits, vol. 47, no. 1, pp. 206–219, Jan. 2012. [2] J. Wibben and R. Harjani, “A high-efficiency DC-DC converter using 2 nH integrated inductors,” IEEE J. Solid-State Circuits, vol. 43, no. 4, pp. 844–854, Apr. 2008. [3] P. Li, L. Xue, P. Hazucha, T. Karnik, and R. Bashirullah, “A delay-locked loop synchronization scheme for high-frequency multiphase hysteretic DC-DC converters,” IEEE J. Solid-State Circuits, vol. 44, no. 11, pp. 3131–3145, Nov. 2009. [4] P. Hazucha et al., “A 233-MHz 80%–87% efficient four-phase DC-DC converter utilizing air-core inductors on package,” IEEE J. Solid-State Circuits, vol. 40, no. 4, pp. 838–845, Apr. 2005. [5] N. Sturcken et al., “A switched-inductor integrated voltage regulator with nonlinear feedback and network-on-chip load in 45 nm SOI,” IEEE J. Solid-State Circuits, vol. 47, no. 8, pp. 1935–1945, Aug. 2012. [6] D. Bhatia, L. Xue, P. Li, Q. Wu, and R. Bashirullah, “High-voltage tolerant digitally aided DCM/PWM multiphase DC-DC boost converter with integrated Schottky diodes in 0.13 m 1.2 V digital CMOS process,” IEEE J. Solid-State Circuits, vol. 48, no. 3, pp. 774–789, Mar. 2013. [7] C. Huang and P. K. T. Mok, “A 100 MHz 82.4% efficiency packagebondwire based four-phase fully-integrated Buck converter with flying capacitor for area reduction,” IEEE J. Solid-State Circuits, vol. 48, no. 12, pp. 2977–2988, Dec. 2013.
[8] Y.-P. Su, W.-C. Chen, Y.-P. Huang, Y.-H. Lee, K.-H. Chen, and H.-Y. Luo, “Pseudo-ramp current balance (PRCB) technique with offset cancellation control (OCC) in dual-phase DC-DC buck converter,” IEEE Trans. Very Large Scale Integr. Syst., accepted for publication. [9] J. T. Su and C. W. Liu, “A novel phase-shedding control scheme for improved light load efficiency of multiphase interleaved DC-DC converters,” IEEE Trans. Power Electron., vol. 28, no. 10, pp. 4742–4752, Oct. 2013. [10] H. Peng, D. I. Anderson, and M. M. Hella, “A 100 MHz two-phase four-segment DC-DC converter with light load efficiency enhancement in 0.18 m CMOS,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 60, no. 8, pp. 2213–2224, Aug. 2013. [11] Texas Instruments Application Report SLUA538, 2009 [Online]. Available: http://www.ti.com [12] J. Keane, X. Wang, D. Persaud, and C. H. Kim, “An all-in-one silicon odometer for separately monitoring HCI, BTI, and TDDB,” IEEE J. Solid-State Circuits, vol. 45, no. 4, pp. 817–829, Apr. 2010. [13] P. D. Wit and G. Gielen, “Degradation-resilient design of a self-healing xDSL line driver in 90 nm CMOS,” IEEE J. Solid-State Circuits, vol. 47, no. 7, pp. 1757–1767, Jul. 2012. [14] R. W. Erickson and D. Maksimovic, Fundamentals of Power Electronics, 2nd ed. Berlin, Germany: Springer, 2001. [15] C. F. Lee and P. K. T. Mok, “A monolithic current-mode CMOS DC-DC converter with on-chip current-sensing technique,” IEEE J. Solid-State Circuits, vol. 39, no. 1, pp. 3–14, Jan. 2004. [16] C. Y. Leung, P. K. T. Mok, K. N. Leung, and M. Chan, “An integrated CMOS current-sensing circuit for low-voltage current-mode buck regulator,” IEEE Trans. Circuits Syst. II, vol. 52, no. 7, pp. 394–397, Jul. 2005. [17] M. Du, H. Lee, and J. Liu, “A 5-MHz 91% peak-power-efficiency buck regulator with auto-selectable peak- and valley-current control,” IEEE J. Solid-State Circuits, vol. 46, no. 8, pp. 1928–1939, Aug. 2011.
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[18] M. P. Chan and P. K. T. Mok, “On-chip digital inductor current sensor for monolithic digitally controlled DC-DC converter,” IEEE J. SolidState Circuits, vol. 46, no. 8, pp. 1928–1939, Aug. 2011. [19] X. Zhou, P. Xu, and F. C. Lee, “A novel current-sharing control technique for low-voltage high-current voltage regulator module applications,” IEEE Trans. Power Electron., vol. 15, no. 6, pp. 1153–1162, Nov. 2000. [20] B. Tudor, J. Wang, W. Liu, and H. Elhak, “MOS device aging analysis with HSPICE and CustomSim,” Synopsys, White Paper, Aug. 2011. [21] N. Li, F. Haviland, and A. Tuszynski, “CMOS tapered buffer,” IEEE J. Solid-State Circuits, vol. 25, no. 4, pp. 1005–1008, Aug. 1990.
Youngkook Ahn received the B.S. degree in electronic and electrical engineering science, Kyeongsang National University, Jinjoo, Korea, in 2006. He received the M.S and Ph.D. degrees in electrical engineering and computer science, Hanyang University, Ansan, Korea, in 2009 and 2014, respectively. He is now with Dongbu-Hitek, Seoul, Korea, as a Senior Researcher, where he has been involved in the Smart Power IC Design Part. His research interests include power management circuits and mixedsignal integrated circuits.
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Inho Jeon received the B.S. and M.S. degrees in electronics and communication engineering from Hanyang University, Ansan, Korea, in 2012 and 2014, respectively. He is currently working towards the Ph.D. degree in the same university. His current research interests include power management circuits and mixed-signal integrated circuits.
Jeongjin Roh (M’01–SM’10) received the B.S degree in electrical engineering from Hanyang University, Seoul, Korea, in 1990, the M.S. degree in electrical engineering from the Pennsylvania State University, State College, PA, USA, in 1998, and the Ph.D. degree in computer engineering from the University of Texas at Austin, TX, USA, in 2001. From 1990 to 1996, he was with Samsung Electronics, Kiheung, Korea, as a Senior Circuit Designer for mixed-signal products. From 2000 to 2001, he was with Intel Corporation, Austin, Texas, as a Senior Analog Designer for delta-sigma data converters. In 2001, he joined the faculty of Hanyang University, Ansan, Korea. His research interests include power management circuits and oversampled delta-sigma converters.
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A Multiphase Buck Converter With a Rotating Phase-Shedding Scheme For Efficient Light-Load Control Youngkook Ahn, Inho Jeon, and Jeongjin Roh, Senior Member, IEEE
Abstract—Mobile devices need to minimize their power consumption in order to maximize battery runtime, except during short extremely busy periods. This requirement makes dc-dc converters usually operate in standby mode or under light-load conditions. Therefore, implementation of an efficient regulation scheme under a light load is a key aspect of dc-dc converter design. This paper presents a multiphase buck converter with a rotating phase-shedding scheme for efficient light-load control. The converter includes four phases operating in an interleaved manner in order to supply high current with low output ripple. The multiphase converter implements a rotating phase-shedding scheme to distribute the switching activity concentrated on a single phase, resulting in a distribution of the aging effects among the phases instead of a single phase. The proposed multiphase buck converter was fabricated using a 0.18 µm bipolar CMOS DMOS process. The supply voltage ranges from 2.7 V to 5 V, and the maximum allowable output current is 4.5 A. Index Terms—Efficient light-load control, multiphase dc-dc converter, PFM control, rotating phase shedding.
I. INTRODUCTION
T
HE EMERGENCE of smart phones, tablet PCs, and other advanced devices has led to the rapid growth of the smart mobile market. The performance of smart mobile devices depends entirely on their application processor (AP). Smart mobile devices are required to have significant processing power in order to support their multiple functions. Since most smart devices are operated with batteries, managing power consumption while meeting the requirements of each function has been considered one of the most crucial issues in designing smart mobile devices. In the past, processing performance was improved simply by raising the clock speed. However, this approach puts constraints on performance due to additional heat generation and power consumption. Multi-core processors have recently emerged due to advancements in very-large-scale integration
Manuscript received March 15, 2014; revised June 30, 2014 and September 12, 2014; accepted September 20, 2014. Date of current version October 24, 2014. This work was supported in part by the Ministry of Knowledge Economy, Korea, under the University ITRC support program supervised by the National IT Industry Promotion Agency (NIPA-2014-H0301-14-1007), and supported in part by the Industrial Core Technology Development Program (10049095, “Development of Fusion Power Management Platforms and Solutions for Smart Connected Devices”) funded by the Ministry of Trade, Industry and Energy. The authors are with the Department of Electrical Engineering, Hanyang University, Ansan 426-791, Korea (e-mail: [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/JSSC.2014.2360400
technology. Theses multi-core platforms are becoming dominant in providing sufficient processing power and flexibility to smart mobile devices. A high-performance AP has a system-level power management unit that efficiently manages power utilization and reduces unnecessary power consumption. Representative system-level technologies include power gating and dynamic voltage and frequency scaling [1]. These technologies, which decrease unnecessary leakage and dynamic power, are widely used for processors that require high performance. The APs of smart mobile devices are required to have high-performance dc-dc converters as well as system-level power management techniques in order to support high current density and other stringent power constraints. The inductor-type switching dc-dc converters are widely and advantageously used because of their high efficiency and high power capability. However, there are limitations in terms of current driving capability and thermal management when only a single-phase dc-dc converter is used for a high-performance AP. Comparison of single-phase and multiphase dc-dc converters confirm that the latter are beneficial due to higher current driving capability, a smaller output voltage ripple, a faster transient response, and improved thermal management. Therefore, multiphase dc-dc converters are good candidates for smart mobile devices that require greater performance. Several advanced studies about multiphase dc-dc converters have been conducted. The design and analysis of a fully integrated multiphase buck converter with on-chip filter inductors and capacitors are presented in [2]. A high-frequency multiphase hysteretic dc-dc converter using a delay-locked loop for automatic synchronization of the remaining phases and elimination of external synchronization is reported in [3]. In [4], [5], a four-phase converter with off-chip air-core inductors on package is introduced. A highly integrated step-up multiphase converter with a high-voltage-tolerant digitally assisted controller is presented in [6]. A 100 MHz four-phase fully integrated buck converter equipped with standard package bondwire inductors and a flying capacitor topology for chip-area reduction is proposed in [7]. A pseudo-ramp current balance technique is presented for a voltage-mode dual-phase buck converter in [8]. A phase-shedding technique for adjusting the operational phase number according to the load current condition is introduced to enhance the light-load efficiency of high-power multiphase converters in [9]. A two-phase, four-segment dc-dc converter employing phase-shedding/segmentation and a resonance gate driver is proposed to improve light-load efficiency in [10].
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Fig. 1. Average load profile of a typical smartphone.
Fig. 3. Block diagram of peak current control.
Fig. 2. Conventional operation of the multiphase converter with phase shedding: (a) heavy load and (b) light load.
Fig. 1 shows a typical load profile of a smartphone [11]. As shown in Fig. 1, the smart mobile device usually operates in standby mode or under light-load conditions, except during short busy periods. Therefore, additional power management is required to reduce unnecessary power consumption under light-load conditions when a multiphase dc-dc converter is used as a power management circuit for smart mobile devices. The phase-shedding technique can help improve the efficiency of multiphase dc-dc converters over a wide load range [9], [10]. The number of operating phases decreases when the load current is reduced, and a single phase will be connected eventually to the load system during a light-load condition. Inasmuch as mobile electronic devices usually operate in standby mode or under light-load conditions, as shown in Fig. 1, the switching stress of only one phase in the multiphase dc-dc converter increases compared to other phases, resulting in phase imbalance and long-term reliability issues. This issue can cause degradation in the system’s performance with respect to voltage ripple, current capability, and thermal dissipation, which are advantages of the multiphase converter topology. This paper presents a multiphase dc-dc converter for the efficient light-load control and verifies its operation through circuit implementation and measurements. The converter has four phases for high current capability, and its output is stepped
Fig. 4. Waveforms on the and the rest of the phases ( F,
degradations of power transistors between PH0 , , , nH, MHz).
down to a low voltage level. The converter also implements both pulse width modulation (PWM) and pulse frequency modulation (PFM) for high efficiency in a wide load range. This work proposes a rotating phase-shedding scheme for the distribution of the switching stress into all four phases instead of only one phase under light-load conditions. Section II explains the proposed rotating phase-shedding scheme. Section III presents the circuit details of the proposed multiphase converter. The measurement results are given in Section IV, and the conclusion is presented in Section V. II. A MULTIPHASE BUCK CONVERTER WITH A ROTATING PHASE-SHEDDING SCHEME A. Reliability Issue of Previous Phase-Shedding Scheme CMOS devices are affected by many reliability mechanisms such as negative bias temperature instability (NBTI), hot car-
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Fig. 5. Proposed rotating phase-shedding scheme under light-load conditions: (a) block diagram and (b) its waveforms.
Fig. 6. Simulation results of stress time versus PMOS threshold voltage in PH0: (a) a multiphase buck converter, (b) illustration of aging simulation, (c) aging , and (d) aging curves for ( F, nH, MHz). curves for
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rier injection (HCI), and time-dependent dielectric breakdown (TDDB) [12], [13]. The increased threshold voltage of the PMOS transistor is a common aging effect due to the applied voltage stress [13]. Increased due to NBTI and HCI stresses in a switching dc-dc converter is directly related to the increased on-resistance of the power transistors. Fig. 2 illustrates the conventional operation of a multiphase converter with phase shedding under heavy- and light-load conditions. As explained in [9], [10], the phase-shedding technique can maximize the multiphase converter’s efficiency by adjusting the number of operating phases depending on the load current. Power is supplied to the output through the switching activity of PH0 only at the light-load conditions as shown in Fig. 2(b). The heavy use of PH0 can lead to acceleration of the aging effect on PH0 compared to other phases. The potential phase imbalance and long-term reliability of the multiphase converter will result from the heavy use of only one phase. The current mode control has been widely used to design dc-dc converters [14]. The basic current-mode controller and its variations [15]–[18] can be used for the current sharing in multiphase converters. The current-sensing circuit is a basic building block of these controllers by the nature of the current-mode control. Fig. 3 shows the block diagram of the peak current control used in this work. A peak current mode control, which has the advantages of a simple design and little effect on device parameters, is one of the popular methods for current sharing among the phases [19]. The conventional phase-shedding scheme, however, causes intensive stress and aging only on PH0 at the lightload condition. Since the aging effect introduces an increased threshold voltage of the transistor, the matching of each phase in the multiphase converter will be destroyed by the heavy use of the single phase. The effect of the mismatch is simulated in Fig. 4. The increase in the threshold voltage from the aging effect could be as large as 100 mV or 200 mV for the heavily used phase, and Fig. 4 shows the results of unbalanced inductor current from the mismatch of each phase. The usual current sensing circuits [15], [16] have a sensing MOSFET in parallel with the PMOS power transistor, and the sensing MOSFET is always in a deep triode region, which means that it always experiences high stress without recovery time. Therefore, following a long aging effect on the heavily used phase, the current sensing accuracy also degrades. The large increase in the threshold voltage of the single switching phase in the conventional phase-shedding scheme also implies the degradation of the power conversion efficiency. Therefore, the switching activity needs to be distributed for the phase balance as well as the long-term reliability of multiphase converters. B. Proposed Rotating Phase-Shedding Scheme Fig. 5 shows a conceptual block diagram of a rotating phase-shedding scheme for distribution of switching activity under light-load conditions. Balanced control of the phases under light-load conditions is achieved by rotating all phases in sequence, which is possible by sequentially enabling only one phase, as shown in Fig. 5(b). When the converter begins PFM operation under a light load, the controller selects one switching phase and shuts down the other three phases. This sequential operation means that the proposed approach can distribute switching stress over all the phases for phase balance
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Fig. 7. Efficiency degradation under PFM operation (at mV, mV, , and
).
without degrading the output voltage regulation characteristics. The main purpose of the proposed rotating phase-shedding scheme is to distribute the aging effect of the transistors, so the mismatch problem of the off-chip components cannot be alleviated. The inductors and capacitors are off-chip components, and the proposed technique does not solve the mismatches from these off-chip components. Fig. 6 shows the comparison of the aging effects from the conventional and proposed schemes. Both two-phase and fourphase converters are simulated. The MOSFET model reliability analysis (MOSRA) tool in HSPICE [20] is used for aging analysis of the power transistor. The PMOS threshold voltage is increased by the aging effect [12], and the aging effect is determined by several factors such as the voltage conversion ratio and the load current. Since the voltage level across the inductor determines the slope of the inductor current, the low inductor voltage implies a longer PMOS turn-on time for the peak current controller in Fig. 3. This longer on-time of the PMOS transistor means that the stress time will be longer than the recovery time. More load current also implies that the switching period in Fig. 5(b) becomes longer and the shutdown period becomes shorter. The transient time in the simulation indicates the cycle time for one rotation of all four phases. If load current increases, more switching activity at the PFM mode will be required to supply the increased load current, and the rotation cycle of the four phases will become shorter, as shown in the simulation. During the shutdown period, all power transistors are turned off, and this recovery time alleviates the aging effect. The threshold voltage of the PMOS transistor before aging is mV. When only single phase is switching, as in the conventional scheme, the variation of is as large as 230 mV through the period of five years as shown in Fig. 6. The rotating phase shedding distributes the stress among the phases, and the is also equally distributed among the phases. The variation depends on the complex function of several factors for the aging and recovery effects [13], [20], and the four-phase converter shows smaller than the two-phase converter. It can also be expected that the implementation of more than four phases will further reduce the variation.
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Fig. 8. Block diagram of the four-phase dc-dc converter.
The largest variation of in Fig. 6 is used as a simulation condition for Fig. 7. The difference of 76.8 mV in causes difference in efficiency degradation under light-load conditions (PFM mode). The conventional scheme shows a maximum of 2.5% decrease in efficiency due to the higher turn-on resistance caused by the aging effect. The proposed scheme shows a maximum of 0.86% decrease in efficiency by the distribution of the aging effect. Therefore, we can expect the mitigated light-load efficiency degradation, as well as the balanced PWM operation that was discussed in Fig. 4. If the load current is increased further, the operation mode changes to PWM mode and all phases turn-on to supply large load current. The threshold voltages of unused three phases in the conventional scheme increase less than those in the proposed distribution scheme, which implies that the overall conversion efficiency shows insignificant differences at PWM mode. III. CIRCUIT IMPLEMENTATION A. Four-Phase dc-dc Buck Converter Fig. 8 shows the proposed multiphase dc-dc buck converter, which includes four single-phase modulators that are controlled
in an interleaved manner. A peak current control is used for current sharing among the phases [19]. Each phase in the proposed converter consists of power switches, a gate driver, a current-sensing circuit [16] for peak current control, and circuits for PWM/PFM mode operation. Each phase is controlled by enable signals generated by the phase-rotation circuit. The converter operates in PWM mode under a heavy load condition. Here, all phases are modulated with a phase difference of 90 . The load located at the output is supplied with large currents through four inductors . and are configured as off-chip resistors for easy control of the output voltage during the test. An error signal , which is the difference between and , is applied equally to each phase. The comparator located in PH0 generates a reset signal by comparing to a summed signal . The rest of the phases conduct the same action for generating reset signals, but each has a phase difference of 90 . When the load current gradually decreases and the buck converter operates under light-load conditions, the mode decision circuit changes the operation mode of the converter from PWM to PFM. Once the mode is changed to PFM, the remaining phases, except one active phase, are disabled to reduce power loss. Unnecessary
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Fig. 9. Block diagram of the PFM-mode buck converter.
blocks are also powered down during the PFM operation. From this point, a single-phase buck converter regulates the output voltage. Unlike the conventional phase-shedding architecture, each phase in the proposed multiphase buck converter sequentially operates, using the phase-rotation control under a light load. Therefore, the switching stress concentrated on PH0 can be distributed over all the phases. B. Control Circuits With decreasing load current, the proposed multiphase converter automatically enters into PFM mode. The switching activity of the buck converter depends on the load current condition at PFM mode. Fig. 9 illustrates a simplified block diagram of a PFM-mode buck converter. When the multiphase converter operates in the pre-determined light-load state, the PWM/PFM detector converts the mode signal from high to low after certain intervals determined by an internal counter. The PFM control monitors and regulates the output voltage; the monitoring includes both switching and shutdown periods during the PFM operation. When the converter enters the switching period, the output voltage is controlled by peak current control, which determines the reset timing of the SR latch by comparing the sensing voltage to the peak current threshold, as shown in Fig. 9. The shutdown period begins when the output voltage rises above the high boundary voltage . During the shutdown period, the PFM control turns off both PMOS and NMOS power switches. The PFM control circuit in Fig. 9 generates the signal, which determines the switching and shutdown periods. The repeat of the switching and shutdown periods in PFM mode regulates the buck converter’s output voltage within the boundary.
Fig. 10 shows the phase-rotation circuit and its corresponding waveforms. The proposed converter sequentially transmits to each phase using signals generated by the phase-rotation circuit in Fig. 10(a). Therefore, each phase can share the switching period in sequence for distributed switching activity, as shown in Fig. 10(b). Fig. 11 illustrates the circuit that generates clock signals required for the proposed four-phase buck converter. In the designed converter, each phase operates at a switching frequency of 2 MHz. To make this possible, the four-phase clock generator includes a clock generator that generates 8 MHz and digital logics. The short pulse circuit in Fig. 11 generates the set clock signal of 2 MHz, which is required for each phase of the multiphase converter. During the shutdown period in PFM mode, the clock circuit is also powered down to minimize quiescent current by using the signal from the circuit in Fig. 9. Differences usually occur in control mechanisms and hardware implementation of PWM controllers, especially depending on voltage mode or current mode [14]. Each voltage mode or current mode also has slight variations in control hardware. However, the PFM controllers usually have a relatively simple mechanism, and Fig. 10 and Fig. 11 show most of the extra hardware needed to implement the rotating phase-shedding scheme. If the gate driver circuit for power switches is poorly designed with a CMOS tapered buffer [21], a huge shoot-through current, which is an unwanted power loss in dc-dc converters, will flow through PMOS and NMOS power transistors during each switching transition. Therefore, a gate driver with dead-time delay is needed to reduce shoot-though current loss. Fig. 12 shows the gate driver circuit used in each phase of the proposed multiphase converter. Since the CMOS tapered buffer [21] would have series of large inverters, the switching noise
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Fig. 10. (a) Phase-rotation circuit and (b) its corresponding waveforms.
Fig. 11. Four-phase clock generator.
and shoot-through current would be higher than the designed gate driver. In Fig. 12(a), when rises due to fast path through M1, also rises though the slow path of M1 and
falls due to the fast path through M4, M2. When also falls using the slow path through M3 and M4 as shown in Fig. 12(b). Here, the size of M2 and M3 can be adjusted to
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Fig. 12. Gate driver circuit: (a) charging, (b) discharging, (c) dead-time control, and (d) simulation results.
Fig. 13. Layout and micrograph of a chip.
control the dead-time delays. Fig. 12(c) shows the dead-time control circuit. The simulated waveforms of the gate driver are displayed in Fig. 12(d). The gate driving signals and with dead-time delays are generated so that the PMOS and NMOS power transistors do not turn on simultaneously, avoiding a large shoot-through current. IV. MEASUREMENT RESULTS The multiphase dc-dc buck converter is designed and fabricated using a 0.18 bipolar CMOS DMOS (BCD) process. A buck converter includes four phases for high current capability. For efficient light-load control, the proposed converter employs the rotating phase-shedding scheme in PFM mode. Fig. 13 displays the layout and the micrograph of the proposed
Fig. 14. (a) Evaluation board and (b) cross-section of a QFN package on a PCB.
converter. The entire silicon area, including the bonding pads, is . Fig. 14 shows an evaluation board and the cross-section of a quad-flat-no-leads (QFN) package on a printed circuit board (PCB). The fabricated converter was packaged using a QFN package. As the converter can supply large currents to load circuits, thermal management is crucial for ensuring the converter’s desired performance. The QFN package used for the proposed converter includes a thermal pad at the center. Additionally, multiple thermal vias on the PCB are required for smooth heat dissipation of the chip, as illustrated in Fig. 14(b). For easier achievement of a high-power supply and better thermal management, a 1-oz board is used. The switching stress concentrated on PH0 under light-load conditions, as shown in Fig. 2, is distributed by having each phase in the proposed converter sequentially perform the
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TABLE I SUMMARY OF PERFORMANCE
Fig. 15. Measured waveforms of SW nodes in PFM mode.
Fig. 16. Measured load regulation waveform.
switching activity using the rotating phase-shedding scheme. Fig. 15 displays the waveform of SW nodes in each phase during the operation of the proposed multiphase buck converter in PFM mode. The waveform shows that the switching operation of the proposed converter is not limited to under a light-load condition but is distributed from to by using the phase-rotation circuit in Fig. 10(a). Fig. 16 shows the measured output voltage waveform of the converter with respect to the variation in the load current; the load current varies between 150 mA and 3.7 A, with , , and MHz. The voltage waveform shows both PWM and PFM operations depending on the load current level. The PFM operation has both switching period and shutdown period, as shown in Fig. 10(b), and the waveform in Fig. 16 clearly verifies these periods. The measured waveform shows that the output voltage of the proposed converter is well controlled under wide load current changes. Fig. 16 also shows that the applied rotating phase-shedding scheme does not influence transient characteristics of the converter. Table I outlines the performance of the fabricated chip. The proposed converter has four phases to enable a high current supply and a dual mode (PWM/PFM) operation to improve the
light-load efficiency. The input voltage ranges from 2.7 V to 5 V, and each phase operates at a switching frequency of 2 MHz. The maximum allowable output current is 4.5 A. The load regulation is 4.83 mV/A at a load range of 0.3 A to 4.5 A. The line regulation is 0.78 mV/V at a supply voltage variation of 2.3 V. Fig. 17 illustrates the measured power conversion efficiencies. For each conversion state, the peak efficiencies are measured as 86.5% and 91.6%. The measurement results also show significant improvement of efficiencies by using the PFM operation in the light load conditions. This work and prior studies are compared in Table II. All dc-dc converters presented in [3], [5], [7], [8], [10] were fabricated using CMOS processes. Most studies use high switching frequencies for LC filter size reduction and a fast response, and have comparable output current capabilities. Hysteretic, unlatched PWM, and voltage-mode (VM) control techniques are used for output regulations. Moreover, multiphase topologies are used for high current driving capability and low output voltage ripples. In [7], [10], phase-shedding schemes are used to improve light-load efficiencies. In [8], the switching frequency of 600 kHz is used for each phase and maximum load current is 2 A. The proposed current-mode (CM) converter includes four phases and can provide a high output current of 4.5 A. The converter has a single battery voltage range and high efficiency, over 90%. Unlike other studies, this work includes both PWM and PFM controls for high efficiency in a wide load range and implements a rotating phase-shedding scheme for phase balance and long-term reliability of the multiphase converter. V. CONCLUSION This paper presents a multiphase CM buck converter for APs that require high current at low battery voltage. The proposed converter includes four phases that enable a high current capability, and it has a dual mode function to increase heavyand light-load efficiencies. The controller implements a rotating phase-shedding scheme to alleviate a potential phase imbalance issue caused by concentrated switching stress on one phase only under light-load conditions. The switching stress is distributed by having each phase sequentially perform a switching activity
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Fig. 17. Measured efficiencies: (a)
,
, (b)
,
.
TABLE II PERFORMANCE COMPARISON OF INTEGRATED MULTIPHASE BUCK CONVERTERS
in PFM mode. The functionality of the proposed converter with a rotating phase-shedding scheme is verified through circuit implementation and measurement results. REFERENCES [1] W. Kim, D. Brooks, and G.-Y. Wei, “A fully-integrated 3-level DC-DC converter for nanosecond-scale DVFS,” IEEE J. Solid-State Circuits, vol. 47, no. 1, pp. 206–219, Jan. 2012. [2] J. Wibben and R. Harjani, “A high-efficiency DC-DC converter using 2 nH integrated inductors,” IEEE J. Solid-State Circuits, vol. 43, no. 4, pp. 844–854, Apr. 2008. [3] P. Li, L. Xue, P. Hazucha, T. Karnik, and R. Bashirullah, “A delay-locked loop synchronization scheme for high-frequency multiphase hysteretic DC-DC converters,” IEEE J. Solid-State Circuits, vol. 44, no. 11, pp. 3131–3145, Nov. 2009. [4] P. Hazucha et al., “A 233-MHz 80%–87% efficient four-phase DC-DC converter utilizing air-core inductors on package,” IEEE J. Solid-State Circuits, vol. 40, no. 4, pp. 838–845, Apr. 2005. [5] N. Sturcken et al., “A switched-inductor integrated voltage regulator with nonlinear feedback and network-on-chip load in 45 nm SOI,” IEEE J. Solid-State Circuits, vol. 47, no. 8, pp. 1935–1945, Aug. 2012. [6] D. Bhatia, L. Xue, P. Li, Q. Wu, and R. Bashirullah, “High-voltage tolerant digitally aided DCM/PWM multiphase DC-DC boost converter with integrated Schottky diodes in 0.13 m 1.2 V digital CMOS process,” IEEE J. Solid-State Circuits, vol. 48, no. 3, pp. 774–789, Mar. 2013. [7] C. Huang and P. K. T. Mok, “A 100 MHz 82.4% efficiency packagebondwire based four-phase fully-integrated Buck converter with flying capacitor for area reduction,” IEEE J. Solid-State Circuits, vol. 48, no. 12, pp. 2977–2988, Dec. 2013.
[8] Y.-P. Su, W.-C. Chen, Y.-P. Huang, Y.-H. Lee, K.-H. Chen, and H.-Y. Luo, “Pseudo-ramp current balance (PRCB) technique with offset cancellation control (OCC) in dual-phase DC-DC buck converter,” IEEE Trans. Very Large Scale Integr. Syst., accepted for publication. [9] J. T. Su and C. W. Liu, “A novel phase-shedding control scheme for improved light load efficiency of multiphase interleaved DC-DC converters,” IEEE Trans. Power Electron., vol. 28, no. 10, pp. 4742–4752, Oct. 2013. [10] H. Peng, D. I. Anderson, and M. M. Hella, “A 100 MHz two-phase four-segment DC-DC converter with light load efficiency enhancement in 0.18 m CMOS,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 60, no. 8, pp. 2213–2224, Aug. 2013. [11] Texas Instruments Application Report SLUA538, 2009 [Online]. Available: http://www.ti.com [12] J. Keane, X. Wang, D. Persaud, and C. H. Kim, “An all-in-one silicon odometer for separately monitoring HCI, BTI, and TDDB,” IEEE J. Solid-State Circuits, vol. 45, no. 4, pp. 817–829, Apr. 2010. [13] P. D. Wit and G. Gielen, “Degradation-resilient design of a self-healing xDSL line driver in 90 nm CMOS,” IEEE J. Solid-State Circuits, vol. 47, no. 7, pp. 1757–1767, Jul. 2012. [14] R. W. Erickson and D. Maksimovic, Fundamentals of Power Electronics, 2nd ed. Berlin, Germany: Springer, 2001. [15] C. F. Lee and P. K. T. Mok, “A monolithic current-mode CMOS DC-DC converter with on-chip current-sensing technique,” IEEE J. Solid-State Circuits, vol. 39, no. 1, pp. 3–14, Jan. 2004. [16] C. Y. Leung, P. K. T. Mok, K. N. Leung, and M. Chan, “An integrated CMOS current-sensing circuit for low-voltage current-mode buck regulator,” IEEE Trans. Circuits Syst. II, vol. 52, no. 7, pp. 394–397, Jul. 2005. [17] M. Du, H. Lee, and J. Liu, “A 5-MHz 91% peak-power-efficiency buck regulator with auto-selectable peak- and valley-current control,” IEEE J. Solid-State Circuits, vol. 46, no. 8, pp. 1928–1939, Aug. 2011.
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[18] M. P. Chan and P. K. T. Mok, “On-chip digital inductor current sensor for monolithic digitally controlled DC-DC converter,” IEEE J. SolidState Circuits, vol. 46, no. 8, pp. 1928–1939, Aug. 2011. [19] X. Zhou, P. Xu, and F. C. Lee, “A novel current-sharing control technique for low-voltage high-current voltage regulator module applications,” IEEE Trans. Power Electron., vol. 15, no. 6, pp. 1153–1162, Nov. 2000. [20] B. Tudor, J. Wang, W. Liu, and H. Elhak, “MOS device aging analysis with HSPICE and CustomSim,” Synopsys, White Paper, Aug. 2011. [21] N. Li, F. Haviland, and A. Tuszynski, “CMOS tapered buffer,” IEEE J. Solid-State Circuits, vol. 25, no. 4, pp. 1005–1008, Aug. 1990.
Youngkook Ahn received the B.S. degree in electronic and electrical engineering science, Kyeongsang National University, Jinjoo, Korea, in 2006. He received the M.S and Ph.D. degrees in electrical engineering and computer science, Hanyang University, Ansan, Korea, in 2009 and 2014, respectively. He is now with Dongbu-Hitek, Seoul, Korea, as a Senior Researcher, where he has been involved in the Smart Power IC Design Part. His research interests include power management circuits and mixedsignal integrated circuits.
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Inho Jeon received the B.S. and M.S. degrees in electronics and communication engineering from Hanyang University, Ansan, Korea, in 2012 and 2014, respectively. He is currently working towards the Ph.D. degree in the same university. His current research interests include power management circuits and mixed-signal integrated circuits.
Jeongjin Roh (M’01–SM’10) received the B.S degree in electrical engineering from Hanyang University, Seoul, Korea, in 1990, the M.S. degree in electrical engineering from the Pennsylvania State University, State College, PA, USA, in 1998, and the Ph.D. degree in computer engineering from the University of Texas at Austin, TX, USA, in 2001. From 1990 to 1996, he was with Samsung Electronics, Kiheung, Korea, as a Senior Circuit Designer for mixed-signal products. From 2000 to 2001, he was with Intel Corporation, Austin, Texas, as a Senior Analog Designer for delta-sigma data converters. In 2001, he joined the faculty of Hanyang University, Ansan, Korea. His research interests include power management circuits and oversampled delta-sigma converters.
