A New Low Power Test Pattern Generator using a Transition ...
A New Low Power Test Pattern Generator using a Transition Monitoring Window based on BIST Architecture Youbean Kim, Myung-Hoon Yang, Yong Lee, and Sungho Kang Department of Electrical and Electronic Engineering, Yonsei University {inyacio, mhyang, daiginda}@soc.yonsei.ac.kr, [email protected] Abstract This paper presents a new low power BIST TPG scheme. It uses a transition monitoring window (TMW) that is comprised of a transition monitoring window block and a MUX. When random test patterns are generated by an LFSR, transitions of those patterns satisfy pseudo-random Gaussian distribution. The proposed technique represses transitions of patterns using the k-value which is a standard that is obtained from the distribution of TMW to observe over transitive patterns causing high power dissipation in a scan chain. Experimental results show that the proposed BIST TPG schemes can reduce scan transition by about 60% without performance loss in ISCAS’89 benchmark circuits that have large number scan inputs.
1. Introduction A linear feedback shift register (LFSR) is commonly used as a test pattern generator (TPG) in the low overhead Built-in Self Test (BIST). However, because a circuit under test (CUT) may contain many random pattern resistant faults, achieving high performance with pseudo-random patterns generated by an LFSR often requires unacceptably long test sequences [1]. In BIST technology, it is an important issue to achieve high fault coverage and reduce test time. This paper focuses on a low power BIST scheme, another important concern in this field. Test patterns generated by an LFSR have less correlative than those by normal operation. Therefore, when those patterns are applied to a scan chain, excessive switching activity due to low correlation between consecutive test patterns would dissipate more power [2]. When the peak power exceeds the capability that can tolerate in a circuit, the circuit during test application would be permanently damaged due to excessive heat dissipation. So, a peak power problem due to over-
transitive patterns generated by an LFSR is a necessary consideration in a BIST scheme [3]. Several techniques have been proposed to address this problem. A BIST strategy called dual-speed LFSR [4] was proposed to reduce the circuit’s overall switching activities. Having two different speed LFSRs, the proposed strategy applies some test patterns using a low-speed LFSR by connecting to some inputs that have elevated transition densities. However, this will increase test application time. In order to reduce the test length and average power simultaneously, Zhang and Roy proposed a low power random testing technique [5], in which both signal probabilities and activities at the primary inputs are optimized, and both the average power and the test length are reduced significantly. For ISCAS benchmark circuits, while the average of power reduction by using DS-LFSR is 19%, the average of power reduction by using the low power random testing technique in [5] is as high as 78%. The previous techniques are unable to reduce the peak power, since the instantaneous power is not directly related to the average signal activities. The technique associated with the peak power problem is proposed in [6], lowtransition random TPG (LT-RTPG), that is comprised of an LFSR, a k-input AND gate, and a T flip-flop to reduce shifting transition number in a scan chain. By using this approach, about 23~59% of scan shifting can be reduced. This paper presents a new test pattern generator for low power BIST. The proposed technique increases the correlation between test patterns by using a transition monitoring window (TMW). Since test patterns generated by an LFSR almost satisfy pseudo-random Gaussian distribution, the standard, called k-value that is obtained from the distribution can repress transitions of scan shifting in a scan chain using a TMW. It is a comprised of two XORs, a comparator, counter block, and a MUX. It is used to observe over transitive vector sequences in a range of window size. If the patterns in TMW are more transitive than the k-value, the last
vector in an LFSR which sends to a scan chain soon would be converted into high correlation vector. It is a very important problem how to set k-value and TMW size. The method that used in this paper adapted the property of the pseudo-random Gaussian distribution, if sample circuits optimal k-value and TMW size are set, those of another circuits will be similar. Experimental results prove the theory. ISCAS’ 89 benchmark circuits that have a large number of scan inputs and adapted the same k-value and TMW size show almost identical scan shifting transition reduction tendency. The rest of this paper is organized as follows: Section 2 introduces notations used in the paper. In addition, the characteristics of random patterns’ transition distribution are described. In Section 3, it is discussed how k-value and TMW size are set using pseudo Gaussian random distribution of circuits. In Section 4, the logic diagram adapted for the proposed scheme is described. In Section 5, experimental results are reported for ISCAS’ 89 benchmark circuits. And the conclusions are stated in Section 6.
Figure 2. Example of a pattern transition
Figure 3 shows the pattern transition distribution graph of 5000 test patterns generated in s1423, s9234, and s38584 that have 74, 228, and 1452 scan inputs, respectively.
(a) s1423
2. Distribution Characteristic of Random Pattern Transitions Some definitions are needed to understand this paper correctly before discussing the distribution characteristics of random pattern transitions. At first, we define a “test pattern” as one entire set to fulfill a scan chain and a “vector” means one of bitwise elements making a test pattern. When a test vector sequence put into a scan chain, a “Si(v)” is defined as one of test vectors that is applied to a scan chain at time i, also a “Sj(v)” means consecutive vector of a Si(v), exactly one of test vectors that is applied to a scan chain at time j. Therefore, when Si(v) and Sj(v) are different, we call it a transition.
S i (v ) ≠
S j (v), v ∈ {0,1}
(b) s9234
(1)
Finally, if a transition has occurred, then “pattern transition” gains 1. Figure 1 explains a typical transition. (c) s38584
Figure 3. Pattern transition distribution graph Figure 1. Example of a transition
For example, if we have a pattern like Figure 2, the pattern transition of the pattern becomes 8. By using these definitions, we can calculate the pattern transition of each pattern that generated by an LFSR, as a result, the distribution of pattern transition satisfies the pseudo-random Gaussian distribution.
Figure 3 (a), total pattern number that has 30 pattern transitions is 3500 among 5000 patterns. And total pattern number that has 40 pattern transitions is about 1200 among 5000 patterns. So the graph is made by connection of the relation to between pattern transition and pattern number. Other graphs represent the same meaning. From this pattern transition distribution
experiment, we can observe that n scan inputs circuit has maximum (n-1) pattern transition factors. And the graph of generated patterns makes an almost symmetrical curve whose central axis is almost (n-1)/2. Practically, when we generate 5000 test patterns in s1423, s9234, and s38584, the average pattern transition are 36.50, 113.6, and 725.3 which are similar value to (n-1)/2. This fact can be seen in another ISCAS’ 89 benchmark circuit. Hence, we can conclude that the distribution tendency shown in Table 1 is similar to the regular form. It is shown in Table 1. Six ISCAS’ 89 benchmark circuits are compared for two parameters, average pattern transition and (n-1)/2. As we can see from the table, two parameters have similar value. That is, we can use (n-1)/2 as a standard for predicting circuit’s average pattern transition.
Occurred pattern transition propagates to the end of scan chain during the time of test application to fulfill a scan chain. T(s1,s2), T(s2,s3), and T(s3,s4) are factors that increase the pattern transition, by the same calculation method, pattern makes 9 scan shifting in total.
Table 1. Comparison average pattern transition with (n-1)/2 parameter in some benchmark circuits
Figure 4. Calculation method of scan shifting in 5 scan inputs
3. Decision to Set k-value and TMW Size
This distribution characteristic comes from the random pattern property that generated by an LFSR. If we can have a scheme to monitor the transitive tendency of the LFSR, some over-transitive patterns could be repressed by applying the last scan input vector again, not the vector that will be sent to a scan chain next. By this method, we can achieve a reduction in scan shifting transitions as well as pattern transitions. As a consequence, we can solve the peak power problem. Scan shifting transitions of a generated pattern can be obtained by the following method. For instance, if a circuit have 5 scan inputs and pattern is applied to the scan chain, then the number of scan shifting is 9. And as explained before, pattern transitions are 3. Figure 4 shows the process of the scan shifting calculation. T(s1,s2) means the transition factor between first scan vector s1 and its consecutive scan vector s2. The pattern transition gains 1 by (1).
S1 (1) ≠
S 2 (0)
(2)
In Section 2, we discussed the characteristics of pseudo-random Gaussian distribution of patterns that are generated by an LFSR and the necessity of a standard to repress pattern transitions. In order to set a standard that is called k-value, we have to decide how transitive tendency will be observed. It is accompanied with the transition monitoring window (TMW). TMW is a part of an LFSR. As transitions in TMW exceed the k-value, a vector to output is converted to the high correlation vector which is the last input vector in a scan chain. By the property of random patterns that were mentioned in Section 2, if we set LFSR size n, it means TMW is LFSR size, (n-1)/2 would be the average pattern transition. Transition numbers are controlled whether pattern transitions in TMW exceed the average pattern transition or not. In here, (n-1)/2 becomes a k-value. Therefore, if we set a k-value smaller than the average pattern transition, (n-1)/2, we could achieve much more transition reduction. However, a small k-value makes many of the same vectors that indicate high correlation vectors, which may be one reason of performance loss in view of fault coverage. In this paper, we increase or decrease a kvalue to find an optimal transitive repression values. There is a trade-off between how many transitions are reduced and how much performance is lost. At first, let us discuss how TMW size should be selected. In Figure 5, TD means transition density. When TMW is set to its maximum size, the TMW
block should observe whole transitions of the LFSR. Therefore, transitions that exceed the k-value will be repressed by a MUX which will be discussed in next section. If TD2 is bigger than TD1, its effect would be affirmative because the region where transition density is high is repressed. But, in the reverse situation, if TD1 has high density then its effect would be negative because monitored transition of far vectors from the output of the LFSR impacts on near vectors that will go out soon. For this reason, TMW size has to be small.
has the regular form in every circuit that has an LFSR as a random pattern generator.
4. Additional Logic Block for the Proposed Scheme In this section, the logic block for the proposed scheme is described as shown in Figure 6. It is comprised of two XORs, counter, comparator, and a MUX. Two XORs are observing transition of input and output in TMW. Table 2 shows operations of two XORs. XOR_1 detects the transition in front of the TMW, and XOR_2 finds the transition in end of the TMW. From this operation, the counter can observe exact pattern transition number of the TMW. Table 2. Operations of two XOR gates in the transition monitoring window(TMW)
Figure 5. Relation of the transition monitoring window size and transition density
Practically, in order to decide TMW size for patterns having random Gaussian distribution, we can experiment on several sample circuits because, as mentioned in the above section, the distribution tendency has the regular form in every circuit that has an LFSR as a random pattern generator. Experiments were done using 3/4, 1/2, 1/4 of LFSR size. As a result, a half of an LFSR size was examined as an optimal solution for a TMW because other sizes decreased performance and transition reduction. From this point, we should decide how many transitions repress using k-value. In Section 2, we discussed what k-value is and how k-value helps to repress transitions. Equations (3) and (4) represent formal expressions of the k-value and TMW size. k − value =
Monitoring WindowSize − 1 ±α 2
Monitoring WindowSize =
LFSRsize 2
The counter is compared with the comparator per each clock. The comparator includes the k-value. So, if the counter has bigger number than the k-value, the comparator sends MUX enable signal that represses over transitive patterns to make high correlation patters. If the counter has smaller number than the k-value, the output vector of the LFSR would be applied to the scan chain.
(3) (4)
If k-value is small, so many transitions would be repressed. Therefore, increased consecutive and repeated patterns would cause performance loss. In this paper, we applied variable k-values from α = 0. During this process, fault coverage and transition reduction tendency are observed. The reason that this style experiments are available is the distribution tendency
Figure 6. Block diagram of the TMW
Figure 6 explains the additional circuit for the TMW. The counter is initialized to the pattern transition number of the primitive seed of the LFSR. And the
counter number is dependent of the size of TMW. Because the TMW size is the half of the LFSR, we need only log2(MonitoringWindowSize) counter. For example, if we have 32 bits LFSR, the monitoring window size would be 16 bits. Then, the counter should be able to count 15 pattern transitions at most. So, the counter block would be a 4 bits counter, log216. Therefore, even if an LFSR size is big, the hardware overhead for the counter block is not big comparatively
The k-value 10 is obtained by α = +3, the k-value 9 is obtained by α = +2, and k-value 8 is obtained by α = +1. Another k-value is obtained by the same method that adds 1 of the value beginning from 0. Table 4. Results of the experiment using variable size of LFSR and transition monitoring window (a) LFSR size 32 bits, TMW size 16 bits
5. Results In this paper, experiments were conducted using chosen circuits that have many scan inputs among ISCAS’ 89 benchmark circuits. The proposed approach was implemented by C++ language. In this paper, we fixed the applied pattern number to 5000. The experimental results are compared with the representative previous work, LT-RTPG. The comparison table would be shown in the last of this chapter. The LFSR sizes to set TMW size are 32 bits, 24 bits, and 16 bits. And TMW size as mentioned is a half of LFSR size which was determined by additional experiments not shown here. We applied variable kvalues from α = 0. From the results, we found every circuit chosen for the experiment shows identical transition reduction tendency by the distribution of random pattern in Section 2. There are scan input numbers for each circuit that used for experiments in Table 3, in here, PI and SI mean primary input and scan input, respectively.
(b) LFSR size 24 bits, TMW size 12 bits
(c) LFSR size 16 bits, TMW size 8 bits
Table 3. PI and SI number of example circuits
Table 4 shows the results from applying variable sizes of LFSR and TMW, and k-values. In the k-value raw of each table, TR means the ratio of transition reduction compared with the original patterns generated in a LFSR. FC means fault coverage. In Table 4 (a), the results are shown in the case of 32 bits LFSR and 16 bits TMW size, that is, a half size of an LFSR. A k-value is set to 10, 9, 8, and 7 in each cell.
As a result, about 60% average scan shifting transition reduction achieved for every circuit uniformly when α = +1 of the k-value. In that condition, the optimal fault coverage and transition reduction appeared simultaneously. Therefore, α = +1 can be a standard for all circuits that use an LFSR as a random test pattern generator because of the distribution of random patterns. And the reason for the performance loss in the last k-value section of all tables is that converted patterns use so small k-value which is too
high correlative to detect different kinds of faults. So, the condition of α = +1 is the extreme point of the ratio of transition reduction and the performance of fault coverage. Table 5, we compared the previous method, LTRTPG, with the proposed one. Experiments of the previous work have done by circuits that have less gates than s9234, but as shown in Table 4, those circuits that have more gates are experimented in this paper. Therefore, we reported another table to compare two methods. In order to compare performance, transition reduction (TR) and fault coverage (FC) are compared. While the proposed method shows about 60% average transition reduction, the previous method shows about 30% average transition reduction with similar performance. Table 5. Comparison the previous method with the proposed scheme
*Previous Work : LT-RTPG [6]
6. Conclusions This paper proposed a new low power BIST TPG scheme which represses scan shifting transition using random Gaussian distribution of patterns generated by an LFSR. Additional circuits that are comprised of two XORs, a counter, a comparator and a MUX were used to achieve this objective. TMW which is a window to observe transition tendency and k-value which is a standard of repression of over transition were the center of the proposed technique in this paper. Every selected circuit that has many scan inputs among ISCAS’ 89 benchmark circuit showed about 60% scan shifting transition reduction uniformly because these patterns act according to the characteristic of the random Gaussian distribution. The optimal k-value is made by α = +1 and the optimal TMW size is a half of an LFSR size by experiments. These results achieved more transition reduction about average 30% compared with the previous low power technology, LT-RTPG. And it has achieved that
experiment about some other circuits having more gates than s9234 circuits. As shown in experiment results, in those circuits, about 60% transition reduction achieved almost uniformly.
7. References [1] Nan-Cheng Lai and Sying-Jyan Wang, "A Reseeding Technique for LFSR-Based BIST Applications", Proc. IEEE Asian Test Symposium (ATS), 2002, pp. 200-205. [2] Seongmoon Wang, "Generation of Low Power Dissipation and High Fault Coverage Patterns for ScanBased BIST", Proc. IEEE International Test Conference (ITC), 2002, pp. 834-843. [3] Xiaodong Zhang and Kaushik Roy, "Peak Power Reduction in Low Power BIST", Proc. ISQED, 2000, pp. 425-432. [4] S. Wang, and K. Gupta, "DS-LFSR : A New BIST TPG for Low Heat Dissipation", Proc. IEEE International Test Conference (ITC), 1997, pp. 848-857. [5] X. Zhang, K. Roy, and S. Bhawmik, "POWERTEST : A Tool for Energy Conscious Weighted Random Pattern Testing", Proc. The 12th International Conference on VLSI Design, 1999, pp. 416-422. [6] S. Wang, and K. Gupta, "LT-RTPG : A New Test-PerScan BIST TPG for low Heat Dissipation", Proc. IEEE International Test Conference (ITC), 1999, pp. 85-94. [7] N. Ahmed, M. H. Teharanipour, and M. Nourani, "Low Power Pattern Generation for BIST Architecture", proc. IEEE ISCAS, 2004, pp. 689-692. [8] Nadir Z. Basturkmen, Sudhakar M. Reddy, and Irith Pomeranz, "A Low Power Pseudo-Random BIST Technique", proc. IOLTS, 2002, pp. 140-144. [9] S. Wang, "Low Hardware Overhead Scan Based 3Weighted Weighted Random BIST", Proc. IEEE International Test Conference (ITC), 2001, pp. 868-877. [10] S. Manich, A. Gabarro, M. Lopez, and J. Figueras, "Low Power BIST by Filtering Non-Detecting Vectors", Proc. IEEE Test workshop, 1999, pp. 165-170. [11] He Ronghui, Li Xiaowei, and Gong Yunzhan, "A Low Power BIST TPG Design", Proc. IEEE 5th International ASIC Conference, 2003, pp. 1136-1139. [12] Kenneth M. Butler, Jayashree Saxena, Tony Fryars, and Graham Hethrington, "Minimizing Power Consumption in Scan Testing: Pattern Generation and DFT Techniques", Proc. IEEE International Test Conference (ITC), 2004, pp. 355-364. [13] Debjyoti Ghosh, Swarup Bhunia, and Kaushik Roy, "A Technique to Reduce Power and Test Application Time in BIST", Proc. IOLTS, 2004, pp. 182-183. [14] C. Y. Tsui, J. Rajski, and M. Marek0Sadowska, "Star Test: The Theory and Its Applications", IEEE Trans. On Computer-Aided Design of Integrated Circuit and System, Vol. 19(9), September 2000, pp. 1052-1064. [15] Y. Zorian, "A Distributed BIST Control Scheme for Complex VLSI Devices", Proc. VLSI Testing Symposium, 1993, pp. 4-9.
1. Introduction A linear feedback shift register (LFSR) is commonly used as a test pattern generator (TPG) in the low overhead Built-in Self Test (BIST). However, because a circuit under test (CUT) may contain many random pattern resistant faults, achieving high performance with pseudo-random patterns generated by an LFSR often requires unacceptably long test sequences [1]. In BIST technology, it is an important issue to achieve high fault coverage and reduce test time. This paper focuses on a low power BIST scheme, another important concern in this field. Test patterns generated by an LFSR have less correlative than those by normal operation. Therefore, when those patterns are applied to a scan chain, excessive switching activity due to low correlation between consecutive test patterns would dissipate more power [2]. When the peak power exceeds the capability that can tolerate in a circuit, the circuit during test application would be permanently damaged due to excessive heat dissipation. So, a peak power problem due to over-
transitive patterns generated by an LFSR is a necessary consideration in a BIST scheme [3]. Several techniques have been proposed to address this problem. A BIST strategy called dual-speed LFSR [4] was proposed to reduce the circuit’s overall switching activities. Having two different speed LFSRs, the proposed strategy applies some test patterns using a low-speed LFSR by connecting to some inputs that have elevated transition densities. However, this will increase test application time. In order to reduce the test length and average power simultaneously, Zhang and Roy proposed a low power random testing technique [5], in which both signal probabilities and activities at the primary inputs are optimized, and both the average power and the test length are reduced significantly. For ISCAS benchmark circuits, while the average of power reduction by using DS-LFSR is 19%, the average of power reduction by using the low power random testing technique in [5] is as high as 78%. The previous techniques are unable to reduce the peak power, since the instantaneous power is not directly related to the average signal activities. The technique associated with the peak power problem is proposed in [6], lowtransition random TPG (LT-RTPG), that is comprised of an LFSR, a k-input AND gate, and a T flip-flop to reduce shifting transition number in a scan chain. By using this approach, about 23~59% of scan shifting can be reduced. This paper presents a new test pattern generator for low power BIST. The proposed technique increases the correlation between test patterns by using a transition monitoring window (TMW). Since test patterns generated by an LFSR almost satisfy pseudo-random Gaussian distribution, the standard, called k-value that is obtained from the distribution can repress transitions of scan shifting in a scan chain using a TMW. It is a comprised of two XORs, a comparator, counter block, and a MUX. It is used to observe over transitive vector sequences in a range of window size. If the patterns in TMW are more transitive than the k-value, the last
vector in an LFSR which sends to a scan chain soon would be converted into high correlation vector. It is a very important problem how to set k-value and TMW size. The method that used in this paper adapted the property of the pseudo-random Gaussian distribution, if sample circuits optimal k-value and TMW size are set, those of another circuits will be similar. Experimental results prove the theory. ISCAS’ 89 benchmark circuits that have a large number of scan inputs and adapted the same k-value and TMW size show almost identical scan shifting transition reduction tendency. The rest of this paper is organized as follows: Section 2 introduces notations used in the paper. In addition, the characteristics of random patterns’ transition distribution are described. In Section 3, it is discussed how k-value and TMW size are set using pseudo Gaussian random distribution of circuits. In Section 4, the logic diagram adapted for the proposed scheme is described. In Section 5, experimental results are reported for ISCAS’ 89 benchmark circuits. And the conclusions are stated in Section 6.
Figure 2. Example of a pattern transition
Figure 3 shows the pattern transition distribution graph of 5000 test patterns generated in s1423, s9234, and s38584 that have 74, 228, and 1452 scan inputs, respectively.
(a) s1423
2. Distribution Characteristic of Random Pattern Transitions Some definitions are needed to understand this paper correctly before discussing the distribution characteristics of random pattern transitions. At first, we define a “test pattern” as one entire set to fulfill a scan chain and a “vector” means one of bitwise elements making a test pattern. When a test vector sequence put into a scan chain, a “Si(v)” is defined as one of test vectors that is applied to a scan chain at time i, also a “Sj(v)” means consecutive vector of a Si(v), exactly one of test vectors that is applied to a scan chain at time j. Therefore, when Si(v) and Sj(v) are different, we call it a transition.
S i (v ) ≠
S j (v), v ∈ {0,1}
(b) s9234
(1)
Finally, if a transition has occurred, then “pattern transition” gains 1. Figure 1 explains a typical transition. (c) s38584
Figure 3. Pattern transition distribution graph Figure 1. Example of a transition
For example, if we have a pattern like Figure 2, the pattern transition of the pattern becomes 8. By using these definitions, we can calculate the pattern transition of each pattern that generated by an LFSR, as a result, the distribution of pattern transition satisfies the pseudo-random Gaussian distribution.
Figure 3 (a), total pattern number that has 30 pattern transitions is 3500 among 5000 patterns. And total pattern number that has 40 pattern transitions is about 1200 among 5000 patterns. So the graph is made by connection of the relation to between pattern transition and pattern number. Other graphs represent the same meaning. From this pattern transition distribution
experiment, we can observe that n scan inputs circuit has maximum (n-1) pattern transition factors. And the graph of generated patterns makes an almost symmetrical curve whose central axis is almost (n-1)/2. Practically, when we generate 5000 test patterns in s1423, s9234, and s38584, the average pattern transition are 36.50, 113.6, and 725.3 which are similar value to (n-1)/2. This fact can be seen in another ISCAS’ 89 benchmark circuit. Hence, we can conclude that the distribution tendency shown in Table 1 is similar to the regular form. It is shown in Table 1. Six ISCAS’ 89 benchmark circuits are compared for two parameters, average pattern transition and (n-1)/2. As we can see from the table, two parameters have similar value. That is, we can use (n-1)/2 as a standard for predicting circuit’s average pattern transition.
Occurred pattern transition propagates to the end of scan chain during the time of test application to fulfill a scan chain. T(s1,s2), T(s2,s3), and T(s3,s4) are factors that increase the pattern transition, by the same calculation method, pattern makes 9 scan shifting in total.
Table 1. Comparison average pattern transition with (n-1)/2 parameter in some benchmark circuits
Figure 4. Calculation method of scan shifting in 5 scan inputs
3. Decision to Set k-value and TMW Size
This distribution characteristic comes from the random pattern property that generated by an LFSR. If we can have a scheme to monitor the transitive tendency of the LFSR, some over-transitive patterns could be repressed by applying the last scan input vector again, not the vector that will be sent to a scan chain next. By this method, we can achieve a reduction in scan shifting transitions as well as pattern transitions. As a consequence, we can solve the peak power problem. Scan shifting transitions of a generated pattern can be obtained by the following method. For instance, if a circuit have 5 scan inputs and pattern is applied to the scan chain, then the number of scan shifting is 9. And as explained before, pattern transitions are 3. Figure 4 shows the process of the scan shifting calculation. T(s1,s2) means the transition factor between first scan vector s1 and its consecutive scan vector s2. The pattern transition gains 1 by (1).
S1 (1) ≠
S 2 (0)
(2)
In Section 2, we discussed the characteristics of pseudo-random Gaussian distribution of patterns that are generated by an LFSR and the necessity of a standard to repress pattern transitions. In order to set a standard that is called k-value, we have to decide how transitive tendency will be observed. It is accompanied with the transition monitoring window (TMW). TMW is a part of an LFSR. As transitions in TMW exceed the k-value, a vector to output is converted to the high correlation vector which is the last input vector in a scan chain. By the property of random patterns that were mentioned in Section 2, if we set LFSR size n, it means TMW is LFSR size, (n-1)/2 would be the average pattern transition. Transition numbers are controlled whether pattern transitions in TMW exceed the average pattern transition or not. In here, (n-1)/2 becomes a k-value. Therefore, if we set a k-value smaller than the average pattern transition, (n-1)/2, we could achieve much more transition reduction. However, a small k-value makes many of the same vectors that indicate high correlation vectors, which may be one reason of performance loss in view of fault coverage. In this paper, we increase or decrease a kvalue to find an optimal transitive repression values. There is a trade-off between how many transitions are reduced and how much performance is lost. At first, let us discuss how TMW size should be selected. In Figure 5, TD means transition density. When TMW is set to its maximum size, the TMW
block should observe whole transitions of the LFSR. Therefore, transitions that exceed the k-value will be repressed by a MUX which will be discussed in next section. If TD2 is bigger than TD1, its effect would be affirmative because the region where transition density is high is repressed. But, in the reverse situation, if TD1 has high density then its effect would be negative because monitored transition of far vectors from the output of the LFSR impacts on near vectors that will go out soon. For this reason, TMW size has to be small.
has the regular form in every circuit that has an LFSR as a random pattern generator.
4. Additional Logic Block for the Proposed Scheme In this section, the logic block for the proposed scheme is described as shown in Figure 6. It is comprised of two XORs, counter, comparator, and a MUX. Two XORs are observing transition of input and output in TMW. Table 2 shows operations of two XORs. XOR_1 detects the transition in front of the TMW, and XOR_2 finds the transition in end of the TMW. From this operation, the counter can observe exact pattern transition number of the TMW. Table 2. Operations of two XOR gates in the transition monitoring window(TMW)
Figure 5. Relation of the transition monitoring window size and transition density
Practically, in order to decide TMW size for patterns having random Gaussian distribution, we can experiment on several sample circuits because, as mentioned in the above section, the distribution tendency has the regular form in every circuit that has an LFSR as a random pattern generator. Experiments were done using 3/4, 1/2, 1/4 of LFSR size. As a result, a half of an LFSR size was examined as an optimal solution for a TMW because other sizes decreased performance and transition reduction. From this point, we should decide how many transitions repress using k-value. In Section 2, we discussed what k-value is and how k-value helps to repress transitions. Equations (3) and (4) represent formal expressions of the k-value and TMW size. k − value =
Monitoring WindowSize − 1 ±α 2
Monitoring WindowSize =
LFSRsize 2
The counter is compared with the comparator per each clock. The comparator includes the k-value. So, if the counter has bigger number than the k-value, the comparator sends MUX enable signal that represses over transitive patterns to make high correlation patters. If the counter has smaller number than the k-value, the output vector of the LFSR would be applied to the scan chain.
(3) (4)
If k-value is small, so many transitions would be repressed. Therefore, increased consecutive and repeated patterns would cause performance loss. In this paper, we applied variable k-values from α = 0. During this process, fault coverage and transition reduction tendency are observed. The reason that this style experiments are available is the distribution tendency
Figure 6. Block diagram of the TMW
Figure 6 explains the additional circuit for the TMW. The counter is initialized to the pattern transition number of the primitive seed of the LFSR. And the
counter number is dependent of the size of TMW. Because the TMW size is the half of the LFSR, we need only log2(MonitoringWindowSize) counter. For example, if we have 32 bits LFSR, the monitoring window size would be 16 bits. Then, the counter should be able to count 15 pattern transitions at most. So, the counter block would be a 4 bits counter, log216. Therefore, even if an LFSR size is big, the hardware overhead for the counter block is not big comparatively
The k-value 10 is obtained by α = +3, the k-value 9 is obtained by α = +2, and k-value 8 is obtained by α = +1. Another k-value is obtained by the same method that adds 1 of the value beginning from 0. Table 4. Results of the experiment using variable size of LFSR and transition monitoring window (a) LFSR size 32 bits, TMW size 16 bits
5. Results In this paper, experiments were conducted using chosen circuits that have many scan inputs among ISCAS’ 89 benchmark circuits. The proposed approach was implemented by C++ language. In this paper, we fixed the applied pattern number to 5000. The experimental results are compared with the representative previous work, LT-RTPG. The comparison table would be shown in the last of this chapter. The LFSR sizes to set TMW size are 32 bits, 24 bits, and 16 bits. And TMW size as mentioned is a half of LFSR size which was determined by additional experiments not shown here. We applied variable kvalues from α = 0. From the results, we found every circuit chosen for the experiment shows identical transition reduction tendency by the distribution of random pattern in Section 2. There are scan input numbers for each circuit that used for experiments in Table 3, in here, PI and SI mean primary input and scan input, respectively.
(b) LFSR size 24 bits, TMW size 12 bits
(c) LFSR size 16 bits, TMW size 8 bits
Table 3. PI and SI number of example circuits
Table 4 shows the results from applying variable sizes of LFSR and TMW, and k-values. In the k-value raw of each table, TR means the ratio of transition reduction compared with the original patterns generated in a LFSR. FC means fault coverage. In Table 4 (a), the results are shown in the case of 32 bits LFSR and 16 bits TMW size, that is, a half size of an LFSR. A k-value is set to 10, 9, 8, and 7 in each cell.
As a result, about 60% average scan shifting transition reduction achieved for every circuit uniformly when α = +1 of the k-value. In that condition, the optimal fault coverage and transition reduction appeared simultaneously. Therefore, α = +1 can be a standard for all circuits that use an LFSR as a random test pattern generator because of the distribution of random patterns. And the reason for the performance loss in the last k-value section of all tables is that converted patterns use so small k-value which is too
high correlative to detect different kinds of faults. So, the condition of α = +1 is the extreme point of the ratio of transition reduction and the performance of fault coverage. Table 5, we compared the previous method, LTRTPG, with the proposed one. Experiments of the previous work have done by circuits that have less gates than s9234, but as shown in Table 4, those circuits that have more gates are experimented in this paper. Therefore, we reported another table to compare two methods. In order to compare performance, transition reduction (TR) and fault coverage (FC) are compared. While the proposed method shows about 60% average transition reduction, the previous method shows about 30% average transition reduction with similar performance. Table 5. Comparison the previous method with the proposed scheme
*Previous Work : LT-RTPG [6]
6. Conclusions This paper proposed a new low power BIST TPG scheme which represses scan shifting transition using random Gaussian distribution of patterns generated by an LFSR. Additional circuits that are comprised of two XORs, a counter, a comparator and a MUX were used to achieve this objective. TMW which is a window to observe transition tendency and k-value which is a standard of repression of over transition were the center of the proposed technique in this paper. Every selected circuit that has many scan inputs among ISCAS’ 89 benchmark circuit showed about 60% scan shifting transition reduction uniformly because these patterns act according to the characteristic of the random Gaussian distribution. The optimal k-value is made by α = +1 and the optimal TMW size is a half of an LFSR size by experiments. These results achieved more transition reduction about average 30% compared with the previous low power technology, LT-RTPG. And it has achieved that
experiment about some other circuits having more gates than s9234 circuits. As shown in experiment results, in those circuits, about 60% transition reduction achieved almost uniformly.
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