A Novel Digital Lock Detector For QPSK Receiver - IEEE Xplore
750
IEEE TRANSACTIONS ON COMMUNICATIONS, VOL. 46, NO. 6, JUNE 1998
A Novel Digital Lock Detector for QPSK Receiver Kyung Ha Lee, Seung Chul Jung, and Hyung Jin Choi, Member, IEEE
Abstract—A new lock detection algorithm for digital quadrature phase-shift keying (QPSK) receiver is proposed. Analysis of the detector’s output characteristics is given and is verified by using computer simulation. Performance degradation due to carrier jitter is also considered. Analytic and simulation results show that the proposed algorithm is very useful as a lock detector in digital receivers because it has a good detection performance and simple structure. Index Terms—Lock detector, synchronization.
I. INTRODUCTION
T
HE LOCK detector plays an important role in monitoring and controlling communication receivers. A general carrier lock detection algorithm for quadrature phase-shift keying (QPSK) is given by [1]
out the fourth-power calculation. Moreover, when the signalto-noise ratio (SNR) is low, the performance degradation due to the cross product of noise becomes significant. Therefore, a lock detection algorithm which requires fewer multiplications is necessary for effective implementation of the digital lock detector. In this letter a new lock detection algorithm for a digital QPSK receiver is proposed. The proposed lock detector needs no multipliers and shows improved detection performance. In Section II we describe the new detection algorithm and analyze the output characteristics. In Section III we discuss performance evaluation of the proposed lock detector. II. THE PROPOSED LOCK DETECTOR The proposed algorithm can be expressed as follows:
(1) In (1), the th sampling outputs of the inphase and quadrature are given by (assuming perfect gain control channel and and symbol synchronization)
(2) where the input phase is denoted by , is the th symbol information, i.e., or , is the th phase error, and is the baseband noise. During the carrier lock detection, each , the output of the lock detector, is compared to a predefined threshold , and the lock detector decides that the loop is in the lock state when exceeds . The main problem of this algorithm is that it requires heavy computational load for digital implementation. It needs three multipliers and a large number of bits to carry Paper approved by E. Panayirci, the Editor for Synchronization and Equalization of the IEEE Communications Society. Manuscript received September 1, 1996; revised February 3, 1997 and February 1, 1998. This paper was presented in part at the International Symposium on PIMRC, Taiwan, October 15–18, 1996. K. H. Lee was with the Department of Electronics Engineering, Sung Kyun Kwan University, Suwon-City, KyungKi-Do 440-746, Korea. He is now with the Wireless Development Team Core Technical Group, Samsung Electronics Company, Ltd., Kihung, Korea. S. C. Jung was with the Department of Electronics Engineering, Sung Kyun Kwan University, Suwon-City, KyungKi-Do 440-746, Korea. He is now with the Multimedia Laboratory, LG Electronics Company, Ltd., Seoul, Korea. H. J. Choi is with the Department of Electronics Engineering, Sung Kyun Kwan University, Suwon-City, KyungKi-Do 440-746, Korea (e-mail: [email protected]). Publisher Item Identifier S 0090-6778(98)04590-5.
(3) The proposed algorithm is easy to implement digitally because it needs no multiplier. The structure of the digital QPSK demodulator with the new lock detector is shown in Fig. 1. The proposed lock detector can be also implemented using a comparator by using the second term of (3). and are mutually independent Bearing in mind that Gaussian random variables for a given phase ( ) (with means and , respectively, and variance equal to that of the input noise ), then the conditional probability density functions (pdf’s) ) of (which are the absolute value of , ) can be obtained from the transformation of random variables as follows:
for
for (4) If we assume that takes the value . Also, if function of corresponds to the event
0090–6778/98$10.00 1998 IEEE
, then is only a , then the event
IEEE TRANSACTIONS ON COMMUNICATIONS, VOL. 46, NO. 6, JUNE 1998
751
Fig. 1. The proposed lock detector.
. So, by using nonmonotonic transformation of the random variable, the conditional pdf is found to be
for Vice versa, if the event
where and means the tail function, not channel signal. It can be shown that to be confused with takes the same values regardless of whether the is or . In other words, information symbol is independent of symbol information and is expressed only as a function of phase error . By using the pdf of , the mean and the variance of when the receiver is in the lock is obtained as
(5) , the event
corresponds to , and we have
(8) for
(6)
Because the conditional pdf of is zero when and is a positive value from (5) and (6), we have (7), shown at the bottom of the page,
and the joint pdf In (8) the pdf of phase error process of phase error are obtained from [1]. When the ), we can assume that the loop SNR is very high (i.e.,
(7)
752
IEEE TRANSACTIONS ON COMMUNICATIONS, VOL. 46, NO. 6, JUNE 1998
phase error
is zero so that
and
become
(9) where
Generally, a loss of lock results from an unsuccessful tracking of the frequency offset. When the loop gain of the carrier recovery loop is so small that the estimated phase is nearly constant within one observation period, the phase error can be assumed to be changed by the frequency offset only. In addition, if the frequency offset is so small that the effect , which are the of the channel filter can be ignored, mean and the variance of when the receiver is in the unlock state, can be approximated as
Fig. 2. Probability of the lock detection failure 1 Pf .
0 Pd versus the required
and variance [1]. Correspondingly, the probability of detection is expressed as
(11) In the unlock state, the probability of false lock is given by
(12) The threshold value
is derived from (11) and (12) as
(13) From (13), since the mean is expressed as
in the unlock state is zero,
(14)
(10) ( - ). In (10) where we note that the variance of is almost constant regardless of when the observation length is large enough to satisfy . III. DESIGN
AND
PERFORMANCE EVALUATION
In designing the decision threshold we apply the central limit theorem and, in particular, we assume the pdf of the lock detector’s output to be approximately Gaussian with mean
In (14), SNR , the detector SNR, which is defined as [1], is a very important parameter for the lock detector performance. of Fig. 2 depicts the detection failure probability the lock detector, which is designed to have the required false detection probability when the carrier recovery loop SNR is infinite (i.e., the effect of carrier jitter can be ignored). For computer simulation, we choose the observation length to be 128 and to be 2.5 dB. Fig. 3 depicts the detection failure probability of the lock detector as a function of the observation length and the required false when the carrier recovery loop SNR is detection probability infinite. In Figs. 2 and 3 the proposed algorithm shows a better probability of lock detection than the conventional one with
IEEE TRANSACTIONS ON COMMUNICATIONS, VOL. 46, NO. 6, JUNE 1998
Fig. 3. length
Probability of the lock detection failure 1
M.
0 Pd versus observation
the same probability of false lock and observation length. This results from the fact that the proposed detector has no secondand fourth-power nonlinearities. Next, we consider the performance degradation due to the phase jitter of the carrier recovery loop. Fig. 4 depicts the of the lock detector as detection failure probability a function of the loop SNR which is defined as the inverse is 10 . The carrier of the phase jitter variance, when recovery loop used in the simulation is a general decisiondirect (DD) loop [3] shown in Fig. 1. This figure shows that the proposed detector has some performance degradation when the loop SNR is low, but the detection failure probability of the proposed algorithm is still lower than that of the conventional algorithm in the range of the loop SNR that guarantees normal operation of the carrier recovery loop (i.e., higher than 12 dB).
753
Fig. 4.
Probability of lock detection failure 1
0 Pd versus loop SNR.
Consequently, we believe that the proposed algorithm is very useful as a lock detector in a digital receiver because it has better detection performance and simpler structure than the conventional one. REFERENCES [1] A. Mileant and S. Hinedi, “On the effect of phase jitter on QPSK lock detection,” IEEE Trans. Commun., vol. 41, pp. 1043–1046, July 1993. , “Lock detection in Costas loop,” IEEE Trans. Commun., vol. [2] 40, pp. 480–483, Mar. 1992. [3] H. C. Osborne, “A generalized polarity-type Costas loop for tracking MPSK signals,” IEEE Trans. Commun., vol. COM-30, pp. 2289–2296, Oct. 1982. [4] H. J. Choi, Coherent Digital Communications. Seoul, Korea: KyoHakSa, 1995.
IEEE TRANSACTIONS ON COMMUNICATIONS, VOL. 46, NO. 6, JUNE 1998
A Novel Digital Lock Detector for QPSK Receiver Kyung Ha Lee, Seung Chul Jung, and Hyung Jin Choi, Member, IEEE
Abstract—A new lock detection algorithm for digital quadrature phase-shift keying (QPSK) receiver is proposed. Analysis of the detector’s output characteristics is given and is verified by using computer simulation. Performance degradation due to carrier jitter is also considered. Analytic and simulation results show that the proposed algorithm is very useful as a lock detector in digital receivers because it has a good detection performance and simple structure. Index Terms—Lock detector, synchronization.
I. INTRODUCTION
T
HE LOCK detector plays an important role in monitoring and controlling communication receivers. A general carrier lock detection algorithm for quadrature phase-shift keying (QPSK) is given by [1]
out the fourth-power calculation. Moreover, when the signalto-noise ratio (SNR) is low, the performance degradation due to the cross product of noise becomes significant. Therefore, a lock detection algorithm which requires fewer multiplications is necessary for effective implementation of the digital lock detector. In this letter a new lock detection algorithm for a digital QPSK receiver is proposed. The proposed lock detector needs no multipliers and shows improved detection performance. In Section II we describe the new detection algorithm and analyze the output characteristics. In Section III we discuss performance evaluation of the proposed lock detector. II. THE PROPOSED LOCK DETECTOR The proposed algorithm can be expressed as follows:
(1) In (1), the th sampling outputs of the inphase and quadrature are given by (assuming perfect gain control channel and and symbol synchronization)
(2) where the input phase is denoted by , is the th symbol information, i.e., or , is the th phase error, and is the baseband noise. During the carrier lock detection, each , the output of the lock detector, is compared to a predefined threshold , and the lock detector decides that the loop is in the lock state when exceeds . The main problem of this algorithm is that it requires heavy computational load for digital implementation. It needs three multipliers and a large number of bits to carry Paper approved by E. Panayirci, the Editor for Synchronization and Equalization of the IEEE Communications Society. Manuscript received September 1, 1996; revised February 3, 1997 and February 1, 1998. This paper was presented in part at the International Symposium on PIMRC, Taiwan, October 15–18, 1996. K. H. Lee was with the Department of Electronics Engineering, Sung Kyun Kwan University, Suwon-City, KyungKi-Do 440-746, Korea. He is now with the Wireless Development Team Core Technical Group, Samsung Electronics Company, Ltd., Kihung, Korea. S. C. Jung was with the Department of Electronics Engineering, Sung Kyun Kwan University, Suwon-City, KyungKi-Do 440-746, Korea. He is now with the Multimedia Laboratory, LG Electronics Company, Ltd., Seoul, Korea. H. J. Choi is with the Department of Electronics Engineering, Sung Kyun Kwan University, Suwon-City, KyungKi-Do 440-746, Korea (e-mail: [email protected]). Publisher Item Identifier S 0090-6778(98)04590-5.
(3) The proposed algorithm is easy to implement digitally because it needs no multiplier. The structure of the digital QPSK demodulator with the new lock detector is shown in Fig. 1. The proposed lock detector can be also implemented using a comparator by using the second term of (3). and are mutually independent Bearing in mind that Gaussian random variables for a given phase ( ) (with means and , respectively, and variance equal to that of the input noise ), then the conditional probability density functions (pdf’s) ) of (which are the absolute value of , ) can be obtained from the transformation of random variables as follows:
for
for (4) If we assume that takes the value . Also, if function of corresponds to the event
0090–6778/98$10.00 1998 IEEE
, then is only a , then the event
IEEE TRANSACTIONS ON COMMUNICATIONS, VOL. 46, NO. 6, JUNE 1998
751
Fig. 1. The proposed lock detector.
. So, by using nonmonotonic transformation of the random variable, the conditional pdf is found to be
for Vice versa, if the event
where and means the tail function, not channel signal. It can be shown that to be confused with takes the same values regardless of whether the is or . In other words, information symbol is independent of symbol information and is expressed only as a function of phase error . By using the pdf of , the mean and the variance of when the receiver is in the lock is obtained as
(5) , the event
corresponds to , and we have
(8) for
(6)
Because the conditional pdf of is zero when and is a positive value from (5) and (6), we have (7), shown at the bottom of the page,
and the joint pdf In (8) the pdf of phase error process of phase error are obtained from [1]. When the ), we can assume that the loop SNR is very high (i.e.,
(7)
752
IEEE TRANSACTIONS ON COMMUNICATIONS, VOL. 46, NO. 6, JUNE 1998
phase error
is zero so that
and
become
(9) where
Generally, a loss of lock results from an unsuccessful tracking of the frequency offset. When the loop gain of the carrier recovery loop is so small that the estimated phase is nearly constant within one observation period, the phase error can be assumed to be changed by the frequency offset only. In addition, if the frequency offset is so small that the effect , which are the of the channel filter can be ignored, mean and the variance of when the receiver is in the unlock state, can be approximated as
Fig. 2. Probability of the lock detection failure 1 Pf .
0 Pd versus the required
and variance [1]. Correspondingly, the probability of detection is expressed as
(11) In the unlock state, the probability of false lock is given by
(12) The threshold value
is derived from (11) and (12) as
(13) From (13), since the mean is expressed as
in the unlock state is zero,
(14)
(10) ( - ). In (10) where we note that the variance of is almost constant regardless of when the observation length is large enough to satisfy . III. DESIGN
AND
PERFORMANCE EVALUATION
In designing the decision threshold we apply the central limit theorem and, in particular, we assume the pdf of the lock detector’s output to be approximately Gaussian with mean
In (14), SNR , the detector SNR, which is defined as [1], is a very important parameter for the lock detector performance. of Fig. 2 depicts the detection failure probability the lock detector, which is designed to have the required false detection probability when the carrier recovery loop SNR is infinite (i.e., the effect of carrier jitter can be ignored). For computer simulation, we choose the observation length to be 128 and to be 2.5 dB. Fig. 3 depicts the detection failure probability of the lock detector as a function of the observation length and the required false when the carrier recovery loop SNR is detection probability infinite. In Figs. 2 and 3 the proposed algorithm shows a better probability of lock detection than the conventional one with
IEEE TRANSACTIONS ON COMMUNICATIONS, VOL. 46, NO. 6, JUNE 1998
Fig. 3. length
Probability of the lock detection failure 1
M.
0 Pd versus observation
the same probability of false lock and observation length. This results from the fact that the proposed detector has no secondand fourth-power nonlinearities. Next, we consider the performance degradation due to the phase jitter of the carrier recovery loop. Fig. 4 depicts the of the lock detector as detection failure probability a function of the loop SNR which is defined as the inverse is 10 . The carrier of the phase jitter variance, when recovery loop used in the simulation is a general decisiondirect (DD) loop [3] shown in Fig. 1. This figure shows that the proposed detector has some performance degradation when the loop SNR is low, but the detection failure probability of the proposed algorithm is still lower than that of the conventional algorithm in the range of the loop SNR that guarantees normal operation of the carrier recovery loop (i.e., higher than 12 dB).
753
Fig. 4.
Probability of lock detection failure 1
0 Pd versus loop SNR.
Consequently, we believe that the proposed algorithm is very useful as a lock detector in a digital receiver because it has better detection performance and simpler structure than the conventional one. REFERENCES [1] A. Mileant and S. Hinedi, “On the effect of phase jitter on QPSK lock detection,” IEEE Trans. Commun., vol. 41, pp. 1043–1046, July 1993. , “Lock detection in Costas loop,” IEEE Trans. Commun., vol. [2] 40, pp. 480–483, Mar. 1992. [3] H. C. Osborne, “A generalized polarity-type Costas loop for tracking MPSK signals,” IEEE Trans. Commun., vol. COM-30, pp. 2289–2296, Oct. 1982. [4] H. J. Choi, Coherent Digital Communications. Seoul, Korea: KyoHakSa, 1995.
