A Phase-Domain All-Digital Phase-Locked Loop ... - IEEE Xplore
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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 56, NO. 11, NOVEMBER 2009
A Phase-Domain All-Digital Phase-Locked Loop Architecture Without Reference Clock Retiming Stefan Mendel, Student Member, IEEE, Christian Vogel, Member, IEEE, and Nicola Da Dalt, Member, IEEE
Abstract—State-of-the-art phase-domain all-digital phaselocked loops (ADPLLs) require a retimed reference clock to synchronize the digitally controlled oscillator (DCO) output frequency and the reference clock frequency. Therefore, the entire digital logic is operated with a periodically nonuniform clock. Due to on-chip coupling effects, the DCO output frequency is pulled with the edges of the retimed reference clock, producing undesired spurs in the phase noise power spectrum. In this brief, we analyze and classify the spur generation from a signal processing point of view and propose an alternative ADPLL implementation that abandons the retiming mechanism. Thus, the entire ADPLL can be clocked with a uniform reference clock, and consequently, side spurs are avoided. Behavioral simulations verify the spur analysis and emphasize the improved behavior of the proposed synchronous reference architecture. Index Terms—All-digital phase-locked loops (ADPLLs), injection pulling, metastability, nonuniform sampling, reference spurs, side spurs.
I. I NTRODUCTION
P
ARASITIC coupling between the digital circuitry and the inductance–capacitance oscillator, which share the same substrate, power, and ground planes [1], causes a periodic disturbance of the oscillator. The rising and falling edges of the nonuniform retimed reference clock trigger the massive digital logic, which “pulls” the digitally controlled oscillator (DCO) output frequency. This effect produces undesired spurs in the output phase noise spectrum. In [1], the spurs are separated into reference spurs and side spurs. Reference spurs are caused by injection pulling, whereas side spurs are caused by injection pulling and the periodically time-varying retimed reference clock. The retimed reference clock is used to synchronize the fast DCO clock domain with the clock domain of the slow reference clock within the ADPLL [1]–[4]. Furthermore, it was reported in [1] that some measured side spurs have been close to the margins of the GSM specification. Reducing the coupling on the die through careful circuit design mitigates these spurs; however, in this brief, we present an alternative
Manuscript received February 11, 2009; revised June 28, 2009. Current version published November 18, 2009. The work of S. Mendel was supported by Infineon Technologies Austria AG. The work of C. Vogel was supported by the Austrian Science Fund (FWF) Erwin Schroedinger Fellowship J2709-N20. This paper was recommended by Associate Editor S. Pamarti. S. Mendel is with the Christian Doppler Laboratory for Nonlinear Signal Processing, Graz University of Technology, 8010 Graz, Austria (e-mail: [email protected]). C. Vogel was with the Signal and Information Processing Laboratory, Swiss Federal Institute of Technology (ETH) Zürich, 8092 Zürich, Switzerland. He is now with the Signal Processing and Speech Communication Laboratory, Graz University of Technology, 8010 Graz, Austria (e-mail: [email protected]). N. Da Dalt is with the Infineon Technologies Development Center, 9500 Villach, Austria (e-mail: [email protected]). Digital Object Identifier 10.1109/TCSII.2009.2034079
Fig. 1. Injection pulling model: The nonuniform impulse train, corresponding to the rising and falling edges of the retimed reference clock s(t), is decomposed into P sampling functions sp (t). The 2-periodic impulse response hp,2 (t) models the shape of the frequency injection pulse for rising and falling edges, i.e., hp,2 = h0 (t) when p is even and hp,2 = h1 (t) when p is odd.
architecture that solves the problem of side spurs on the system level. Therefore, we first analyze the generation of spurs due to injection pulling and then propose a phase-domain ADPLL operated by a uniform reference clock without retiming that does not generate side spurs. II. R EFERENCE S PURS , S IDE S PURS , AND I NJECTION M ISMATCH S PURS This section analyzes the generation of injection pulling spurs, their frequencies and amplitudes, and their dependence on the frequency command word Nr . Basically, we can distinguish between three kinds of spurs: reference spurs, side spurs, and injection mismatch spurs. Reference spurs are caused by a periodic injection pulling signal, which is due to parasitic coupling effects on the die. The periodic nonuniform retimed reference clock CKR of the ADPLL in [2]–[4] generates side spurs by shifting the energy of the reference spurs to additional frequencies. Different gains of the injected frequency among rising and falling CKR edges lead to injection mismatch spurs. A. General Injection Pulling Model Injection pulling changes the DCO output frequency fv (t) over a period shorter than a reference cycle. As the frequencyto-phase conversion in the feedback path of an ADPLL is basically an integration over one reference cycle, the error due to injection pulling appears as a constant factor in the phase error. The loop compensates this factor, and consequently, the analysis of injection pulling can neglect the feedback mechanism, which leads to the open-loop model shown in Fig. 1. The output signal fv (t) can be decomposed into an ideal
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MENDEL et al.: PHASE-DOMAIN ADPLL ARCHITECTURE WITHOUT REFERENCE CLOCK RETIMING
Fig. 2.
ADPLL architecture with a retimed reference mechanism [2]–[4].
signal f˜v (t), which is constantly in lock, and an undesired injection pulling signal fip (t). The nonuniform impulse train s(t) represents the rising and falling edge events of the periodically nonuniform retimed reference clock and is decomposed into P sampling functions sp (t) at a P -time lower rate. With each Dirac impulse of sp (t), the injection pulling generation filter produces an injection pulse. The 2-periodic impulse response hp,2 (t), where p, 2 stands for p modulo 2, accounts for the different pulse shapes of the rising and falling CKR edges. To evaluate the effects of the injection pulling signal fip (t) on the output frequency fv (t), we apply the injection pulling model to the retimed reference architecture. First, we describe the P uniform impulse trains sp (t), whose sum represent the periodically nonuniform retimed reference clock, and then convolve sp (t) with the injection pulling generation impulse responses hp,2 (t). B. Retimed Reference Clock The architecture shown in Fig. 2 uses a retimed reference clock CKR to synchronize the reference phase ϕr [m] and the variable phase ϕv [i], where the signal ε[m] compensates for the retiming error [2]–[4]. As shown in Fig. 3, the edges of the slow reference clock REF (frequency fr = 1/Tr and time index n) are delayed to the subsequent rising edge of the fast DCO output clock CKV (frequency fv = 1/Tv and time index i) to produce the nonuniform retimed reference clock CKR (average frequency fr and time index m). The retiming mechanism can be implemented with flip-flops, as shown in Fig. 2. In the steady state, the retimed reference clock CKR has an average period of Tr = Nr × Tvss , where Tvss = 1/fvss denotes the DCO output period in the steady state. The clock follows a certain periodic pattern with a period given by the denominator M of Nrfrac = L/M , where Nr = Nrint + Nrfrac , and L and M are relative prime integers. For example, if Nr = 100 + 1/5, i.e., Nrint = 100, Nrfrac = 1/5, and M = 5, then four reference cycles are 100 × Tvss long, and every fifth reference cycle is 101 × Tvss long. This pattern will periodically repeat with period M = 5 [5]. The signal s(t) in Fig. 3 describes the rising and falling edge events of the clock signal CKR (solid) as a train of Dirac impulses δ(t). As illustrated in Fig. 3, the time shifts between the nonuniform impulse train (solid) and the uniform impulse train with constant period Tr /2 (dashed) are given by ε[m]Tvss for the rising CKR edges and ε[m]Tvss for the falling CKR edges. For the sake of brevity, we introduce relative time
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Fig. 3. Reference clock REF, variable clock CKV, retimed reference clock CKR, and the impulse train s(t) corresponding to the rising and falling edges of the uniform clock REF (dashed) and the nonuniform clock CKR (solid) in the steady state for Nr = 2 + 1/4.
offsets r[p], which are the deviations normalized to the half Tr /2 of the uniform period, i.e., 2 ε[p/2], if p is even r[p] = N2r (1) ε [(p − 1)/2] , if p is odd Nr where we used Tr = Tvss × Nr . Since ε[m] and ε[m] are periodic with M , the nonuniform sampling train s(t) with the relative time offsets r[p] is periodic with P = 2M , i.e., P −1 ∞ Tr s(t) = δ t − (lP + p + r[p]) . (2) 2 p=0 l=−∞ sp (t)
C. Injection Pulling Signal The injection pulling signal fip (t) is given by the sum of the convolutions of the impulse responses hp,2 (t) with the nonuniform impulse trains sp (t) in (2), i.e., ∞ P −1 Tr fip (t) = hp,2 t − (lP + p + r[p]) . (3) 2 p=0 l=−∞
After applying the continuous-time Fourier transform (CTFT) to (3) and some simplifications, we obtain ∞ 2 2 × 2πfr Fip (jΩ) = 2πδ Ω − k Ak (jΩ) (4) Tr P k=−∞
with Ak (jΩ) =
P −1 Tr 2π 1 Hp,2 (jΩ)e−jΩr[p] 2 e−jkp P P p=0
(5)
and Hp,2 (jΩ) is the CTFT of hp,2 (t). The spectrum Fip (jΩ) in (4) allows for describing the frequency locations and the amplitudes of the spurs caused by injection pulling. Based on this description, we can classify the spurs into reference spurs, side spurs, and injection mismatch spurs. An example of such an output spectrum [converted into the phase domain by integration, i.e., Fip (jΩ)/(jΩ)] is shown in Fig. 4. Basically, the spectrum consists of P = 2M spurs uniformly spaced between 0 and 2fr , which are periodically repeated with 2fr . The amplitudes of the spurs are given by the frequency
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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 56, NO. 11, NOVEMBER 2009
Fig. 4. Phase noise of the reference retimed ADPLL with injection pulling and a frequency command word of Nr = 63 + 2/5, i.e., a period of M = 5.
response Ak (jΩ), which depends on the time offsets r[p] and the impulse responses hp,2 (t). Reference spurs are introduced by injection pulling, located at multiples of (2fr ), and weighted by A0 (jΩ). Side spurs are caused by the time shifts r[p] of the injection pulling signal due to the nonuniform clock CKR. They appear at k(2fr /P ) + l(2fr ) weighted by Ak (jΩ) with k = 1, . . . , P − 1 and l = 1, . . . , ∞. Injection mismatch spurs are determined by the periodicity (with period two) of the impulse responses hp,2 (t). They are located at fr + l(2fr ) weighted by AP/2 (jΩ) with l = 1, . . . , ∞. Note that injection mismatch spurs and side spurs contribute energy to AP/2 (jΩ). When we assume that injection pulling appears with a uniform clock signal, the time offsets r[p] are zero, and we can simplify (4) to ∞ 2
2πδ(Ω − kπ4fr )A0 (jΩ) Fip (jΩ) = Tr k=−∞ + 2πδ(Ω − 2πfr − k4πfr )AP/2 (jΩ) (6)
Fig. 5.
ADPLL architecture with synchronous reference timing.
Fig. 6. Relation between the reference clock REF, the variable clock CKV, and the injection pulling signal fip (t).
the phase-domain ADPLL remains, we present an alternative way to extract the phase information from the oscillating DCO output signal. Basically, we measure the number of CKV cycles within one REF cycle, which is denoted as Nv [n]. Accumulating Nv [n] at the rate of the uniform reference frequency gives the variable phase, i.e., ϕv [n] = ϕv [n − 1] + Nv [n]
and (5) to 1 (H0 (jΩ) + H1 (jΩ)) 2 1 AP/2 (jΩ) = (H0 (jΩ) − H1 (jΩ)) . 2
(8)
which can directly be compared with the reference phase
A0 (jΩ) =
(7)
Thus, all side spurs vanish. Only the reference spurs with the weight A0 (jΩ) and the injection mismatch spurs with the weight AP/2 (jΩ) remain in the spectrum. In case the injection pulling signal is identical for rising and falling edges, the 2-periodic impulse response hp,2 (t) simplifies to a nonperiodic impulse response h(t), and the weight AP/2 (jΩ) becomes zero. We can conclude that an ADPLL with a uniform clock does not generate side spurs. III. S YNCHRONOUS R EFERENCE A RCHITECTURE In this section, we propose an alternative phase-domain ADPLL, which is shown in Fig. 5, that avoids the retiming of the reference clock and, thus, the generation of side spurs. In contrast to [2]–[4], the entire digital logic is clocked by the uniform reference clock REF.1 While the principal structure of 1 The synchronization between the CKV and the REF clock domains is done with a dedicated circuit, which is presented in Section IV.
ϕr [n] = ϕr [n − 1] + Nr .
(9)
In the steady state, the value of Nv [n] equals Nr and may be a fractional number consisting of an integer part Nvint and a fractional part Nvfrac . To measure the variable phase ϕv [n], we split the computation into an integer part ϕint v [n] and a fractional part ϕfrac v [n], i.e., frac ϕv [n] = ϕint v [n] + ϕv [n] int = ϕint v [n − 1] + Nv [n] frac + ϕv [n − 1] + Nvfrac [n].
(10)
In practice, the integer part ϕint v [n] is determined by accumulating 1 at rate CKV and sampling its value with the reference clock REF instead of CKR in Fig. 2. As illustrated in Fig. 6, counting the number of rising edge events corresponds to the integer number of CKV periods Nvint [n] plus one, resulting in int
int ϕint (11) v [n] = ϕv [n − 1] + Nv [n] + 1 . Accordingly, the fractional part of the variable phase accumulates Nvfrac [n] minus one, so that the sum of the variable
MENDEL et al.: PHASE-DOMAIN ADPLL ARCHITECTURE WITHOUT REFERENCE CLOCK RETIMING
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Fig. 8. Metastability avoidance circuit. Fig. 7.
Synchronous reference timing mechanism in lock for Nr = 1 + 1/2.
frac integer phase ϕint v [n] and the variable fractional phase ϕv [n] yields (8). Determining the fractional part ϕfrac v [n] is more difficult, because the REF clock and the CKV clock are not synchronized. Fig. 6 shows the variable clock CKV for one reference cycle REF. The fractional part Nvfrac [n] consists of the fractional part ε[n] at the beginning of one REF cycle and the fractional part ξ[n] at the ending of one REF cycle, i.e.:
Nvfrac [n] = ε[n] + ξ[n]
(12)
where ξ[n] is the time between the rising edge of CKV and the following rising edge of REF normalized by Tv , while ε[n] is the time between the rising edge of REF and the following rising edge of the CKV clock normalized by Tv . One way to compute the fractional part Nvfrac [n] is to measure ε[n] and ξ[n] with a time-to-digital converter (TDC). Alternatively, by assuming that Tv [n] ≈ Tv [n − 1], we can relate ε[n] and ξ[n − 1] (cf. Fig. 6) as ε[n] ≈ 1 − ξ[n − 1].
(13)
During the locking process, the approximation in (13) introduces an insignificant error, which is getting smaller as Tv [n] approaches Tvss . Finally, in the steady state, (13) will be exact. Accumulating (Nvfrac [n] − 1) with (12) and (13) and solving the recursive relation yields the fractional part of the variable phase ϕfrac v [n], i.e.: frac ϕfrac v [n] = ϕv [n−1]+(ξ[n]−ξ[n−1]) = ξ[n]−ξ[0].
(14)
The initial value of ξ[0] in (14) can be neglected, because a constant phase error will be compensated by the control loop. Finally, by using the reference phase ϕr [n] from (9) and the variable phase ϕv [n] from (8), the phase error ϕe [n] is given by ϕe [n] = ϕr [n] − ϕv [n].
(15)
Fig. 7 illustrates the synchronous reference timing mechanism in lock for Nr = 1 + 1/2. Note that the transfer function of the synchronous reference architecture matches the transfer function of the reference retimed architecture (with the exception of slightly different sampling instances [6]). Consequently, both architectures have equivalent noise suppression capabilities, but the synchronous reference architecture, which uses a uniform clock, is better concerning injection pulling, as discussed in Section II.
IV. M ETASTABILITY AVOIDANCE In (11), the variable phase ϕv [i] of the rate of the fast CKV clock is sampled by the slow clock REF. Since these clocks are not synchronized, metastability problems may occur when both rising edges coincide. Metastable states must be avoided, because the ADPLL immediately loses lock. Fortunately, the TDC measures the relation between both edges with a higher resolution (typically, an inverter delay of 20 ps) than Tv , and the gained information about ξ[n] can be used to avoid metastability [7]. Therefore, the value of the accumulator ϕv [i] is additionally sampled with the negative edge of CKV to produce ϕv [i]. In case the positive edges of CKV and CKR happen to be close to each other, the well-defined value of ϕv [i] can be used for further processing instead of the possibly corrupted value of ϕv [i]. Since the value of ϕv [i] will be updated when ξ[n] = 1/2, we distinguish between two cases: if ξ[n] is close to 1, i.e., ξ[n] > 1 − ξT , where ξT is a certain threshold, e.g., ξT = 1/4, we will use ϕv [i], and if ξ[n] is close to 0, i.e., ξ[n] < ξT , we will use ϕv [i] + 1, because the value of ϕv [i] was not yet updated. Fig. 8 shows the metastability avoidance circuit (MAC). Additionally, the circuit may be gated to minimize the power consumption and switched on if needed. Metastable states, i.e., ξ[n], may be predicted from its previous value ξ[n] = (ξ[n − 1] + Nrfrac ) mod 1, where mod denotes the modulo operation [5]. V. S IMULATIONS The simulations were carried out in a high-level time-domain simulation environment according to [8]. Since the proposed synchronous reference architecture is slightly different from the retimed reference architecture, the model has slightly been modified. A. Modeling Synchronous Reference Timing The change of the tuning word d[n] may occur at any time during a variable period Tv [i] (shown in dark gray in Fig. 6). The period Tv [i] is affected by two frequencies, i.e., fv [n − 1] corresponding to d[n − 1] and fv [n] corresponding to d[n]. The nth CKV cycle is advanced to ξ[n − 1]Tv [n − 1] when the positive edge of the REF clock triggers a change in the DCO frequency. Consequently, the oscillator completes its remaining cycle, i.e., (1 − ξ[n − 1])Tv [n] with the updated output frequency fv [n]. Therefore, the DCO period Tv [i] with an intermediate frequency change is modeled as Tv [i] = ξ[n−1]Tv [n−1]+(1−ξ[n]) Tv [n]+ηDCO [i]
(16)
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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 56, NO. 11, NOVEMBER 2009
TABLE I ADPLL S IMULATION C ONFIGURATION
where ηDCO [i] accounts for the DCO noise. Transient effects like amplitude-modulation-to-phase-modulation noise conversion are not considered. B. Modeling Injection Pulling In accordance with the injection pulling model in [1], we have modeled hp,2 (t) as a rectangular function
(17) hp,2 (t) = gp,2 u(t) − u t − Tp,2 where u(t) is the continuous-time step function, Tp,2 is the injection pulling time, and gp,2 is a gain factor. Note that four CKV cycles (shown in dark and light gray in Fig. 6) are affected by the transition of the injection pulling frequency. Similar to a tuning word update, the injection pulling pulse may start and end at any time within one CKV cycle (depicted in light and dark gray in Fig. 6) and thus has to be accordingly modeled. C. Simulation Results We have simulated an ADPLL with a retimed reference architecture and an ADPLL with a synchronous reference architecture with the configuration in Table I. Note that the simulation setup agrees with the simulation in [1, Fig. 7], where the actual output frequency is the DCO output divided by two. Expressing the phase noise in decibels relative to the carrier per hertz and using the same parameters yields the same result as in [1, Fig. 7]. Since we have investigated discrete tones in the spectrum, we plot the graphs in decibels relative to the carrier, instead of decibels relative to the carrier per hertz. The simulated results of both architectures are compared with the values of Ak (jΩ) converted into the phase domain by integration, i.e., Ak (jΩ)/(jΩ). The number of spurs, their frequency location, and their amplitudes match with the theory given by (4) for the retiming architecture and given by (6) for the synchronous reference architecture. In both architectures, the reference spurs A0 (jΩ)/(jΩ) and the injection mismatch spurs AP/2 (jΩ)/(jΩ) have similar amplitudes. To mitigate the reference spurs, the coupling effects on the die and, simultaneously, the injected frequency (the gain gp,2 of the impulse response hp,2 (t) in the model in Fig. 1) have to be reduced. Matching the load on both edges, i.e., eliminating the mismatches of the pulses, avoids the injection mismatch spurs in the synchronous reference architecture. In the retimed reference architecture, the injection mismatch spurs will only reduce their amplitude to the level of the side spurs, because of the remaining deviation r[P/2]. Finally, the side spurs of the retimed reference architecture appear at up to −100 dBc. By contrast, no side spurs are evident in the phase noise of the synchronous reference architecture in Fig. 9.
Fig. 9. Phase noise of the synchronous reference ADPLL with injection pulling and a frequency command word of Nr = 63 + 2/5, i.e., a period of M = 5.
VI. C ONCLUSION In this brief, we have analyzed the periodically time-varying sampling clock of the phase-domain ADPLL with a retimed reference architecture. Any disturbance on the system introduces shifted and scaled spectral copies of the disturbance in the output phase noise spectrum. In addition to reference spurs due to injection pulling and injection mismatch spurs due to different pulling forces between rising and falling edges, side spurs due to the periodically nonuniform clock appear in the output phase noise power spectrum. The amplitude and number of spurs depend on the synthesized frequency or, more specifically, on the fractional part of the frequency command word. We have presented an alternative implementation of a phasedomain ADPLL that avoids a retiming mechanism and uses the uniform reference clock for the entire system. Behavioral simulations show that these critical side spurs are not evident in the synchronous reference architecture. R EFERENCES [1] K. Waheed, R. B. Staszewski, and J. Wallberg, “Injection spurs due to reference frequency retiming by a channel dependent clock at the ADPLL RF output and its mitigation,” in Proc. IEEE ISCAS, May 2007, pp. 3291–3294. [2] R. B. Staszewski, C.-M. Hung, K. Maggio, J. Wallberg, D. Leipold, and P. T. Balsara, “All-digital phase-domain TX frequency synthesizer for Bluetooth radios in 0.13 μm CMOS,” in Proc. IEEE ISSCC, Feb. 15–19, 2004, pp. 272–273. [3] R. B. Staszewski, J. L. Wallberg, S. Rezeq, C.-M. Hung, O. E. Eliezer, S. K. Vemulapalli, C. Fernando, K. Maggio, R. Staszewski, N. Barton, M.-C. Lee, P. Cruise, M. Entezari, K. Muhammad, and D. Leipold, “All-digital PLL and transmitter for mobile phones,” IEEE J. Solid-State Circuits, vol. 40, no. 12, pp. 2469–2482, Dec. 2005. [4] R. B. Staszewski, J. Wallberg, S. Rezeq, C.-M. Hung, O. Eliezer, S. Vemulapalli, C. Fernando, K. Maggio, R. Staszewski, N. Barton, M.-C. Lee, P. Cruise, M. Entezari, K. Muhammad, and D. Leipold, “Alldigital PLL and GSM/EDGE transmitter in 90 nm CMOS,” in Proc. IEEE ISSCC, Feb. 6–10, 2005, vol. 1, pp. 316–317. [5] S. Mendel, C. Vogel, and N. Da Dalt, “Signal and timing analysis of a phase-domain all-digital phase-locked loop with reference retiming mechanism,” in Proc. 16th Int. Conf. Mixed Des. Integr. Circuits Syst., Lodz, Poland, Jun. 25–27, 2009, pp. 681–687. [6] S. Mendel and C. Vogel, “A z-domain model and analysis of phase-domain all-digital phase-locked loops,” in Proc. 25th IEEE Norchip Conf., Aalborg, Denmark, Nov. 19–20, 2007, pp. 1–6. [7] R. B. Staszewski and P. T. Balsara, All-Digital Frequency Synthesizer in Deep-Submicron CMOS. Hoboken, NJ: Wiley, 2006. [8] I. L. Syllaios, R. B. Staszewski, and P. T. Balsara, “Time-domain modeling of an RF all-digital PLL,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 55, no. 6, pp. 601–605, Jun. 2008.
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 56, NO. 11, NOVEMBER 2009
A Phase-Domain All-Digital Phase-Locked Loop Architecture Without Reference Clock Retiming Stefan Mendel, Student Member, IEEE, Christian Vogel, Member, IEEE, and Nicola Da Dalt, Member, IEEE
Abstract—State-of-the-art phase-domain all-digital phaselocked loops (ADPLLs) require a retimed reference clock to synchronize the digitally controlled oscillator (DCO) output frequency and the reference clock frequency. Therefore, the entire digital logic is operated with a periodically nonuniform clock. Due to on-chip coupling effects, the DCO output frequency is pulled with the edges of the retimed reference clock, producing undesired spurs in the phase noise power spectrum. In this brief, we analyze and classify the spur generation from a signal processing point of view and propose an alternative ADPLL implementation that abandons the retiming mechanism. Thus, the entire ADPLL can be clocked with a uniform reference clock, and consequently, side spurs are avoided. Behavioral simulations verify the spur analysis and emphasize the improved behavior of the proposed synchronous reference architecture. Index Terms—All-digital phase-locked loops (ADPLLs), injection pulling, metastability, nonuniform sampling, reference spurs, side spurs.
I. I NTRODUCTION
P
ARASITIC coupling between the digital circuitry and the inductance–capacitance oscillator, which share the same substrate, power, and ground planes [1], causes a periodic disturbance of the oscillator. The rising and falling edges of the nonuniform retimed reference clock trigger the massive digital logic, which “pulls” the digitally controlled oscillator (DCO) output frequency. This effect produces undesired spurs in the output phase noise spectrum. In [1], the spurs are separated into reference spurs and side spurs. Reference spurs are caused by injection pulling, whereas side spurs are caused by injection pulling and the periodically time-varying retimed reference clock. The retimed reference clock is used to synchronize the fast DCO clock domain with the clock domain of the slow reference clock within the ADPLL [1]–[4]. Furthermore, it was reported in [1] that some measured side spurs have been close to the margins of the GSM specification. Reducing the coupling on the die through careful circuit design mitigates these spurs; however, in this brief, we present an alternative
Manuscript received February 11, 2009; revised June 28, 2009. Current version published November 18, 2009. The work of S. Mendel was supported by Infineon Technologies Austria AG. The work of C. Vogel was supported by the Austrian Science Fund (FWF) Erwin Schroedinger Fellowship J2709-N20. This paper was recommended by Associate Editor S. Pamarti. S. Mendel is with the Christian Doppler Laboratory for Nonlinear Signal Processing, Graz University of Technology, 8010 Graz, Austria (e-mail: [email protected]). C. Vogel was with the Signal and Information Processing Laboratory, Swiss Federal Institute of Technology (ETH) Zürich, 8092 Zürich, Switzerland. He is now with the Signal Processing and Speech Communication Laboratory, Graz University of Technology, 8010 Graz, Austria (e-mail: [email protected]). N. Da Dalt is with the Infineon Technologies Development Center, 9500 Villach, Austria (e-mail: [email protected]). Digital Object Identifier 10.1109/TCSII.2009.2034079
Fig. 1. Injection pulling model: The nonuniform impulse train, corresponding to the rising and falling edges of the retimed reference clock s(t), is decomposed into P sampling functions sp (t). The 2-periodic impulse response hp,2 (t) models the shape of the frequency injection pulse for rising and falling edges, i.e., hp,2 = h0 (t) when p is even and hp,2 = h1 (t) when p is odd.
architecture that solves the problem of side spurs on the system level. Therefore, we first analyze the generation of spurs due to injection pulling and then propose a phase-domain ADPLL operated by a uniform reference clock without retiming that does not generate side spurs. II. R EFERENCE S PURS , S IDE S PURS , AND I NJECTION M ISMATCH S PURS This section analyzes the generation of injection pulling spurs, their frequencies and amplitudes, and their dependence on the frequency command word Nr . Basically, we can distinguish between three kinds of spurs: reference spurs, side spurs, and injection mismatch spurs. Reference spurs are caused by a periodic injection pulling signal, which is due to parasitic coupling effects on the die. The periodic nonuniform retimed reference clock CKR of the ADPLL in [2]–[4] generates side spurs by shifting the energy of the reference spurs to additional frequencies. Different gains of the injected frequency among rising and falling CKR edges lead to injection mismatch spurs. A. General Injection Pulling Model Injection pulling changes the DCO output frequency fv (t) over a period shorter than a reference cycle. As the frequencyto-phase conversion in the feedback path of an ADPLL is basically an integration over one reference cycle, the error due to injection pulling appears as a constant factor in the phase error. The loop compensates this factor, and consequently, the analysis of injection pulling can neglect the feedback mechanism, which leads to the open-loop model shown in Fig. 1. The output signal fv (t) can be decomposed into an ideal
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MENDEL et al.: PHASE-DOMAIN ADPLL ARCHITECTURE WITHOUT REFERENCE CLOCK RETIMING
Fig. 2.
ADPLL architecture with a retimed reference mechanism [2]–[4].
signal f˜v (t), which is constantly in lock, and an undesired injection pulling signal fip (t). The nonuniform impulse train s(t) represents the rising and falling edge events of the periodically nonuniform retimed reference clock and is decomposed into P sampling functions sp (t) at a P -time lower rate. With each Dirac impulse of sp (t), the injection pulling generation filter produces an injection pulse. The 2-periodic impulse response hp,2 (t), where p, 2 stands for p modulo 2, accounts for the different pulse shapes of the rising and falling CKR edges. To evaluate the effects of the injection pulling signal fip (t) on the output frequency fv (t), we apply the injection pulling model to the retimed reference architecture. First, we describe the P uniform impulse trains sp (t), whose sum represent the periodically nonuniform retimed reference clock, and then convolve sp (t) with the injection pulling generation impulse responses hp,2 (t). B. Retimed Reference Clock The architecture shown in Fig. 2 uses a retimed reference clock CKR to synchronize the reference phase ϕr [m] and the variable phase ϕv [i], where the signal ε[m] compensates for the retiming error [2]–[4]. As shown in Fig. 3, the edges of the slow reference clock REF (frequency fr = 1/Tr and time index n) are delayed to the subsequent rising edge of the fast DCO output clock CKV (frequency fv = 1/Tv and time index i) to produce the nonuniform retimed reference clock CKR (average frequency fr and time index m). The retiming mechanism can be implemented with flip-flops, as shown in Fig. 2. In the steady state, the retimed reference clock CKR has an average period of Tr = Nr × Tvss , where Tvss = 1/fvss denotes the DCO output period in the steady state. The clock follows a certain periodic pattern with a period given by the denominator M of Nrfrac = L/M , where Nr = Nrint + Nrfrac , and L and M are relative prime integers. For example, if Nr = 100 + 1/5, i.e., Nrint = 100, Nrfrac = 1/5, and M = 5, then four reference cycles are 100 × Tvss long, and every fifth reference cycle is 101 × Tvss long. This pattern will periodically repeat with period M = 5 [5]. The signal s(t) in Fig. 3 describes the rising and falling edge events of the clock signal CKR (solid) as a train of Dirac impulses δ(t). As illustrated in Fig. 3, the time shifts between the nonuniform impulse train (solid) and the uniform impulse train with constant period Tr /2 (dashed) are given by ε[m]Tvss for the rising CKR edges and ε[m]Tvss for the falling CKR edges. For the sake of brevity, we introduce relative time
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Fig. 3. Reference clock REF, variable clock CKV, retimed reference clock CKR, and the impulse train s(t) corresponding to the rising and falling edges of the uniform clock REF (dashed) and the nonuniform clock CKR (solid) in the steady state for Nr = 2 + 1/4.
offsets r[p], which are the deviations normalized to the half Tr /2 of the uniform period, i.e., 2 ε[p/2], if p is even r[p] = N2r (1) ε [(p − 1)/2] , if p is odd Nr where we used Tr = Tvss × Nr . Since ε[m] and ε[m] are periodic with M , the nonuniform sampling train s(t) with the relative time offsets r[p] is periodic with P = 2M , i.e., P −1 ∞ Tr s(t) = δ t − (lP + p + r[p]) . (2) 2 p=0 l=−∞ sp (t)
C. Injection Pulling Signal The injection pulling signal fip (t) is given by the sum of the convolutions of the impulse responses hp,2 (t) with the nonuniform impulse trains sp (t) in (2), i.e., ∞ P −1 Tr fip (t) = hp,2 t − (lP + p + r[p]) . (3) 2 p=0 l=−∞
After applying the continuous-time Fourier transform (CTFT) to (3) and some simplifications, we obtain ∞ 2 2 × 2πfr Fip (jΩ) = 2πδ Ω − k Ak (jΩ) (4) Tr P k=−∞
with Ak (jΩ) =
P −1 Tr 2π 1 Hp,2 (jΩ)e−jΩr[p] 2 e−jkp P P p=0
(5)
and Hp,2 (jΩ) is the CTFT of hp,2 (t). The spectrum Fip (jΩ) in (4) allows for describing the frequency locations and the amplitudes of the spurs caused by injection pulling. Based on this description, we can classify the spurs into reference spurs, side spurs, and injection mismatch spurs. An example of such an output spectrum [converted into the phase domain by integration, i.e., Fip (jΩ)/(jΩ)] is shown in Fig. 4. Basically, the spectrum consists of P = 2M spurs uniformly spaced between 0 and 2fr , which are periodically repeated with 2fr . The amplitudes of the spurs are given by the frequency
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Fig. 4. Phase noise of the reference retimed ADPLL with injection pulling and a frequency command word of Nr = 63 + 2/5, i.e., a period of M = 5.
response Ak (jΩ), which depends on the time offsets r[p] and the impulse responses hp,2 (t). Reference spurs are introduced by injection pulling, located at multiples of (2fr ), and weighted by A0 (jΩ). Side spurs are caused by the time shifts r[p] of the injection pulling signal due to the nonuniform clock CKR. They appear at k(2fr /P ) + l(2fr ) weighted by Ak (jΩ) with k = 1, . . . , P − 1 and l = 1, . . . , ∞. Injection mismatch spurs are determined by the periodicity (with period two) of the impulse responses hp,2 (t). They are located at fr + l(2fr ) weighted by AP/2 (jΩ) with l = 1, . . . , ∞. Note that injection mismatch spurs and side spurs contribute energy to AP/2 (jΩ). When we assume that injection pulling appears with a uniform clock signal, the time offsets r[p] are zero, and we can simplify (4) to ∞ 2
2πδ(Ω − kπ4fr )A0 (jΩ) Fip (jΩ) = Tr k=−∞ + 2πδ(Ω − 2πfr − k4πfr )AP/2 (jΩ) (6)
Fig. 5.
ADPLL architecture with synchronous reference timing.
Fig. 6. Relation between the reference clock REF, the variable clock CKV, and the injection pulling signal fip (t).
the phase-domain ADPLL remains, we present an alternative way to extract the phase information from the oscillating DCO output signal. Basically, we measure the number of CKV cycles within one REF cycle, which is denoted as Nv [n]. Accumulating Nv [n] at the rate of the uniform reference frequency gives the variable phase, i.e., ϕv [n] = ϕv [n − 1] + Nv [n]
and (5) to 1 (H0 (jΩ) + H1 (jΩ)) 2 1 AP/2 (jΩ) = (H0 (jΩ) − H1 (jΩ)) . 2
(8)
which can directly be compared with the reference phase
A0 (jΩ) =
(7)
Thus, all side spurs vanish. Only the reference spurs with the weight A0 (jΩ) and the injection mismatch spurs with the weight AP/2 (jΩ) remain in the spectrum. In case the injection pulling signal is identical for rising and falling edges, the 2-periodic impulse response hp,2 (t) simplifies to a nonperiodic impulse response h(t), and the weight AP/2 (jΩ) becomes zero. We can conclude that an ADPLL with a uniform clock does not generate side spurs. III. S YNCHRONOUS R EFERENCE A RCHITECTURE In this section, we propose an alternative phase-domain ADPLL, which is shown in Fig. 5, that avoids the retiming of the reference clock and, thus, the generation of side spurs. In contrast to [2]–[4], the entire digital logic is clocked by the uniform reference clock REF.1 While the principal structure of 1 The synchronization between the CKV and the REF clock domains is done with a dedicated circuit, which is presented in Section IV.
ϕr [n] = ϕr [n − 1] + Nr .
(9)
In the steady state, the value of Nv [n] equals Nr and may be a fractional number consisting of an integer part Nvint and a fractional part Nvfrac . To measure the variable phase ϕv [n], we split the computation into an integer part ϕint v [n] and a fractional part ϕfrac v [n], i.e., frac ϕv [n] = ϕint v [n] + ϕv [n] int = ϕint v [n − 1] + Nv [n] frac + ϕv [n − 1] + Nvfrac [n].
(10)
In practice, the integer part ϕint v [n] is determined by accumulating 1 at rate CKV and sampling its value with the reference clock REF instead of CKR in Fig. 2. As illustrated in Fig. 6, counting the number of rising edge events corresponds to the integer number of CKV periods Nvint [n] plus one, resulting in int
int ϕint (11) v [n] = ϕv [n − 1] + Nv [n] + 1 . Accordingly, the fractional part of the variable phase accumulates Nvfrac [n] minus one, so that the sum of the variable
MENDEL et al.: PHASE-DOMAIN ADPLL ARCHITECTURE WITHOUT REFERENCE CLOCK RETIMING
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Fig. 8. Metastability avoidance circuit. Fig. 7.
Synchronous reference timing mechanism in lock for Nr = 1 + 1/2.
frac integer phase ϕint v [n] and the variable fractional phase ϕv [n] yields (8). Determining the fractional part ϕfrac v [n] is more difficult, because the REF clock and the CKV clock are not synchronized. Fig. 6 shows the variable clock CKV for one reference cycle REF. The fractional part Nvfrac [n] consists of the fractional part ε[n] at the beginning of one REF cycle and the fractional part ξ[n] at the ending of one REF cycle, i.e.:
Nvfrac [n] = ε[n] + ξ[n]
(12)
where ξ[n] is the time between the rising edge of CKV and the following rising edge of REF normalized by Tv , while ε[n] is the time between the rising edge of REF and the following rising edge of the CKV clock normalized by Tv . One way to compute the fractional part Nvfrac [n] is to measure ε[n] and ξ[n] with a time-to-digital converter (TDC). Alternatively, by assuming that Tv [n] ≈ Tv [n − 1], we can relate ε[n] and ξ[n − 1] (cf. Fig. 6) as ε[n] ≈ 1 − ξ[n − 1].
(13)
During the locking process, the approximation in (13) introduces an insignificant error, which is getting smaller as Tv [n] approaches Tvss . Finally, in the steady state, (13) will be exact. Accumulating (Nvfrac [n] − 1) with (12) and (13) and solving the recursive relation yields the fractional part of the variable phase ϕfrac v [n], i.e.: frac ϕfrac v [n] = ϕv [n−1]+(ξ[n]−ξ[n−1]) = ξ[n]−ξ[0].
(14)
The initial value of ξ[0] in (14) can be neglected, because a constant phase error will be compensated by the control loop. Finally, by using the reference phase ϕr [n] from (9) and the variable phase ϕv [n] from (8), the phase error ϕe [n] is given by ϕe [n] = ϕr [n] − ϕv [n].
(15)
Fig. 7 illustrates the synchronous reference timing mechanism in lock for Nr = 1 + 1/2. Note that the transfer function of the synchronous reference architecture matches the transfer function of the reference retimed architecture (with the exception of slightly different sampling instances [6]). Consequently, both architectures have equivalent noise suppression capabilities, but the synchronous reference architecture, which uses a uniform clock, is better concerning injection pulling, as discussed in Section II.
IV. M ETASTABILITY AVOIDANCE In (11), the variable phase ϕv [i] of the rate of the fast CKV clock is sampled by the slow clock REF. Since these clocks are not synchronized, metastability problems may occur when both rising edges coincide. Metastable states must be avoided, because the ADPLL immediately loses lock. Fortunately, the TDC measures the relation between both edges with a higher resolution (typically, an inverter delay of 20 ps) than Tv , and the gained information about ξ[n] can be used to avoid metastability [7]. Therefore, the value of the accumulator ϕv [i] is additionally sampled with the negative edge of CKV to produce ϕv [i]. In case the positive edges of CKV and CKR happen to be close to each other, the well-defined value of ϕv [i] can be used for further processing instead of the possibly corrupted value of ϕv [i]. Since the value of ϕv [i] will be updated when ξ[n] = 1/2, we distinguish between two cases: if ξ[n] is close to 1, i.e., ξ[n] > 1 − ξT , where ξT is a certain threshold, e.g., ξT = 1/4, we will use ϕv [i], and if ξ[n] is close to 0, i.e., ξ[n] < ξT , we will use ϕv [i] + 1, because the value of ϕv [i] was not yet updated. Fig. 8 shows the metastability avoidance circuit (MAC). Additionally, the circuit may be gated to minimize the power consumption and switched on if needed. Metastable states, i.e., ξ[n], may be predicted from its previous value ξ[n] = (ξ[n − 1] + Nrfrac ) mod 1, where mod denotes the modulo operation [5]. V. S IMULATIONS The simulations were carried out in a high-level time-domain simulation environment according to [8]. Since the proposed synchronous reference architecture is slightly different from the retimed reference architecture, the model has slightly been modified. A. Modeling Synchronous Reference Timing The change of the tuning word d[n] may occur at any time during a variable period Tv [i] (shown in dark gray in Fig. 6). The period Tv [i] is affected by two frequencies, i.e., fv [n − 1] corresponding to d[n − 1] and fv [n] corresponding to d[n]. The nth CKV cycle is advanced to ξ[n − 1]Tv [n − 1] when the positive edge of the REF clock triggers a change in the DCO frequency. Consequently, the oscillator completes its remaining cycle, i.e., (1 − ξ[n − 1])Tv [n] with the updated output frequency fv [n]. Therefore, the DCO period Tv [i] with an intermediate frequency change is modeled as Tv [i] = ξ[n−1]Tv [n−1]+(1−ξ[n]) Tv [n]+ηDCO [i]
(16)
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TABLE I ADPLL S IMULATION C ONFIGURATION
where ηDCO [i] accounts for the DCO noise. Transient effects like amplitude-modulation-to-phase-modulation noise conversion are not considered. B. Modeling Injection Pulling In accordance with the injection pulling model in [1], we have modeled hp,2 (t) as a rectangular function
(17) hp,2 (t) = gp,2 u(t) − u t − Tp,2 where u(t) is the continuous-time step function, Tp,2 is the injection pulling time, and gp,2 is a gain factor. Note that four CKV cycles (shown in dark and light gray in Fig. 6) are affected by the transition of the injection pulling frequency. Similar to a tuning word update, the injection pulling pulse may start and end at any time within one CKV cycle (depicted in light and dark gray in Fig. 6) and thus has to be accordingly modeled. C. Simulation Results We have simulated an ADPLL with a retimed reference architecture and an ADPLL with a synchronous reference architecture with the configuration in Table I. Note that the simulation setup agrees with the simulation in [1, Fig. 7], where the actual output frequency is the DCO output divided by two. Expressing the phase noise in decibels relative to the carrier per hertz and using the same parameters yields the same result as in [1, Fig. 7]. Since we have investigated discrete tones in the spectrum, we plot the graphs in decibels relative to the carrier, instead of decibels relative to the carrier per hertz. The simulated results of both architectures are compared with the values of Ak (jΩ) converted into the phase domain by integration, i.e., Ak (jΩ)/(jΩ). The number of spurs, their frequency location, and their amplitudes match with the theory given by (4) for the retiming architecture and given by (6) for the synchronous reference architecture. In both architectures, the reference spurs A0 (jΩ)/(jΩ) and the injection mismatch spurs AP/2 (jΩ)/(jΩ) have similar amplitudes. To mitigate the reference spurs, the coupling effects on the die and, simultaneously, the injected frequency (the gain gp,2 of the impulse response hp,2 (t) in the model in Fig. 1) have to be reduced. Matching the load on both edges, i.e., eliminating the mismatches of the pulses, avoids the injection mismatch spurs in the synchronous reference architecture. In the retimed reference architecture, the injection mismatch spurs will only reduce their amplitude to the level of the side spurs, because of the remaining deviation r[P/2]. Finally, the side spurs of the retimed reference architecture appear at up to −100 dBc. By contrast, no side spurs are evident in the phase noise of the synchronous reference architecture in Fig. 9.
Fig. 9. Phase noise of the synchronous reference ADPLL with injection pulling and a frequency command word of Nr = 63 + 2/5, i.e., a period of M = 5.
VI. C ONCLUSION In this brief, we have analyzed the periodically time-varying sampling clock of the phase-domain ADPLL with a retimed reference architecture. Any disturbance on the system introduces shifted and scaled spectral copies of the disturbance in the output phase noise spectrum. In addition to reference spurs due to injection pulling and injection mismatch spurs due to different pulling forces between rising and falling edges, side spurs due to the periodically nonuniform clock appear in the output phase noise power spectrum. The amplitude and number of spurs depend on the synthesized frequency or, more specifically, on the fractional part of the frequency command word. We have presented an alternative implementation of a phasedomain ADPLL that avoids a retiming mechanism and uses the uniform reference clock for the entire system. Behavioral simulations show that these critical side spurs are not evident in the synchronous reference architecture. R EFERENCES [1] K. Waheed, R. B. Staszewski, and J. Wallberg, “Injection spurs due to reference frequency retiming by a channel dependent clock at the ADPLL RF output and its mitigation,” in Proc. IEEE ISCAS, May 2007, pp. 3291–3294. [2] R. B. Staszewski, C.-M. Hung, K. Maggio, J. Wallberg, D. Leipold, and P. T. Balsara, “All-digital phase-domain TX frequency synthesizer for Bluetooth radios in 0.13 μm CMOS,” in Proc. IEEE ISSCC, Feb. 15–19, 2004, pp. 272–273. [3] R. B. Staszewski, J. L. Wallberg, S. Rezeq, C.-M. Hung, O. E. Eliezer, S. K. Vemulapalli, C. Fernando, K. Maggio, R. Staszewski, N. Barton, M.-C. Lee, P. Cruise, M. Entezari, K. Muhammad, and D. Leipold, “All-digital PLL and transmitter for mobile phones,” IEEE J. Solid-State Circuits, vol. 40, no. 12, pp. 2469–2482, Dec. 2005. [4] R. B. Staszewski, J. Wallberg, S. Rezeq, C.-M. Hung, O. Eliezer, S. Vemulapalli, C. Fernando, K. Maggio, R. Staszewski, N. Barton, M.-C. Lee, P. Cruise, M. Entezari, K. Muhammad, and D. Leipold, “Alldigital PLL and GSM/EDGE transmitter in 90 nm CMOS,” in Proc. IEEE ISSCC, Feb. 6–10, 2005, vol. 1, pp. 316–317. [5] S. Mendel, C. Vogel, and N. Da Dalt, “Signal and timing analysis of a phase-domain all-digital phase-locked loop with reference retiming mechanism,” in Proc. 16th Int. Conf. Mixed Des. Integr. Circuits Syst., Lodz, Poland, Jun. 25–27, 2009, pp. 681–687. [6] S. Mendel and C. Vogel, “A z-domain model and analysis of phase-domain all-digital phase-locked loops,” in Proc. 25th IEEE Norchip Conf., Aalborg, Denmark, Nov. 19–20, 2007, pp. 1–6. [7] R. B. Staszewski and P. T. Balsara, All-Digital Frequency Synthesizer in Deep-Submicron CMOS. Hoboken, NJ: Wiley, 2006. [8] I. L. Syllaios, R. B. Staszewski, and P. T. Balsara, “Time-domain modeling of an RF all-digital PLL,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 55, no. 6, pp. 601–605, Jun. 2008.
