A Prevenient Voltage Stress Test Method for High ... - Semantic Scholar
A Prevenient Voltage Stress Test Method for High Density Memory Jongsoo Yim1, Gunbae kim1, Incheol Nam2, Sangki Son2, Jonghyoung Lim2, Hwacheol Lee2, Sangseok Kang2, Byungheon Kwak2, Jinseok Lee2 and Sungho Kang1 1 Department of Electrical and Electronic Engineering, Yonsei University, Seoul, Korea 2 Samsung Electronics, Memory Division, DRAM PE Team, Hwasung, Korea 1 jerry017, [email protected], [email protected] 2 {ic.nam, sangki.son, limjh, hc0905.lee, kss.kang, b.h.kwak, jsl001}@samsung.com
Abstract The most effective acceleration factor of reliability is the high voltage stress. However high electric field generated on thin gate oxide transistors in nanometer technology becomes the uppermost limit. In this paper, an improved voltage stress method for DRAM with the 6F2 structure and the open bit line scheme is proposed to enhance the Early Life Failure Rates (ELFR) and the yield of package test. The proposed method reduces the degradation of transistors caused by a high voltage stress. Experimental results show that the proposed method improves the yield of package test and the characteristic of refresh, and avoids the degradation of transistors using voltage ramp stress (VRS).
1. Introduction Burn-in test is a method used to detect infant mortality by applying higher levels of stress to accelerate the deterioration of electronic devices. However, burn-in test itself may affect the yield of devices. It results from the fact that systematic defects grow during burn-in test and some of them end up in yield-loss [1]. The breakdown mechanism of the gate oxide is in close connection with the growth of defects under the given voltage and temperature. The amount of defect growth and yield-loss depend upon the environment of burn-in test, such as stress time, temperature, voltage, and stress patterns [2]. During SHOrt Voltage Elevation (SHOVE) test, stress factors are run at higher than normal supply voltage for a short period. This procedure is effective for screening thin gate oxide defects. This approach deals with 3.3V and 5V technologies where the electric field value is about 6MV/cm. For current technologies, operating voltage becomes lower than 2.0V and the
breakdown voltages of conventional DRAM are higher than those of [3]. SHOVE does not give the acceleration of cell to cell defects and cell to bit-line defects, etc. Dynamic Voltage Stress (DVS) is proposed as the method which can reduce burn-in stress time and skip the pre-burn-in testing or on board level testing. After DVS test is done, the normal test process is carried out again. Defects that were activated by the DVS, is especially good at activating dielectric gate defects [4]. Other approaches (i.e. Enhanced Voltage Stress, Low Voltage Stress, and IDDQ Test) have been used as an effective acceleration method [5]. Since these methods could not satisfy the specification of reliability and can not become alternative-reliability test methods. As the circuit complexity increases and the gate oxide thickness is continuously scaled down, the fundamental degradation mechanisms of thin gate oxide transistors have been changed. The burn-in test methodology becomes more difficult to exactly stress all the gate oxides in a circuit. Since this generates highest voltages across thin gate oxide while simultaneously pushing electric fields higher, the effectiveness of a voltage stress test must fall off. It has been recognized that a high electric oxide field on the gate oxide causes a dielectric degradation in the FN (Fowler-Nordheim) regime [6]. In the ultra-thin gate oxide, excessive acceleration factors, such as high electric field on the gate oxide and high temperature, give rise to the degradation of device performances [7]. By the constant high voltage stress and high temperature, it is impossible to satisfy rising attention for the reliability assessment. In recent years, numerous studies have attempted to find and explore the appropriate acceleration method [8-9]. To enhance the reliability using a high voltage test without the deterioration of electric devices, we try to find out a new approach under a less elevated
1.2
Thershold voltage, Vth [V]
The gate oxide thickness decreases and the oncurrent increases according to each technology. Larger on-current will charge the capacitors faster, and as a result, the circuit speed increases. The generation rate of Stress Induced Leakage Current (SILC) and Charge to BreakDown (QBD) in ultra thin gate oxides is controlled by the gate voltage. It is well known that the high electric field FN stress on thin gate oxides can lead to increase in gate oxide leakage current as well as threshold voltage shift. Indeed, numerous operations under the stress condition, which increase interfacetrapped charges in the gate oxide, cause the gate oxide degradation, mainly due to the successive electric fields applied across the gate oxide, as shown in Figure 1 [10].
Threshold voltage, Vth [V]
2. Degradation in thin oxide gate
as shown in Figure 3. These results are explained by unnecessary charges in the gate oxide. Drain current, ID [A]
acceleration environment by changing a stress voltage type as a ramp stress.
1.0
0.8
0.6
0.4 0.8
1.0
1.2
1.4
1.6
1.8
Ratio of stress voltage
Figure 2. Degradation under the high voltage stress A typical burn-in temperature is raised to between 100°C and 140°C. Besides 125°C also 140°C is also a well-established burn-in temperature. The junction temperature is defined as the temperature of the silicon substrate. 6.0
200
5.8
180
5.6
160
5.4
140
5.2
120
100
5.0 5.0
5.2
5.4
5.6
5.8
6.0
100
120
140
160
180
200
Figure 3. Phenomena of the before and after a high voltage stress at 8.3MV/cm electric-filed in 80nm CMOS technology
Figure 1. Diagram of the interface-trapped charges of FN-tunnelling in DRAM
During the FN stress, a constant voltage stress (CVS) is applied to the gate with the source, drain, and substrate connected to ground. In high field between the gate and the well-body, FN-stress is occurred. On burn-in stress, many transistors are operating under the FN-stress condition. This is because word-lines are enabled, but bit-lines and cell nodes are in the ground level (Vss) as if we write “zero” on the cell. The degradation results of the drain current and the threshold voltage are shown in Figure 2. This kind of changes on the degradation has been observed in high density DRAM at Samsung with 80nm process of 1Gb DDR2. When the higher stress voltage is given, the threshold voltage and drain current are increased. In the case of 1.6 times stress voltage, the value of Vth is shifted from 0.6V to 0.9V. After providing a constant high voltage stress, the precharge power down currents which can indicate the amount of off-state leakage currents move toward highly, and the number of refresh time fail bits increase
The junction temperature increases with technology scaling due to increased transistor density, larger chip size, and increased leakage currents. Therefore, it is a key parameter of reliability and burn-in testing. The self-generated temperature in the burn-in environment contributes to the larger currents that can lead to further increase of the junction temperature, the possible thermal run away, and yield-loss of good parts. Indeed, the high density memory, such as 1Gb DDR2, has the characteristic of the various distributions and the increase of the operating-currents under the high temperature environment. Variation of self refresh current according to increase of the ambient temperature on a 1Gb DDR2 in 68nm CMOS technology at 1.8V VDD is shown in Figure 4. The same number of devices is measured on the different temperature environments. Figure 4 shows that the device current has a 3 times wide standard variation and higher mean current at the high temperature. It means that the junction current of the high temperature is higher than that of the low temperature condition. Moreover, major factor of the leakage, such as sub threshold leakage, increases exponentially according to the temperature. Therefore the burn-in temperature
Number of devices (EA)
Number of devices (EA)
must be reduced in step with the technology scaling. As technology shrinks, additional care must be taken to set stress voltages and temperatures properly to develop and evaluate tests in order to ensure that an acceptable acceleration factor is achieved.
Figure 4. Variation of self refresh current depends on the temperature
3. A new voltage stress method Practically, the acceleration of temperature and the stress time is very limited in the burn-in test. The most effective acceleration method is the variation of voltages. The CVS method is commonly used as the methodology for reliability screening. This method developed for ultra-thin SiO2 based dielectric gates. The voltage acceleration factors, the shape parameter of the Weibull distribution (ß) and the thermal activation energy (Ea) are required as a basic parameter for reliability prediction. Addition to both ßvalue and Ea, an effective reliability screening method needs to focus on the total stress time. Recently, a new breakdown time model was proposed. This model (Eq.1) includes the gate oxide thickness (Tox) and the gate voltage (VG) [11].
where γ is the acceleration factor, Ea is the activation energy, α is the oxide thickness acceleration factor, To is a constant for a given technology, and Tj is the average junction temperature. To determine the optimized stress time in burn-in test, it is need to look more closely at tradeoffs. It is a paradox that the high voltage stress is the most variable acceleration factor and yet has a relatively serious degradation of devices. In order to achieve a high reliability in spite of operating at the high voltage level, we can find a
solution in flash memory. The amount of interface trapped charges determines the threshold voltage and the off-state current. In the conventional flash devices, non-uniformities in the process or changes in the environment widely vary the required number of program pulses. The Incremental Step Pulse Programming (ISPP) has been provided fast programming performance under the process and the environmental variations while still keeping a tight programmed cell threshold voltage distribution. This method optimizes the interface trapped charges in the floating gate [12]. Hence, with the identical ISPP method concept, the VRS method which increases the gate voltage as a step pulse has the advantage to reduce the interface trapped charges in the gate oxide by the FN-tunneling in DRAM caused by the CVS. Although each method has a different voltage acceleration type, the CVS and the VRS have an equivalent result in terms of breakdown voltage distributions and TBD distributions. In the ability of the lifetime prediction, the VRS method shows a negligible variation in the measurement time.
Figure 5. Types of voltage stress (a) Constant voltage stress (b) Voltage ramp stress
Compared with the CVS, the VRS method has lower summation of voltage accelerate factor. However under the same stress time, VRS makes enhanced refresh characteristics and the improvement of the yield. A lower voltage than the user condition has not an acceleration effect. So the starting voltage is the user voltage as VA shown in Figure 5. The voltage of CVS (VB) generates about 8MV/cm electric field. In this evaluation, we will not take up the variation of the VRS in detail. The 0.1 voltage is determined as the variation of the VRS. In wafer level, burn-in stresses of the CVS and the VRS are directly applied to the test element group (TEG). Using the observation of the states of transistors and the split of burn-in condition, mass products are evaluated as in terms of the yield, the refresh time failure rate, and the reliability test in package level.
4. Experimental results To evaluate the effect of the voltage stress type, the drain saturation current is measured. The gate and drain voltage is forced at 6.7V for 100second in the CVS, and is from 5.8V to 6.7V by increasing 0.1V per 10second in the VRS. The peripheral thick transistor in TEG is used to evaluate the degradation of transistors in the CVS and the VRS conditions. The evaluation results are shown in Figure 6. As a result of measurement, the variations of Idsat are to be 13.4~15.0% at 6.7V of the CVS, and 2.9~3.0% of the VRS. The proposed VRS can reduce 72% the degradation of the saturation drain current in TEG level.
increase about 0.05% in VRS. This means that the ingredient of AC stress of the VRS more activates latent defects. Table 1. Yield comparison results
The variation of device parameters is also the index of the degeneration. At hot temperature package test, the criteria of degradation is refresh characteristic. According to the Table 2, refresh items, which detect the failure of transistors by disturbing and accelerating noise environments, are practically reduced. Even the leakage current of the flawless transistors is increased in the case of the high electric field on the thin gate oxide. This leakage current causes the failure of the refresh time. Figure 6. The saturation drain current variation versus stress time for peripheral thick transistor in TEG level
Each burn-in method is verified by mass chips. In terms of the yield, the refresh time fail rate, and reliability, we observed the difference between each method. Product reliability test (PRT) is processed by stressing + 0.5V, which is higher than the user voltage under 125℃ for 24 hours. If the failure rate of PRT and ILT meets the certain ppm, PRT can guarantee 6month operating life time and Infant lifetime test (ILT), stressing for 168 hours at 125℃ assures of 10 years operating life time at Samsung. For the verification and detail comparisons, the various burn-in methods are implemented using 1Gb DDR2 with 80nm CMOS technology. The sample number of each group is 4500. Table 1 shows detail comparison results between the previous CVS and the proposed VRS. Through the test yield and the failure rate of reliability, we can affirm that an adequate voltage stress such as the VRS type has an advantage. The yield of the VRS is 1.8% higher than that of the CVS and PRT and ILT rates are the same values. Although it does not mean that the quality of reliability in VRS is higher than CVS, we can assume the VRS is equivalent in the reliability with a less degradation. After burn-in test, the current failures relatively
Table 2. Failure rate comparison results
Therefore, as shown in experimental results, the proposed approach is an attractive and effective solution of the voltage stress test for thin gate oxide transistors.
5. Conclusion In this paper, a new voltage stress method for high density memory using the VRS is developed. Unlike previous approaches using the CVS, a reduction of degradation with the thin gate oxide transistors is achieved. By changing the voltage stress optimally, effectively enhanced test data with the minimum degradation during the VRS can be achieved. In addition, this method can increase the yield during the package test as well as the burn-in test operation. Therefore, this method can be applied for all thin gate
oxide transistors without a serous aggravation of devices. The future work is the development of the more efficient voltage stress test can be accomplished by dealing with various stress coverage.
[6] Rainer Duschl and Rolf-Peter Vollertsen, “Voltage acceleration of oxide breakdown in the sub-10 nm FowlerNordheim and direct tunneling regime”, Proceedings IEEE International Workshop on Integrated Reliability Workshop, Oct.2005, pp.17-20.
6. References
[7] Mesut Meterelliyoz, Hamid Mahmoodi, and Kaushik Roy, “A leakage control system for thermal stability during burn-in test”, Proceedings IEEE International Test Conference, Nov.2005, pp.10-16.
[1] Taeho Kim, Way Kuo and Wei-Ting Kary Chien, “Burnin effect on yield”, IEEE Transactions on Electronics Packaging Manufacturing,23(4), Oct. 2000, pp.293-299. [2] Way Kuo and Taeho Kim, “An overview of manufacturing yield and reliability modeling for semiconductor products”, Proceedings of the IEEE, 87(8), Aug. 1999, pp.1329-1344. [3] Jonathan T.-Y. Chang and Edward J. McCluskey, “SHOrt voltage elevation (SHOVE) test for weak CMOS ICs”, Proceedings 15th IEEE International Symposium on VLSI Test, Apr.1997, pp.446-451. [4] Chung-Yuan Tsao, R.Y. Shiue, C.C. Ting, Y.S. Huang, Y.C. Lin and J.T. Yue, “Applying dynamic voltage stressing to reduce early failure rate”, Proceedings 39th IEEE International Symposium on Reliability Physics, Apr.2001, pp.37-41. [5] Minh Quach, Tuan Pham, Tim Figal, Bob Kopitzke and Pete O'Neill, “Wafer-level defect-based testing using enhanced voltage stress and statistical test data evaluation”, Proceedings IEEE International Test Conference,Oct.2002, pp.683-692.
[8] F.Monsieur, E.Vincent, D.Roy, S.Bruyre, G. Pananakakis and G.Ghibaudo, “Time to breakdown and voltage to breakdown modeling for ultra thin oxides (Tox
Abstract The most effective acceleration factor of reliability is the high voltage stress. However high electric field generated on thin gate oxide transistors in nanometer technology becomes the uppermost limit. In this paper, an improved voltage stress method for DRAM with the 6F2 structure and the open bit line scheme is proposed to enhance the Early Life Failure Rates (ELFR) and the yield of package test. The proposed method reduces the degradation of transistors caused by a high voltage stress. Experimental results show that the proposed method improves the yield of package test and the characteristic of refresh, and avoids the degradation of transistors using voltage ramp stress (VRS).
1. Introduction Burn-in test is a method used to detect infant mortality by applying higher levels of stress to accelerate the deterioration of electronic devices. However, burn-in test itself may affect the yield of devices. It results from the fact that systematic defects grow during burn-in test and some of them end up in yield-loss [1]. The breakdown mechanism of the gate oxide is in close connection with the growth of defects under the given voltage and temperature. The amount of defect growth and yield-loss depend upon the environment of burn-in test, such as stress time, temperature, voltage, and stress patterns [2]. During SHOrt Voltage Elevation (SHOVE) test, stress factors are run at higher than normal supply voltage for a short period. This procedure is effective for screening thin gate oxide defects. This approach deals with 3.3V and 5V technologies where the electric field value is about 6MV/cm. For current technologies, operating voltage becomes lower than 2.0V and the
breakdown voltages of conventional DRAM are higher than those of [3]. SHOVE does not give the acceleration of cell to cell defects and cell to bit-line defects, etc. Dynamic Voltage Stress (DVS) is proposed as the method which can reduce burn-in stress time and skip the pre-burn-in testing or on board level testing. After DVS test is done, the normal test process is carried out again. Defects that were activated by the DVS, is especially good at activating dielectric gate defects [4]. Other approaches (i.e. Enhanced Voltage Stress, Low Voltage Stress, and IDDQ Test) have been used as an effective acceleration method [5]. Since these methods could not satisfy the specification of reliability and can not become alternative-reliability test methods. As the circuit complexity increases and the gate oxide thickness is continuously scaled down, the fundamental degradation mechanisms of thin gate oxide transistors have been changed. The burn-in test methodology becomes more difficult to exactly stress all the gate oxides in a circuit. Since this generates highest voltages across thin gate oxide while simultaneously pushing electric fields higher, the effectiveness of a voltage stress test must fall off. It has been recognized that a high electric oxide field on the gate oxide causes a dielectric degradation in the FN (Fowler-Nordheim) regime [6]. In the ultra-thin gate oxide, excessive acceleration factors, such as high electric field on the gate oxide and high temperature, give rise to the degradation of device performances [7]. By the constant high voltage stress and high temperature, it is impossible to satisfy rising attention for the reliability assessment. In recent years, numerous studies have attempted to find and explore the appropriate acceleration method [8-9]. To enhance the reliability using a high voltage test without the deterioration of electric devices, we try to find out a new approach under a less elevated
1.2
Thershold voltage, Vth [V]
The gate oxide thickness decreases and the oncurrent increases according to each technology. Larger on-current will charge the capacitors faster, and as a result, the circuit speed increases. The generation rate of Stress Induced Leakage Current (SILC) and Charge to BreakDown (QBD) in ultra thin gate oxides is controlled by the gate voltage. It is well known that the high electric field FN stress on thin gate oxides can lead to increase in gate oxide leakage current as well as threshold voltage shift. Indeed, numerous operations under the stress condition, which increase interfacetrapped charges in the gate oxide, cause the gate oxide degradation, mainly due to the successive electric fields applied across the gate oxide, as shown in Figure 1 [10].
Threshold voltage, Vth [V]
2. Degradation in thin oxide gate
as shown in Figure 3. These results are explained by unnecessary charges in the gate oxide. Drain current, ID [A]
acceleration environment by changing a stress voltage type as a ramp stress.
1.0
0.8
0.6
0.4 0.8
1.0
1.2
1.4
1.6
1.8
Ratio of stress voltage
Figure 2. Degradation under the high voltage stress A typical burn-in temperature is raised to between 100°C and 140°C. Besides 125°C also 140°C is also a well-established burn-in temperature. The junction temperature is defined as the temperature of the silicon substrate. 6.0
200
5.8
180
5.6
160
5.4
140
5.2
120
100
5.0 5.0
5.2
5.4
5.6
5.8
6.0
100
120
140
160
180
200
Figure 3. Phenomena of the before and after a high voltage stress at 8.3MV/cm electric-filed in 80nm CMOS technology
Figure 1. Diagram of the interface-trapped charges of FN-tunnelling in DRAM
During the FN stress, a constant voltage stress (CVS) is applied to the gate with the source, drain, and substrate connected to ground. In high field between the gate and the well-body, FN-stress is occurred. On burn-in stress, many transistors are operating under the FN-stress condition. This is because word-lines are enabled, but bit-lines and cell nodes are in the ground level (Vss) as if we write “zero” on the cell. The degradation results of the drain current and the threshold voltage are shown in Figure 2. This kind of changes on the degradation has been observed in high density DRAM at Samsung with 80nm process of 1Gb DDR2. When the higher stress voltage is given, the threshold voltage and drain current are increased. In the case of 1.6 times stress voltage, the value of Vth is shifted from 0.6V to 0.9V. After providing a constant high voltage stress, the precharge power down currents which can indicate the amount of off-state leakage currents move toward highly, and the number of refresh time fail bits increase
The junction temperature increases with technology scaling due to increased transistor density, larger chip size, and increased leakage currents. Therefore, it is a key parameter of reliability and burn-in testing. The self-generated temperature in the burn-in environment contributes to the larger currents that can lead to further increase of the junction temperature, the possible thermal run away, and yield-loss of good parts. Indeed, the high density memory, such as 1Gb DDR2, has the characteristic of the various distributions and the increase of the operating-currents under the high temperature environment. Variation of self refresh current according to increase of the ambient temperature on a 1Gb DDR2 in 68nm CMOS technology at 1.8V VDD is shown in Figure 4. The same number of devices is measured on the different temperature environments. Figure 4 shows that the device current has a 3 times wide standard variation and higher mean current at the high temperature. It means that the junction current of the high temperature is higher than that of the low temperature condition. Moreover, major factor of the leakage, such as sub threshold leakage, increases exponentially according to the temperature. Therefore the burn-in temperature
Number of devices (EA)
Number of devices (EA)
must be reduced in step with the technology scaling. As technology shrinks, additional care must be taken to set stress voltages and temperatures properly to develop and evaluate tests in order to ensure that an acceptable acceleration factor is achieved.
Figure 4. Variation of self refresh current depends on the temperature
3. A new voltage stress method Practically, the acceleration of temperature and the stress time is very limited in the burn-in test. The most effective acceleration method is the variation of voltages. The CVS method is commonly used as the methodology for reliability screening. This method developed for ultra-thin SiO2 based dielectric gates. The voltage acceleration factors, the shape parameter of the Weibull distribution (ß) and the thermal activation energy (Ea) are required as a basic parameter for reliability prediction. Addition to both ßvalue and Ea, an effective reliability screening method needs to focus on the total stress time. Recently, a new breakdown time model was proposed. This model (Eq.1) includes the gate oxide thickness (Tox) and the gate voltage (VG) [11].
where γ is the acceleration factor, Ea is the activation energy, α is the oxide thickness acceleration factor, To is a constant for a given technology, and Tj is the average junction temperature. To determine the optimized stress time in burn-in test, it is need to look more closely at tradeoffs. It is a paradox that the high voltage stress is the most variable acceleration factor and yet has a relatively serious degradation of devices. In order to achieve a high reliability in spite of operating at the high voltage level, we can find a
solution in flash memory. The amount of interface trapped charges determines the threshold voltage and the off-state current. In the conventional flash devices, non-uniformities in the process or changes in the environment widely vary the required number of program pulses. The Incremental Step Pulse Programming (ISPP) has been provided fast programming performance under the process and the environmental variations while still keeping a tight programmed cell threshold voltage distribution. This method optimizes the interface trapped charges in the floating gate [12]. Hence, with the identical ISPP method concept, the VRS method which increases the gate voltage as a step pulse has the advantage to reduce the interface trapped charges in the gate oxide by the FN-tunneling in DRAM caused by the CVS. Although each method has a different voltage acceleration type, the CVS and the VRS have an equivalent result in terms of breakdown voltage distributions and TBD distributions. In the ability of the lifetime prediction, the VRS method shows a negligible variation in the measurement time.
Figure 5. Types of voltage stress (a) Constant voltage stress (b) Voltage ramp stress
Compared with the CVS, the VRS method has lower summation of voltage accelerate factor. However under the same stress time, VRS makes enhanced refresh characteristics and the improvement of the yield. A lower voltage than the user condition has not an acceleration effect. So the starting voltage is the user voltage as VA shown in Figure 5. The voltage of CVS (VB) generates about 8MV/cm electric field. In this evaluation, we will not take up the variation of the VRS in detail. The 0.1 voltage is determined as the variation of the VRS. In wafer level, burn-in stresses of the CVS and the VRS are directly applied to the test element group (TEG). Using the observation of the states of transistors and the split of burn-in condition, mass products are evaluated as in terms of the yield, the refresh time failure rate, and the reliability test in package level.
4. Experimental results To evaluate the effect of the voltage stress type, the drain saturation current is measured. The gate and drain voltage is forced at 6.7V for 100second in the CVS, and is from 5.8V to 6.7V by increasing 0.1V per 10second in the VRS. The peripheral thick transistor in TEG is used to evaluate the degradation of transistors in the CVS and the VRS conditions. The evaluation results are shown in Figure 6. As a result of measurement, the variations of Idsat are to be 13.4~15.0% at 6.7V of the CVS, and 2.9~3.0% of the VRS. The proposed VRS can reduce 72% the degradation of the saturation drain current in TEG level.
increase about 0.05% in VRS. This means that the ingredient of AC stress of the VRS more activates latent defects. Table 1. Yield comparison results
The variation of device parameters is also the index of the degeneration. At hot temperature package test, the criteria of degradation is refresh characteristic. According to the Table 2, refresh items, which detect the failure of transistors by disturbing and accelerating noise environments, are practically reduced. Even the leakage current of the flawless transistors is increased in the case of the high electric field on the thin gate oxide. This leakage current causes the failure of the refresh time. Figure 6. The saturation drain current variation versus stress time for peripheral thick transistor in TEG level
Each burn-in method is verified by mass chips. In terms of the yield, the refresh time fail rate, and reliability, we observed the difference between each method. Product reliability test (PRT) is processed by stressing + 0.5V, which is higher than the user voltage under 125℃ for 24 hours. If the failure rate of PRT and ILT meets the certain ppm, PRT can guarantee 6month operating life time and Infant lifetime test (ILT), stressing for 168 hours at 125℃ assures of 10 years operating life time at Samsung. For the verification and detail comparisons, the various burn-in methods are implemented using 1Gb DDR2 with 80nm CMOS technology. The sample number of each group is 4500. Table 1 shows detail comparison results between the previous CVS and the proposed VRS. Through the test yield and the failure rate of reliability, we can affirm that an adequate voltage stress such as the VRS type has an advantage. The yield of the VRS is 1.8% higher than that of the CVS and PRT and ILT rates are the same values. Although it does not mean that the quality of reliability in VRS is higher than CVS, we can assume the VRS is equivalent in the reliability with a less degradation. After burn-in test, the current failures relatively
Table 2. Failure rate comparison results
Therefore, as shown in experimental results, the proposed approach is an attractive and effective solution of the voltage stress test for thin gate oxide transistors.
5. Conclusion In this paper, a new voltage stress method for high density memory using the VRS is developed. Unlike previous approaches using the CVS, a reduction of degradation with the thin gate oxide transistors is achieved. By changing the voltage stress optimally, effectively enhanced test data with the minimum degradation during the VRS can be achieved. In addition, this method can increase the yield during the package test as well as the burn-in test operation. Therefore, this method can be applied for all thin gate
oxide transistors without a serous aggravation of devices. The future work is the development of the more efficient voltage stress test can be accomplished by dealing with various stress coverage.
[6] Rainer Duschl and Rolf-Peter Vollertsen, “Voltage acceleration of oxide breakdown in the sub-10 nm FowlerNordheim and direct tunneling regime”, Proceedings IEEE International Workshop on Integrated Reliability Workshop, Oct.2005, pp.17-20.
6. References
[7] Mesut Meterelliyoz, Hamid Mahmoodi, and Kaushik Roy, “A leakage control system for thermal stability during burn-in test”, Proceedings IEEE International Test Conference, Nov.2005, pp.10-16.
[1] Taeho Kim, Way Kuo and Wei-Ting Kary Chien, “Burnin effect on yield”, IEEE Transactions on Electronics Packaging Manufacturing,23(4), Oct. 2000, pp.293-299. [2] Way Kuo and Taeho Kim, “An overview of manufacturing yield and reliability modeling for semiconductor products”, Proceedings of the IEEE, 87(8), Aug. 1999, pp.1329-1344. [3] Jonathan T.-Y. Chang and Edward J. McCluskey, “SHOrt voltage elevation (SHOVE) test for weak CMOS ICs”, Proceedings 15th IEEE International Symposium on VLSI Test, Apr.1997, pp.446-451. [4] Chung-Yuan Tsao, R.Y. Shiue, C.C. Ting, Y.S. Huang, Y.C. Lin and J.T. Yue, “Applying dynamic voltage stressing to reduce early failure rate”, Proceedings 39th IEEE International Symposium on Reliability Physics, Apr.2001, pp.37-41. [5] Minh Quach, Tuan Pham, Tim Figal, Bob Kopitzke and Pete O'Neill, “Wafer-level defect-based testing using enhanced voltage stress and statistical test data evaluation”, Proceedings IEEE International Test Conference,Oct.2002, pp.683-692.
[8] F.Monsieur, E.Vincent, D.Roy, S.Bruyre, G. Pananakakis and G.Ghibaudo, “Time to breakdown and voltage to breakdown modeling for ultra thin oxides (Tox
