A Ring-Oscillator-Based Reliability Monitor for Isolated Measurement ...
1360
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 23, NO. 7, JULY 2015
A Ring-Oscillator-Based Reliability Monitor for Isolated Measurement of NBTI and PBTI in High-k/Metal Gate Technology Tony Tae-Hyoung Kim, Pong-Fei Lu, Keith A. Jenkins, and Chris H. Kim
Abstract— Ring-oscillator-based test structures that can separately measure the negative bias temperature instability (NBTI) and positive bias temperature instability (PBTI) degradation effects in digital circuits are presented for high-k metal gate devices. The mathematical derivation also shows that the structure for frequency degradation measurement can directly be used for estimating the portion of the NBTI and PBTI in the conventional ring oscillator. The proposed test structures including frequency degradation sensing circuitry have been implemented in an experimental high-k/metal gate SoI process.
Index Terms— Bias temperature instability, high-k/metal gate, on-chip measurement, reliability monitor, ring oscillator. I. I NTRODUCTION Circuit reliability has become an ever more challenging issue with an aggressive CMOS technology scaling roadmap. One of the most pressing of these challenges is bias temperature instability (BTI). In poly-gate devices, negative BTI (NBTI) in pMOSs has been considered as a dominant reliability concern [1]–[3]. High-k/metal gate technology has been introduced to mitigate leakage effects caused by tunneling when the oxide thickness scales below 2 nm. However, it introduces an additional reliability concern named positive BTI (PBTI) in nMOS devices. Similarly, PBTI also becomes a considerable reliability concern as high-k dielectric material and metal gate are adopted for gate leakage reduction in sub-40-nm CMOS technology nodes [4], [5]. For estimating the impact of BTI on circuit and eventually design aging-tolerant circuits, accurate circuit reliability measurement is imperative. Numerous previous reliability measurements employed individual device probing or simple ring oscillator frequency monitoring. However, device probing increases measurement time significantly, shows less accuracy and requires an extensive measurement setup [6], [7]. To tackle this issue, various research works presented on-chip circuit reliability monitors for accurate measurement and statistical analysis [7]–[10]. However, conventional ring oscillators will give a mixed result of NBTI and PBTI in the high-k dielectric and metal gate CMOS technologies. Since the magnitude of NBTI and PBTI is different after a given stress time, the impact of each NBTI and PBTI on circuit performance should be estimated independently for better understanding. Manuscript received December 20, 2013; revised April 23, 2014; accepted June 23, 2014. Date of publication August 6, 2014; date of current version June 23, 2015. T. T.-H. Kim was with the IBM T. J. Watson Research Center, Yorktown Heights, NY 10598 USA. He is now with the School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore 639798 (e-mail: [email protected]). P.-F. Lu and K. A. Jenkins are with the IBM T. J. Watson Research Center, Yorktown Heights, NY 10598 USA (e-mail: [email protected]; [email protected]). C. H. Kim is with the Department of Electrical and Computer Engineering, University of Minnesota, Minneapolis, MN 55455 USA (e-mail: [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TVLSI.2014.2339364
Ketchen et al. [11] proposed a ring oscillator-based test structure for measuring NBTI in inverter-driven pMOS pass-gates. However, it requires a negative voltage to stress the pass-gates under test, and controls the internal nodes through OFF-current. Kim et al. [12] presented ring oscillator circuit structures to separate out the NBTI/PBTI effects. Additional devices are added to cut the device under test from the rest of circuits and bias the rest circuits free of stress. However, the measured results did not address the equivalence between the proposed ring oscillator and the conventional structure. In this brief, we propose a reliability monitoring circuit, which facilitates the isolated NBTI and PBTI measurement. II. P ROPOSED I SOLATED NBTI AND PBTI M ONITORS A. Proposed NBTI and PBTI Monitors Fig. 1 shows the test structure we presented in [13] for separately measuring the NBTI and PBTI impact on the ring oscillator delay. The delay unit consists of two inverters with transmission gate load, forming two signal paths: 1) a measurement path for frequency degradation measurements; and 2) a control path for applying NBTI or PBTI stress to all the devices under test simultaneously [Fig. 1(a)]. During stress modes, a stress voltage (Vstr ) higher than the nominal supply voltage is applied to STR and the supply (VDD ) of the test structure. The transmission gate in the measurement path is cutoff while that in the control path is turned on. Two inverters between IN and OUT make them the same logic value. Therefore, no other device in the measurement path is stressed except for the devices under test. Devices in the control path are stressed but their impact on measurement path delay is negligible because they are disconnected during the measurement modes and the effect of the stress on the device node capacitance is insignificant. During measurement modes, nominal supply voltage is applied to VDD , and STR becomes 0 (i.e.,/STR = 1), enabling the measurement path. Since only one inverter is connected between IN and OUT, the proposed delay unit operates as an inverter. Fig. 1(b) and (c) shows ring oscillator structures under NBTI stress and PBTI stress, respectively. For NBTI stress, the primary input (IN) of the ring oscillator is connected to GND, which sets A = Vstr and B = 0. This stresses all pMOS transistors [P1 in Fig. 1(a)] in the inverter chain. Likewise, the input of the ring oscillator is connected to Vstr for PBTI stress, which sets A = 0 and B = Vstr . Fig. 1(d) explains the ring oscillator in the measurement modes. Since all the measurement paths are enabled, the circuit works as a ring oscillator. This test structure can be easily expanded to other types of complex logic gates (e.g., NAND, NOR) by replacing the inverter in each stage with those logic gates. B. Mathematical Derivation for Equivalence Checking The proposed ring oscillator has additional devices compared with the conventional ring oscillator at the output of each inverter, and this
1063-8210 © 2014 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 23, NO. 7, JULY 2015
Fig. 1.
1361
Proposed ring oscillator. (a) Delay unit with NBTI and PBTI stress control. (b) NBTI stress mode. (c) PBTI stress mode. (d) Measurement mode.
Equation (3) shows that the period degradation of the conventional ring oscillator is only a function of resistance. Fig. 2(b) illustrates the proposed delay chain and RC parameters in the measurement modes. The period of the proposed ring oscillator can be expressed as T p = α × n × {R p C2 +(R p + Rg )C3 + Rn C2 +(Rn + Rg )C3 } = α × n × {(R p + Rn )(C2 + C3 ) + 2Rg C3 } Fig. 2. (a) Conventional ring oscillator with RC parameters. (b) Proposed ring oscillator with RC parameters.
affects the delay of each delay unit. Therefore, the relation between the conventional ring oscillator and the proposed ring oscillator has to be clearly understood. Fig. 2(a) shows the schematic of the conventional delay chain and simplified RC parameters. The period of the ring oscillator (T1 ) can be expressed as T1 = α × n × C1 (Rn + R p )
(1)
where α is a constant, n is the number of delay units, C1 is the capacitance at each node including gate capacitance, junction capacitance and other parasitics, and Rn and R p are the ON -resistance of the nMOS and pMOS devices. In (1), NBTI and PBTI increase Rn and R p while the other parameters remain unchanged. The delay degradation due to NBTI and PBTI (T1 ) can be directly calculated from (1) T1 = TNBTI + TPBTI = α ×
n × C1 (Rn + R p ). 2
(2)
Here, TNBTI and TPBTI represent the delay degradation due to NBTI and PBTI, respectively. Rn and R p are the ON -resistance degradations in the corresponding nMOS and pMOS devices. Therefore, the period degradation (T1 /T1 ) is derived by dividing (2) by (1) 1 Rn + R p T1 = × . T1 2 Rn + R p
(3)
(4)
where C2 and C3 are the capacitance at the input and output of the inverters in the measurement path, and Rg is the ON -resistance of the pass-gate in the measurement path. The delay degradation due to each NBTI and PBTI can be calculated similarly by utilizing (2) T p_NBTI = α × n × R p (C2 + C3 ) T p_PBTI = α × n × Rn (C2 + C3 ) T p_NBTI α × n × R p (C2 + C3 ) = ∴ Tp Tp T p_PBTI α × n × Rn (C2 + C3 ) ∴ = . Tp Tp
(5)
Finally, the period degradation relationship between the proposed structure and the conventional ring oscillator is obtained from (3) and (5) 2C3 Rg T1 1 = 1+ T1 2 (Rn + R p )(C2 + C3 ) T P_NBTI T P_PBTI × + TP TP T P_PBTI T P_NBTI 1 . (6) + = (1 + β) 2 TP TP Equation (6) indicates that the proposed ring oscillator structures have a linear relationship with the conventional ring oscillator. Due to the unknown parameter [i.e., β in (6)], the measured results from the proposed structures cannot be directly employed as the absolute period degradation. Instead, this allows us to straightforwardly estimate the portion of the delay degradation caused by NBTI and PBTI after given stress.
1362
Fig. 3.
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 23, NO. 7, JULY 2015
Test chip architecture.
Fig. 4.
Input signal waveforms for frequency degradation measurements.
III. T EST C HIP I MPLEMENTATION The test chip architecture for the proposed NBTI and PBTI test structures is shown in Fig. 3. Ten ring oscillators are placed in a macroforming five unit test structures. Four unit test structures employ the proposed structures for isolated NBTI and PBTI measurement and one unit test structure utilizes the conventional ring oscillator for mixed NBTI and PBTI measurement. Each unit test structure has a pair of ring oscillators, one reference ring oscillator and one stressed ring oscillator [14]. The oscillators to be stressed are connected to the main power rail (SUPPLY) as usual while the reference ring oscillators are connected to the main power rail via pMOS header devices. The headers are only turned on during the measurement period to minimize the amount of aging in the reference ring oscillators. After a measurement sequence, we compare the digitized results from both stressed ring oscillators and reference ring oscillators to estimate aging effects. This differential measurement has been demonstrated to be very effective in an actual product environment [15] where ring oscillator frequencies vary due to nonideal operating environments, such as temperature, supply voltage, and so on. Each ring oscillator has a NAND in the feedback loop to control the oscillation. Oscillation is required for measurement and ac stress while it is blocked under dc stress. The proposed topologies have a stress signal to switch between the stress and measure modes. An enable signal (REF_ON) for the reference ring oscillators activates the pMOS headers to provide nominal supply voltage for the reference ring oscillators. When measurement is enabled (i.e., MEASURE = 1), the output of each oscillator is fed to its own counter and the counter measures the number of clock cycles for a given time window defined by the enable signal. Upon completion of a measurement cycle, the contents of each counter are simultaneously transferred into a single scan chain. The data stored in the scan chains can be read out serially using a clock (SCAN_CLK) after the measurement is complete. In this experimental macro, the ring oscillators, input/output circuits, and logic were on different power domains to apply higher stress voltage for accelerated test. In a real system, they would be in a common power domain because aging acceleration is not necessary. The BTI recovery can occur in the stressed ring oscillators when switching from stress modes to measurement modes. Therefore, the measurement times should be kept as short as possible. Fig. 4 illustrates a timing diagram of several critical signals. The measurement time is determined by the accuracy needed and the frequency of the ring oscillators. In this design, measurement time of 100 μs puts a
Fig. 5. Comparison of frequency degradation due to BTI from three different structures. The ring oscillators are under dc stress.
count of from about 10 000 to 30 000 in the counters, according to the frequencies of the implemented ring oscillators. This is sufficiently high enough to achieve the measurement accuracy of 0.1% since the ten-year degradation is expected to be a few percent in this experimental high-k/metal gate SoI process. An even shorter time could be achieved by designing a ring oscillator running at a higher frequency or employing another measurement technique such as the beat-frequency detection scheme presented in [8]. Note that the supply of the reference ring oscillator is enabled 3 μs before the beginning of a measurement cycle to allow stabilization of the ring oscillators. The scan out can occur any time after the measurement signal is OFF. An additional margin of 1 ms is placed for the supply voltage (SUPPLY) to change from the stress voltage level to the system voltage level. This is determined by the switching capability of the power supply used. IV. M EASUREMENT R ESULTS Fig. 5 compares the frequency degradations of three ring oscillators (i.e., the ring oscillator with isolated NBTI, the ring oscillator with isolated PBTI, and the conventional inverter). All ring oscillators are subjected to dc stress. In this experimental technology, the measured NBTI is greater than the measured PBTI. It is manifest that the degradation of the conventional inverter ring oscillator is greater than the isolated NBTI and PBTI oscillators due to the combined NBTI and PBTI. Fig. 6 shows the correlation of the proposed structures to the conventional ring oscillator. As the proposed NBTI and PBTI measurement structures are different from the conventional ring oscillator, it is necessary to know the relationship
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 23, NO. 7, JULY 2015
Fig. 6. Frequency degradation relationship between the proposed ring oscillator structures (Fig. 3) and the conventional ring oscillator in dc stress.
Fig. 7.
1363
Fig. 8. Estimated frequency degradation of the conventional ring oscillator after applying the contribution of each BTI (Fig. 7) to the frequency degradation of the conventional ring oscillator (Fig. 5).
Contribution of NBTI and PBTI to frequency degradation. Fig. 9. Comparison of frequency degradation due to BTI from three different structures. The ring oscillators are under ac stress.
between the proposed structures and the conventional ring oscillator. Summing the isolated NBTI and the isolated PBTI shows a linear relationship with the frequency degradation of the conventional ring oscillator. This validates the mathematical derivation in Section II-B. Therefore, the proposed structures accurately measure NBTI and PBTI separately in order to understand overall circuit performance degradation. However, as explained in Section II-B, the proposed structures provide the % contribution of NBTI and PBTI to the frequency degradation, not the absolute degradation amount. Therefore, we still need the frequency degradation measurement using the conventional ring oscillator that gives actual frequency degradation with mixed NBTI and PBTI (Fig. 5). The contributions of NBTI and PBTI on the frequency degradation over stress time are shown in Fig. 7. Note that the contributions of NBTI and PBTI are constant regardless of the amount of the total frequency degradation. This indicates that the rate of frequency degradation due to NBTI is the same as that due to PBTI. Finally, the frequency degradation of the conventional ring oscillator caused by each BTI mechanism needs to be estimated utilizing the above measured results. The estimated frequency degradation of the conventional ring oscillator with isolated NBTI and PBTI effects is presented in Fig. 8. The measured result from the conventional ring oscillator consists of two components, NBTI only and PBTI only. NBTI only corresponds to the conventional ring oscillator with isolated NBTI and PBTI only represents the conventional ring oscillator with isolated PBTI. Fig. 8 is derived from the frequency degradation of the conventional ring oscillator demonstrated in Fig. 5, and the contributions of NBTI and PBTI described in Fig. 7. Fig. 9 shows how the frequency degradation of the ring oscillators changes when the ring oscillators are stressed in ac modes. In this case, both nMOS and pMOS devices of the inverters in the
Fig. 10. Frequency degradation relationship between the proposed ring oscillator structures (Fig. 3) and the conventional ring oscillator in ac stress.
measurement path experience the BTI stress, and the two ring oscillators with isolated NBTI and PBTI become identical as shown in Fig. 9. They both degrade more slowly than the conventional inverter because the transmission gate between each stage adds a constant delay which lessens the effect of inverter degradation. Note that the frequency degradation of the conventional ring oscillator after ac stress (Fig. 9) is slightly smaller than that after dc stress shown in Fig. 5. In general, dc BTI degradation is worse than ac BTI degradation. However, in this brief, the BTI measurement circuit uses the measurement time of 100 μs, which recovers the BTI degradation partially. This recovery effect can be avoided if other fast measurement circuits are employed [8]–[10]. The relationship between the
1364
Fig. 11.
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 23, NO. 7, JULY 2015
Test chip microphotograph in high-k/metal gate SoI process.
conventional ring oscillator and the proposed structure under ac stress is shown in Fig. 10. Like Fig. 6, the proposed structure also shows a linear relationship with the conventional ring oscillator in ac stress, validating the claims in Section II-B. Fig. 11 shows the test chip microphotograph. V. C ONCLUSION We have presented a reliability monitor utilizing novel ring oscillator-based test structures for measuring the isolated NBTI and PBTI effects in the high-k/ metal gate CMOS technology. The mathematical equivalence derivation and the measured results verify that the proposed structures for frequency degradation measurement facilitate the independent estimation of NBTI and PBTI in logic circuits. The proposed reliability monitor can be employed not only for circuit reliability analysis, but also for an aging sensor whose digitized output data can be exploited to further control various circuit parameters for warning system failures or compensating the degradation. R EFERENCES [1] M. Denais et al., “Interface trap generation and hole trapping under NBTI and PBTI in advanced CMOS technology with a 2-nm gate oxide,” IEEE Trans. Device Mater. Rel., vol. 4, no. 4, pp. 715–722, Apr. 2004. [2] V. Huard, C. R. Parthasarathy, A. Bravaix, T. Hugel, C. Guerin, and E. Vincent, “Design-in-reliability approach for NBTI and hot-carrier degradations in advanced nodes,” IEEE Trans. Device Mater. Rel., vol. 7, no. 4, pp. 558–570, Apr. 2007.
[3] T. Grasser and B. Kaczer, “Evidence that two tightly coupled mechanisms are responsible for negative bias temperature instability in oxynitride MOSFETs,” IEEE Trans. Electron Devices, vol. 56, no. 5, pp. 1056–1062, May 2009. [4] S. Zafar et al., “A comparative study of NBTI and PBTI (charge trapping) in SiO2 /HfO2 stacks with FUSI, TiN, Re gates,” in IEEE Symp. VLSI Technol. Dig. Tech. Papers, Jun. 2006, pp. 23–25. [5] W.-C. Wu et al., “Positive bias temperature instability (PBTI) characteristics of contact-etch-stop-layer-induced local-tensile-strained HfO2 nMOSFET,” IEEE Electron Device Lett., vol. 29, no. 12, pp. 1340–1343, Dec. 2008. [6] G. Chen et al., “Dynamic NBTI of p-MOS transistors and its impact on device lifetime,” IEEE Electron Device Lett., vol. 23, no. 12, pp. 734–736, Dec. 2002. [7] M. Denais et al., “On-the-fly characterization of NBTI in ultra-thin gate oxide PMOSFET’s,” in Proc. IEEE Int. Electron Devices Meeting, Dec. 2004, pp. 109–112. [8] T.-H. Kim, R. Persaud, and C. H. Kim, “Silicon odometer: An onchip reliability monitor for measuring frequency degradation of digital circuits,” IEEE J. Solid-State Circuits, vol. 43, no. 4, pp. 874–880, Apr. 2008. [9] P. Singh, E. Karl, D. Blaauw, and D. Sylvester, “Compact degradation sensors for monitoring NBTI and oxide degradation,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 20, no. 9, pp. 1645–1655, Sep. 2012. [10] P. Singh, E. Karl, D. Blaauw, and D. Sylvester, “Dynamic NBTI management using a 45 nm multi-degradation sensor,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 58, no. 9, pp. 2026–2037, Sep. 2011. [11] M. B. Ketchen, M. Bhushan, and R. Bolam, “Ring oscillator based test structure for NBTI analysis,” in Proc. IEEE Int. Conf. Microelectron. Test Struct., Mar. 2007, pp. 42–47. [12] J.-J. Kim et al., “PBTI/NBTI monitoring ring oscillator circuits with on-chip Vt characterization and high frequency AC stress capability,” in Proc. Symp. VLSI Circuits, Jun. 2011, pp. 224–225. [13] T. T. Kim, P.-F. Lu, and C. Kim, “Design of ring oscillator structures for measuring isolated NBTI and PBTI,” in Proc. IEEE Int. Symp. Circuits Syst., May 2012, pp. 1580–1583. [14] K. A. Jenkins and P.-F. Lu, “On-chip circuit to monitor long-term NBTI and PBTI degradation,” Microelectron. Rel., vol. 53, nos. 9–11, pp. 1252–1256, Sep./Nov. 2013. [15] P.-F. Lu and K. A. Jenkins, “A built-in BTI monitor for long-term data collection in IBM microprocessors,” in Proc. IEEE Int. Rel. Phys. Symp., Apr. 2013, pp. 4A1.2–4A1.6.
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 23, NO. 7, JULY 2015
A Ring-Oscillator-Based Reliability Monitor for Isolated Measurement of NBTI and PBTI in High-k/Metal Gate Technology Tony Tae-Hyoung Kim, Pong-Fei Lu, Keith A. Jenkins, and Chris H. Kim
Abstract— Ring-oscillator-based test structures that can separately measure the negative bias temperature instability (NBTI) and positive bias temperature instability (PBTI) degradation effects in digital circuits are presented for high-k metal gate devices. The mathematical derivation also shows that the structure for frequency degradation measurement can directly be used for estimating the portion of the NBTI and PBTI in the conventional ring oscillator. The proposed test structures including frequency degradation sensing circuitry have been implemented in an experimental high-k/metal gate SoI process.
Index Terms— Bias temperature instability, high-k/metal gate, on-chip measurement, reliability monitor, ring oscillator. I. I NTRODUCTION Circuit reliability has become an ever more challenging issue with an aggressive CMOS technology scaling roadmap. One of the most pressing of these challenges is bias temperature instability (BTI). In poly-gate devices, negative BTI (NBTI) in pMOSs has been considered as a dominant reliability concern [1]–[3]. High-k/metal gate technology has been introduced to mitigate leakage effects caused by tunneling when the oxide thickness scales below 2 nm. However, it introduces an additional reliability concern named positive BTI (PBTI) in nMOS devices. Similarly, PBTI also becomes a considerable reliability concern as high-k dielectric material and metal gate are adopted for gate leakage reduction in sub-40-nm CMOS technology nodes [4], [5]. For estimating the impact of BTI on circuit and eventually design aging-tolerant circuits, accurate circuit reliability measurement is imperative. Numerous previous reliability measurements employed individual device probing or simple ring oscillator frequency monitoring. However, device probing increases measurement time significantly, shows less accuracy and requires an extensive measurement setup [6], [7]. To tackle this issue, various research works presented on-chip circuit reliability monitors for accurate measurement and statistical analysis [7]–[10]. However, conventional ring oscillators will give a mixed result of NBTI and PBTI in the high-k dielectric and metal gate CMOS technologies. Since the magnitude of NBTI and PBTI is different after a given stress time, the impact of each NBTI and PBTI on circuit performance should be estimated independently for better understanding. Manuscript received December 20, 2013; revised April 23, 2014; accepted June 23, 2014. Date of publication August 6, 2014; date of current version June 23, 2015. T. T.-H. Kim was with the IBM T. J. Watson Research Center, Yorktown Heights, NY 10598 USA. He is now with the School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore 639798 (e-mail: [email protected]). P.-F. Lu and K. A. Jenkins are with the IBM T. J. Watson Research Center, Yorktown Heights, NY 10598 USA (e-mail: [email protected]; [email protected]). C. H. Kim is with the Department of Electrical and Computer Engineering, University of Minnesota, Minneapolis, MN 55455 USA (e-mail: [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TVLSI.2014.2339364
Ketchen et al. [11] proposed a ring oscillator-based test structure for measuring NBTI in inverter-driven pMOS pass-gates. However, it requires a negative voltage to stress the pass-gates under test, and controls the internal nodes through OFF-current. Kim et al. [12] presented ring oscillator circuit structures to separate out the NBTI/PBTI effects. Additional devices are added to cut the device under test from the rest of circuits and bias the rest circuits free of stress. However, the measured results did not address the equivalence between the proposed ring oscillator and the conventional structure. In this brief, we propose a reliability monitoring circuit, which facilitates the isolated NBTI and PBTI measurement. II. P ROPOSED I SOLATED NBTI AND PBTI M ONITORS A. Proposed NBTI and PBTI Monitors Fig. 1 shows the test structure we presented in [13] for separately measuring the NBTI and PBTI impact on the ring oscillator delay. The delay unit consists of two inverters with transmission gate load, forming two signal paths: 1) a measurement path for frequency degradation measurements; and 2) a control path for applying NBTI or PBTI stress to all the devices under test simultaneously [Fig. 1(a)]. During stress modes, a stress voltage (Vstr ) higher than the nominal supply voltage is applied to STR and the supply (VDD ) of the test structure. The transmission gate in the measurement path is cutoff while that in the control path is turned on. Two inverters between IN and OUT make them the same logic value. Therefore, no other device in the measurement path is stressed except for the devices under test. Devices in the control path are stressed but their impact on measurement path delay is negligible because they are disconnected during the measurement modes and the effect of the stress on the device node capacitance is insignificant. During measurement modes, nominal supply voltage is applied to VDD , and STR becomes 0 (i.e.,/STR = 1), enabling the measurement path. Since only one inverter is connected between IN and OUT, the proposed delay unit operates as an inverter. Fig. 1(b) and (c) shows ring oscillator structures under NBTI stress and PBTI stress, respectively. For NBTI stress, the primary input (IN) of the ring oscillator is connected to GND, which sets A = Vstr and B = 0. This stresses all pMOS transistors [P1 in Fig. 1(a)] in the inverter chain. Likewise, the input of the ring oscillator is connected to Vstr for PBTI stress, which sets A = 0 and B = Vstr . Fig. 1(d) explains the ring oscillator in the measurement modes. Since all the measurement paths are enabled, the circuit works as a ring oscillator. This test structure can be easily expanded to other types of complex logic gates (e.g., NAND, NOR) by replacing the inverter in each stage with those logic gates. B. Mathematical Derivation for Equivalence Checking The proposed ring oscillator has additional devices compared with the conventional ring oscillator at the output of each inverter, and this
1063-8210 © 2014 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 23, NO. 7, JULY 2015
Fig. 1.
1361
Proposed ring oscillator. (a) Delay unit with NBTI and PBTI stress control. (b) NBTI stress mode. (c) PBTI stress mode. (d) Measurement mode.
Equation (3) shows that the period degradation of the conventional ring oscillator is only a function of resistance. Fig. 2(b) illustrates the proposed delay chain and RC parameters in the measurement modes. The period of the proposed ring oscillator can be expressed as T p = α × n × {R p C2 +(R p + Rg )C3 + Rn C2 +(Rn + Rg )C3 } = α × n × {(R p + Rn )(C2 + C3 ) + 2Rg C3 } Fig. 2. (a) Conventional ring oscillator with RC parameters. (b) Proposed ring oscillator with RC parameters.
affects the delay of each delay unit. Therefore, the relation between the conventional ring oscillator and the proposed ring oscillator has to be clearly understood. Fig. 2(a) shows the schematic of the conventional delay chain and simplified RC parameters. The period of the ring oscillator (T1 ) can be expressed as T1 = α × n × C1 (Rn + R p )
(1)
where α is a constant, n is the number of delay units, C1 is the capacitance at each node including gate capacitance, junction capacitance and other parasitics, and Rn and R p are the ON -resistance of the nMOS and pMOS devices. In (1), NBTI and PBTI increase Rn and R p while the other parameters remain unchanged. The delay degradation due to NBTI and PBTI (T1 ) can be directly calculated from (1) T1 = TNBTI + TPBTI = α ×
n × C1 (Rn + R p ). 2
(2)
Here, TNBTI and TPBTI represent the delay degradation due to NBTI and PBTI, respectively. Rn and R p are the ON -resistance degradations in the corresponding nMOS and pMOS devices. Therefore, the period degradation (T1 /T1 ) is derived by dividing (2) by (1) 1 Rn + R p T1 = × . T1 2 Rn + R p
(3)
(4)
where C2 and C3 are the capacitance at the input and output of the inverters in the measurement path, and Rg is the ON -resistance of the pass-gate in the measurement path. The delay degradation due to each NBTI and PBTI can be calculated similarly by utilizing (2) T p_NBTI = α × n × R p (C2 + C3 ) T p_PBTI = α × n × Rn (C2 + C3 ) T p_NBTI α × n × R p (C2 + C3 ) = ∴ Tp Tp T p_PBTI α × n × Rn (C2 + C3 ) ∴ = . Tp Tp
(5)
Finally, the period degradation relationship between the proposed structure and the conventional ring oscillator is obtained from (3) and (5) 2C3 Rg T1 1 = 1+ T1 2 (Rn + R p )(C2 + C3 ) T P_NBTI T P_PBTI × + TP TP T P_PBTI T P_NBTI 1 . (6) + = (1 + β) 2 TP TP Equation (6) indicates that the proposed ring oscillator structures have a linear relationship with the conventional ring oscillator. Due to the unknown parameter [i.e., β in (6)], the measured results from the proposed structures cannot be directly employed as the absolute period degradation. Instead, this allows us to straightforwardly estimate the portion of the delay degradation caused by NBTI and PBTI after given stress.
1362
Fig. 3.
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 23, NO. 7, JULY 2015
Test chip architecture.
Fig. 4.
Input signal waveforms for frequency degradation measurements.
III. T EST C HIP I MPLEMENTATION The test chip architecture for the proposed NBTI and PBTI test structures is shown in Fig. 3. Ten ring oscillators are placed in a macroforming five unit test structures. Four unit test structures employ the proposed structures for isolated NBTI and PBTI measurement and one unit test structure utilizes the conventional ring oscillator for mixed NBTI and PBTI measurement. Each unit test structure has a pair of ring oscillators, one reference ring oscillator and one stressed ring oscillator [14]. The oscillators to be stressed are connected to the main power rail (SUPPLY) as usual while the reference ring oscillators are connected to the main power rail via pMOS header devices. The headers are only turned on during the measurement period to minimize the amount of aging in the reference ring oscillators. After a measurement sequence, we compare the digitized results from both stressed ring oscillators and reference ring oscillators to estimate aging effects. This differential measurement has been demonstrated to be very effective in an actual product environment [15] where ring oscillator frequencies vary due to nonideal operating environments, such as temperature, supply voltage, and so on. Each ring oscillator has a NAND in the feedback loop to control the oscillation. Oscillation is required for measurement and ac stress while it is blocked under dc stress. The proposed topologies have a stress signal to switch between the stress and measure modes. An enable signal (REF_ON) for the reference ring oscillators activates the pMOS headers to provide nominal supply voltage for the reference ring oscillators. When measurement is enabled (i.e., MEASURE = 1), the output of each oscillator is fed to its own counter and the counter measures the number of clock cycles for a given time window defined by the enable signal. Upon completion of a measurement cycle, the contents of each counter are simultaneously transferred into a single scan chain. The data stored in the scan chains can be read out serially using a clock (SCAN_CLK) after the measurement is complete. In this experimental macro, the ring oscillators, input/output circuits, and logic were on different power domains to apply higher stress voltage for accelerated test. In a real system, they would be in a common power domain because aging acceleration is not necessary. The BTI recovery can occur in the stressed ring oscillators when switching from stress modes to measurement modes. Therefore, the measurement times should be kept as short as possible. Fig. 4 illustrates a timing diagram of several critical signals. The measurement time is determined by the accuracy needed and the frequency of the ring oscillators. In this design, measurement time of 100 μs puts a
Fig. 5. Comparison of frequency degradation due to BTI from three different structures. The ring oscillators are under dc stress.
count of from about 10 000 to 30 000 in the counters, according to the frequencies of the implemented ring oscillators. This is sufficiently high enough to achieve the measurement accuracy of 0.1% since the ten-year degradation is expected to be a few percent in this experimental high-k/metal gate SoI process. An even shorter time could be achieved by designing a ring oscillator running at a higher frequency or employing another measurement technique such as the beat-frequency detection scheme presented in [8]. Note that the supply of the reference ring oscillator is enabled 3 μs before the beginning of a measurement cycle to allow stabilization of the ring oscillators. The scan out can occur any time after the measurement signal is OFF. An additional margin of 1 ms is placed for the supply voltage (SUPPLY) to change from the stress voltage level to the system voltage level. This is determined by the switching capability of the power supply used. IV. M EASUREMENT R ESULTS Fig. 5 compares the frequency degradations of three ring oscillators (i.e., the ring oscillator with isolated NBTI, the ring oscillator with isolated PBTI, and the conventional inverter). All ring oscillators are subjected to dc stress. In this experimental technology, the measured NBTI is greater than the measured PBTI. It is manifest that the degradation of the conventional inverter ring oscillator is greater than the isolated NBTI and PBTI oscillators due to the combined NBTI and PBTI. Fig. 6 shows the correlation of the proposed structures to the conventional ring oscillator. As the proposed NBTI and PBTI measurement structures are different from the conventional ring oscillator, it is necessary to know the relationship
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 23, NO. 7, JULY 2015
Fig. 6. Frequency degradation relationship between the proposed ring oscillator structures (Fig. 3) and the conventional ring oscillator in dc stress.
Fig. 7.
1363
Fig. 8. Estimated frequency degradation of the conventional ring oscillator after applying the contribution of each BTI (Fig. 7) to the frequency degradation of the conventional ring oscillator (Fig. 5).
Contribution of NBTI and PBTI to frequency degradation. Fig. 9. Comparison of frequency degradation due to BTI from three different structures. The ring oscillators are under ac stress.
between the proposed structures and the conventional ring oscillator. Summing the isolated NBTI and the isolated PBTI shows a linear relationship with the frequency degradation of the conventional ring oscillator. This validates the mathematical derivation in Section II-B. Therefore, the proposed structures accurately measure NBTI and PBTI separately in order to understand overall circuit performance degradation. However, as explained in Section II-B, the proposed structures provide the % contribution of NBTI and PBTI to the frequency degradation, not the absolute degradation amount. Therefore, we still need the frequency degradation measurement using the conventional ring oscillator that gives actual frequency degradation with mixed NBTI and PBTI (Fig. 5). The contributions of NBTI and PBTI on the frequency degradation over stress time are shown in Fig. 7. Note that the contributions of NBTI and PBTI are constant regardless of the amount of the total frequency degradation. This indicates that the rate of frequency degradation due to NBTI is the same as that due to PBTI. Finally, the frequency degradation of the conventional ring oscillator caused by each BTI mechanism needs to be estimated utilizing the above measured results. The estimated frequency degradation of the conventional ring oscillator with isolated NBTI and PBTI effects is presented in Fig. 8. The measured result from the conventional ring oscillator consists of two components, NBTI only and PBTI only. NBTI only corresponds to the conventional ring oscillator with isolated NBTI and PBTI only represents the conventional ring oscillator with isolated PBTI. Fig. 8 is derived from the frequency degradation of the conventional ring oscillator demonstrated in Fig. 5, and the contributions of NBTI and PBTI described in Fig. 7. Fig. 9 shows how the frequency degradation of the ring oscillators changes when the ring oscillators are stressed in ac modes. In this case, both nMOS and pMOS devices of the inverters in the
Fig. 10. Frequency degradation relationship between the proposed ring oscillator structures (Fig. 3) and the conventional ring oscillator in ac stress.
measurement path experience the BTI stress, and the two ring oscillators with isolated NBTI and PBTI become identical as shown in Fig. 9. They both degrade more slowly than the conventional inverter because the transmission gate between each stage adds a constant delay which lessens the effect of inverter degradation. Note that the frequency degradation of the conventional ring oscillator after ac stress (Fig. 9) is slightly smaller than that after dc stress shown in Fig. 5. In general, dc BTI degradation is worse than ac BTI degradation. However, in this brief, the BTI measurement circuit uses the measurement time of 100 μs, which recovers the BTI degradation partially. This recovery effect can be avoided if other fast measurement circuits are employed [8]–[10]. The relationship between the
1364
Fig. 11.
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 23, NO. 7, JULY 2015
Test chip microphotograph in high-k/metal gate SoI process.
conventional ring oscillator and the proposed structure under ac stress is shown in Fig. 10. Like Fig. 6, the proposed structure also shows a linear relationship with the conventional ring oscillator in ac stress, validating the claims in Section II-B. Fig. 11 shows the test chip microphotograph. V. C ONCLUSION We have presented a reliability monitor utilizing novel ring oscillator-based test structures for measuring the isolated NBTI and PBTI effects in the high-k/ metal gate CMOS technology. The mathematical equivalence derivation and the measured results verify that the proposed structures for frequency degradation measurement facilitate the independent estimation of NBTI and PBTI in logic circuits. The proposed reliability monitor can be employed not only for circuit reliability analysis, but also for an aging sensor whose digitized output data can be exploited to further control various circuit parameters for warning system failures or compensating the degradation. R EFERENCES [1] M. Denais et al., “Interface trap generation and hole trapping under NBTI and PBTI in advanced CMOS technology with a 2-nm gate oxide,” IEEE Trans. Device Mater. Rel., vol. 4, no. 4, pp. 715–722, Apr. 2004. [2] V. Huard, C. R. Parthasarathy, A. Bravaix, T. Hugel, C. Guerin, and E. Vincent, “Design-in-reliability approach for NBTI and hot-carrier degradations in advanced nodes,” IEEE Trans. Device Mater. Rel., vol. 7, no. 4, pp. 558–570, Apr. 2007.
[3] T. Grasser and B. Kaczer, “Evidence that two tightly coupled mechanisms are responsible for negative bias temperature instability in oxynitride MOSFETs,” IEEE Trans. Electron Devices, vol. 56, no. 5, pp. 1056–1062, May 2009. [4] S. Zafar et al., “A comparative study of NBTI and PBTI (charge trapping) in SiO2 /HfO2 stacks with FUSI, TiN, Re gates,” in IEEE Symp. VLSI Technol. Dig. Tech. Papers, Jun. 2006, pp. 23–25. [5] W.-C. Wu et al., “Positive bias temperature instability (PBTI) characteristics of contact-etch-stop-layer-induced local-tensile-strained HfO2 nMOSFET,” IEEE Electron Device Lett., vol. 29, no. 12, pp. 1340–1343, Dec. 2008. [6] G. Chen et al., “Dynamic NBTI of p-MOS transistors and its impact on device lifetime,” IEEE Electron Device Lett., vol. 23, no. 12, pp. 734–736, Dec. 2002. [7] M. Denais et al., “On-the-fly characterization of NBTI in ultra-thin gate oxide PMOSFET’s,” in Proc. IEEE Int. Electron Devices Meeting, Dec. 2004, pp. 109–112. [8] T.-H. Kim, R. Persaud, and C. H. Kim, “Silicon odometer: An onchip reliability monitor for measuring frequency degradation of digital circuits,” IEEE J. Solid-State Circuits, vol. 43, no. 4, pp. 874–880, Apr. 2008. [9] P. Singh, E. Karl, D. Blaauw, and D. Sylvester, “Compact degradation sensors for monitoring NBTI and oxide degradation,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 20, no. 9, pp. 1645–1655, Sep. 2012. [10] P. Singh, E. Karl, D. Blaauw, and D. Sylvester, “Dynamic NBTI management using a 45 nm multi-degradation sensor,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 58, no. 9, pp. 2026–2037, Sep. 2011. [11] M. B. Ketchen, M. Bhushan, and R. Bolam, “Ring oscillator based test structure for NBTI analysis,” in Proc. IEEE Int. Conf. Microelectron. Test Struct., Mar. 2007, pp. 42–47. [12] J.-J. Kim et al., “PBTI/NBTI monitoring ring oscillator circuits with on-chip Vt characterization and high frequency AC stress capability,” in Proc. Symp. VLSI Circuits, Jun. 2011, pp. 224–225. [13] T. T. Kim, P.-F. Lu, and C. Kim, “Design of ring oscillator structures for measuring isolated NBTI and PBTI,” in Proc. IEEE Int. Symp. Circuits Syst., May 2012, pp. 1580–1583. [14] K. A. Jenkins and P.-F. Lu, “On-chip circuit to monitor long-term NBTI and PBTI degradation,” Microelectron. Rel., vol. 53, nos. 9–11, pp. 1252–1256, Sep./Nov. 2013. [15] P.-F. Lu and K. A. Jenkins, “A built-in BTI monitor for long-term data collection in IBM microprocessors,” in Proc. IEEE Int. Rel. Phys. Symp., Apr. 2013, pp. 4A1.2–4A1.6.
