A Robust Nonlinear Control Scheme for a Sag Compensator Active ...
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A Robust Nonlinear Control Scheme for a Sag Compensator Active Multilevel Rectifier Without Sag Detection Algorithm Jesus Lira, Nancy Visairo, Ciro Nunez, Member, IEEE, Adrian Ramirez, Student Member, IEEE, and Hebertt Sira-Ram´ırez
Abstract—In this paper, a robust nonlinear control scheme is proposed for the single-phase active multilevel rectifier (SPAMR) subject to voltage input sags. The scheme is based on the input– output model of the rectifier system combined with exact linearization achieved via generalized proportional-integral (GPI) control. The GPI controller provides enhanced robustness for the SPAMR against unexpected voltage sags and load changes. The main contribution of this paper resides on avoiding the need for voltage sags detection algorithms while improving the dynamic response of the SPAMR. Simulation and experimental results obtained on a 1-kVA SPAMR laboratory prototype are presented. Index Terms—Active multilevel rectifier, generalized proportional-integral (GPI) controllers, robust nonlinear control, sag compensation.
I. INTRODUCTION OLTAGE sags constitute one of the most harmful events that can occur in electrical networks [1]. Power rectifiers, commonly used inside a motor drive, are one of the most common industrial loads that are particularly sensitive to voltage sags with considerable economic impacts. This issue has been widely recognized in several journal articles and specialized books [2], [3]. Sag detection algorithms have been developed to provide voltage sag robustness in several power electronics topologies. There exist several sag detection algorithms such as wavelet-based, dq transformation-based, Kalman filters, and trigonometry algorithms [4]–[6]. Once a voltage sag is detected, it is necessary to properly compensate it. There exist many research proposals to solve this important power quality problem. In general, from a power electronics standpoint, there are three main approaches addressing this issue.
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Manuscript received July 22, 2011; revised September 21, 2011 and November 10, 2011; accepted January 5, 2012. Date of current version April 20, 2012. This work was supported in part by the Mexican Council for Science and Technology via Project SEP-84616 and the Universidad Aut´onoma de San Luis Potos´ı—Fondo de Apoyo a la Investigaci´on via Project C10-FAI-05-39.66. Recommended for publication by Associate Editor D. Xu. J. Lira, N. Visairo, and C. Nunez are with the Facultad de Ingenier´ıa, Universidad Aut´onoma de San Luis Potos´ı, 78290 San Luis Potos´ı, M´exico (e-mail: [email protected]; [email protected]; [email protected]). A. Ramirez is with the Departamento of Control Autom´atico, Centro de Investigaci´on de Estudios Avanzados, Instituto Polit´ecnico Nacional, 07300 M´exico City, Mexico (e-mail: [email protected]). H. Sira-Ram´ırez is with the Departamento of Ingenier´ıa El´ectrica, Secci´on of Mecatr´onica, Centro de Investigaci´on de Estudios Avanzados, Instituto Polit´ecnico Nacional, 07300 M´exico City, M´exico (e-mail: [email protected]). Digital Object Identifier 10.1109/TPEL.2012.2185516
1) To carry out the compensation at the ac side. This implies the use of dynamic voltage restorers (DVRs) [7]–[11] that compensate the sag by means of a series voltage injection to the ac mains, thus delivering a regulated sinusoidal waveform to the load. However, the compensation scheme can represent an important active power consumption; this fact is highly dependent on the compensation reference obtained by means of some additional algorithm [12]. 2) To carry out the compensation at the dc side. In this case, there are several topologies whose purpose is to provide a compensation for the step down caused by the sag [13]. Similarly to the DVR case, it is necessary to calculate the missing voltage to be able to ride through the sag. The idea is to maintain a dc constant voltage at the load. 3) To carry out the compensation at the power rectifier. In this case, power switches are used instead of noncontrolled diodes [14]–[18]. In all the precedent references to append the voltage sag ride-through capability, a specific algorithm is required to calculate the missing voltage. Heretofore, all the options for compensating voltage sags, presented in the literature, require a sag detection algorithm which involves a digital, or analogical, signal processing effort causing a significant time delay to ride through the sag event. In this paper, the authors undertook an effort to achieve the sag compensation in an SPAMR without the use of detection algorithms but based only on a suitable control scheme robust with respect to disturbances. This paper is organized as follows. In Section II, the mathematical model of the SPAMR is described and some assumptions are established to obtain the model in the dq synchronous reference frame. In Section III, a robust nonlinear feedback control scheme is proposed which is based on an input–output linearized mode. A generalized proportional-integral (GPI) controller is proposed to guarantee asymptotic stability and to add the required robustness on the entire system. Section IV presents simulation and experimental results considering a 1-kVA SPAMR prototype. A discussion of these results is also provided. Section V contains some conclusions of this contribution. II. CIRCUIT DESCRIPTION AND MATHEMATICAL MODEL The SPAMR is depicted in Fig. 1; the circuit consists on a noncontrolled rectifier bridge and two bidirectional switches. A boost inductor LS is placed between ac mains and the rectifier bridge to minimize the current ripple. The system is also provided with two equal capacitors, C1 = C2 = C.
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LIRA et al.: ROBUST NONLINEAR CONTROL SCHEME FOR A SAG COMPENSATOR ACTIVE MULTILEVEL RECTIFIER
model is given by ⎡ d ⎤ Ls is −Rs ⎢ dt ⎥ ⎦= ⎣ d 2u C vdc dt Fig. 1.
−u −1/R
is vdc
1
+
0
vs .
(5)
B. Single-Phase DQ Transformation
SPAMR.
This topology improves the power factor (PF) and decreases the total harmonic distortion (THD) at the currents. This is achieved by proper operation of the switches, resulting in a three-level pulse width modulation (PWM) voltage between ab terminals when the switches operate synchronously. On the other hand, if the switches operate independently, a five-level PWM pattern is generated between the ab terminals. In order to better understand the properties of the system, the mathematical model is presented in the form of differential equations describing the rectifier dynamics [19] (see Fig. 1) Ls
d is = vs − vab dt
d vC 1 = i1 − ir 1 dt d C2 vC 2 = i2 − ir 2 dt
In a dq synchronous reference frame, all the calculations for control and compensation purposes become simpler. From this standpoint, the dq transformation constitutes a rather useful setup. So, an imaginary orthogonal circuit is generated; this virtual circuit comprises the same components as the real circuit. However, the state variables, in steady state, lag 90◦ with respect to their counterparts in the real circuit. This way, a synchronous reference frame is obtained. Thus, applying the transformation matrix
sin (ωt) − cos (ωt) N= (6) cos (ωt) sin (ωt) the dq representation is obtained. From the rectifier, imaginary and real signals are given by
re im T re im T , vs = v s v s is = is is
C1
re u = us
(1)
where 1 [sgn (is ) + 1] [vC 1 (1 − T1 ) + vC 2 (1 − T2 )] 2 1 + [sgn (is ) − 1] [vC 1 (1 − T2 ) + vC 2 (1 − T1 )] (2) 2 1 1 i1 = [sgn (is ) + 1] (1 − T1 ) is + [sgn (is ) − 1] (1 − T2 ) is 2 2 (3) vab =
i2 =
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1 1 [sgn (is )+1] (1 − T2 ) is + [sgn (is )−1] (1 − T1 ) is . 2 2 (4)
sgn (is ) = 1 if is ≥ 0 and sgn(is ) = −1 if is < 0. T1 is the gate signal for power switch 1 and T2 is the gate signal for power switch 2.
uim s
T .
Using vectors is , vs , and u in (5), the average model of the real and imaginary circuits are obtained. The dq transformation is performed by applying the matrix N; thus, the model of the SPAMR in the dq synchronous reference frame is given by d dq dq dq dq i = ΩLs idq s + vs − Rs is − u vdc dt s T d C vdc = − (1/R) vdc + udq idq s dt
Ls
where Ω=
0 −ω
ω d , idq s = [ is 0
iqs ]T , vsdq = [ vsd
(7)
vsq ]T
and udq = [ ud
uq ]T
III. CONTROL DESIGN A. Average Model In this paper, a three-level PWM technique is considered, i.e., T2 = T1 = T which is defined in the discrete set {0, 1}. The switching function is given by s = (1 − T )sgn(is ), defined in the discrete set {−1, 0, 1}. So, considering that the PWM frequency is high enough with respect to line frequency, an averaged model is valid. Then, the average switching function is given by u which is defined in the continuous set [−1, 1]. Besides, it is considered that the load resistors are equal, i.e., R2 = R1 = R. Thus, a new state variable vdc given by the sum of vC 1 and vC 2 can be defined, and incorporating the effect of a resistance RS in series with the inductor LS , the rectifier average
This section is devoted to introduce the main results of this paper. It considers the need for a disturbance rejection strategy on, both, ac mains voltage and dc dynamic load connected to the SPAMR. The control objectives are: 1) to stabilize the dc voltage at a nominal value rejecting all disturbances that can be produced via the dynamic loads or voltage sags; and 2) to deliver a sinusoidal current with self-adjusting capabilities, depending on the load dynamics. The virtue of the proposed control scheme consists on the suitable combination of the input–output linearization via feedback and generalized PI controllers [20]. The operation of the SPAMR can be decoupled in two control loops: an inner current
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Ls
Fig. 2.
Ls
Block diagram of the proposed control scheme.
loop, whose task is to deliver a sinusoidal current with fast dynamics, and an outer voltage loop, whose purpose is to regulate the dc voltage with slower dynamics. In order to simplify the notation, a change of variables is carried out. The system is rewritten as follows: d x1 = ωLs x2 − Rs x1 + vsd − x3 u1 dt d Ls x2 = −ωLs x1 − Rs x2 + vsq − x3 u2 dt 1 d C x3 = − x3 + x1 u1 + x2 u2 dt R
d ξ1 = ωLs ξ2 − Rs ξ1 + vsd dt 1/2 Ls 2 ξ1 + ξ22 − 2η − u1 C d ξ2 = −ωLs ξ1 − Rs ξ2 + vsq dt 1/2 Ls 2 ξ1 + ξ22 − 2η − u2 C
C
Ls
(8)
where x = [ ids iqs vdc ]T , u = [ ud uq ]T , and y = [ x1 x2 ]T . Fig. 2 shows the block diagram of the proposed control scheme, where x∗ is the reference signal vector, and v 1 and v 2 are auxiliary control variables.
and with the natural condition that R and C are always positive; η = 0 is a globally, exponentially asymptotically stable equilibrium point for the zero dynamics. This means that (8) has a minimum phase zero dynamics. As a consequence, it is possible to design controllers for x1 and x2 . The state feedback current controller after reverting the change of coordinates ϕ−1 (ξ, η) expressed as x1 = ξ1
Considering the output vector y and the input vector u, the relative degree vector [21] is given by [ ρ1 ρ2 ] = [ 1 1 ] and so, the diffeomorphism ⎤ ⎤ ⎡ x1 φ1 (x) ξ1 ⎥ ⎢ ⎥ ⎢ ⎥ ⎢ x2 ϕ (x) = ⎣ φ2 (x) ⎦ = ⎣ ξ2 ⎦ = ⎢ ⎥ ⎣ 2 2 2 ⎦ Ls x1 + x2 + Cx3 η φ3 (x) 2C (9) defines the input–output linearization of the multiple-input multiple-output (MIMO) system (8) and φ3 (x) satisfies the condition LG (x) φ3 (x) = 0 where G(x) is the matrix related with u given by
x2 = ξ2 1/2 Ls 2 2 ξ1 + ξ2 x3 = 2η − C
⎤ ⎡
⎡
x3 − L s ⎢ ⎢ ⎢ G (x) = ⎢ 0 ⎣ x1 C
0 x3 − Ls x2 C
⎤ ⎥ ⎥ ⎥. ⎥ ⎦
(10)
The aforementioned condition guarantees that the input vector u will not appear in the dynamics of η which implies that it becomes unobservable from y, and therefore, there exists an internal dynamics governed by η. Thus, system (8) in its norm form, considering the transformation (9), is given by
(11)
Now, to assure that the internal dynamics is well behaved, the zero dynamics should be evaluated. Setting ξ1 = ξ2 = 0 and substituting them into (11), the zero dynamics results in 2 d η=− η (12) dt RC
A. Current Loop
⎡
d η = ξ1 ωLs ξ2 − Rs ξ1 + vsd dt + ξ2 (−ωLs ξ1 − Rs ξ2 + vsq ) Ls 2 1 ξ1 + ξ22 . − 2η − R C
is given by u1 u2
=
1 x3
ωLs x2 − Rs x1 + vsd − v1 −ωLs x1 − Rs x2 + vsq − v2
(13) .
(14)
This reduces the input–output map to a linear map from the input to the output d y=v dt
(15)
where v = [ v1 v2 ]T is the auxiliary control input to be designed. Consider now the unknown but bounded and sufficiently smooth perturbation input signals p1 (t) and p2 (t) acting in the ac mains voltage and load current, respectively. The perturbed system is, then, considered to be given by d x1 = ωLs x2 − Rs x1 + vsd + pd1 − x3 u1 dt d Ls x2 = −ωLs x1 − Rs x2 + vsq + pq1 − x3 u2 dt 1 d C x3 = − x3 − p2 (t) + x1 u1 + x2 u2 dt R Ls
(16)
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where the dq components pd1 and pq1 of p1 (t)were obtained following the procedure described in Section II-B. Thus, applying (14), the perturbed input–output system becomes d y = v + pdq dt
(17)
where pdq = [ pd1 pq1 ]T . Assuming that pdq is well approximated by a second-degree polynomial, a third-order GPI controller vector is proposed as ∗ v = kC 3 (y −y) + kC 2 (y∗ − y) dt + kC 1
(y∗ − y) dt2 + kc0
2
x1 (s) kC 3 s + kC 2 s + kC 1 s + kC 0 = 4 x∗1 (s) s + kC 3 s3 + kC 2 s2 + kC 1 s + kC 0 kC 3 s3 + kC 2 s2 + kC 1 s + kC 0 x2 (s) = . x∗2 (s) s4 + kC 3 s3 + kC 2 s2 + kC 1 s + kC 0
(19)
On the other hand, the reference signal x∗1 can be calculated offline from the steady-state solution of (8). Thus, considering a unity PF (x2 = 0), the steady-state equations of (8) are vsd = Rs x∗1 + x∗3 U1 0 = ωLs x∗1 + x∗3 U2 i∗L = x∗1 U1
GPI controller of the dc bus output voltage loop. TABLE I NOMINAL PARAMETERS OF THE SPAMR
(y∗ − y) dt3 (18)
where the reference signal is y∗ = [ x∗1 x∗2 ]T . Equation (18) adds robustness with respect to unknown perturbations of the form p1 (t) suddenly appearing. It is important to note that p1 (t) represents a voltage sag in this particular case. Now, observe that (17) and (18) represent a linear controller. This is an additional advantage of the proposed feedback control scheme. So, performing the Laplace transform to (17) in closed loop with (18) and taking pdq as perturbation vector, the transfer functions from references to outputs are given by 3
Fig. 3.
(20)
where U1 and U2 are the nominal values of u1 and u2 , respectively, x∗3 is the desired dc bus voltage and i∗L = x∗3 /R is the nominal load current. Solving (20) for x∗1 and taking the solution that consumes less energy, the reference signal is given by ⎡ ⎤ 2 2 d ∗ d vs 1 v 4 (x3 ) ⎦ x∗1 = ⎣ s − . (21) − 2 Rs Rs RRs B. Voltage Loop Since reference signal x∗1 is calculated offline using the nominal parameters of the system and the load resistance, the current control becomes very sensitive to model uncertainties and load changes. In this paper, instead of estimating or measuring the load current, the available dc voltage is used to cope with this problem. This fact represents another contribution of this study. So, consider the perturbed dc voltage equation from (16) 1 d (22) C x3 = − x3 − p2 (t) + x1 u1 + x2 u2 . dt R
The dynamics of the current loop is designed to be much faster than the dynamics of the dc voltage loop; it is considered that u1 is always at its nominal value U1 . Thus, neglecting RS from (20), U1 ≈ vsd /x∗3 and considering a unity PF, the dc bus output voltage can be rewritten as d vs d ∗ C x3 = x1 + γ (t) (23) dt x∗3 where γ (t) = − (1/R) x3 − p2 (t) is a function that describes the unknown load current demand, considered like a perturbation depending of time t. Once again, assuming that γ (t) is well approximated by a second-degree polynomial, a third-order GPI controller is proposed x∗1 = kv 3 (x∗3 − x3 ) + kv 2 (x∗3 − x3 ) dt + kv 1
(x∗3
− x3 ) dt + kv 0 2
(x∗3 − x3 ) dt3 (24)
allowing the regulation of the dc bus output voltage under an unknown load. The block diagram of (23) with the GPI controller is shown in Fig. 3 and the closed-loop transfer function taking γ (t) as a perturbation is given by kv 3 s3 + kv 2 s2 + kv 1 s + kv 0 vsd x3 (s) = . (25) x∗3 (s) Cx∗3 s4 + (kv 3 s3 + kv 2 s2 + kv 1 s + kv 0 ) vsd IV. SIMULATION AND EXPERIMENTAL RESULTS A 1-kVA SPAMR prototype was built and tested; likewise, simulations were performed using the mathematical model with the proposed control scheme in order to evaluate the theoretical analysis. Table I shows the parameters of the prototype that were used to carry out simulations.
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Fig. 4.
Simulations in steady state. From top to bottom: dc bus voltage v d c , ac mains current is , and ac mains voltage v s .
Fig. 5.
Simulation results with voltage sag to 72% at t = 0.45 s. From top to bottom: regulated dc bus voltage vd c , ac mains current is , and ac mains voltage v s .
A. Simulation Results Two types of tests were proposed to validate the nonlinear control scheme ability to achieve the control objectives. The first one is concerned with the quality of the steady-state behavior and the second one is the ability to compensate voltage sags without using detection algorithms. The performance of the scheme on the entire operation range was also tested. For this purpose, an ac mains voltage sag was induced at the same time of several load changes. Fig. 4 shows the simulation results in steady state. A good response can be observed according to the numerical results presented in that figure, which are vs = 124 Vrm s , is = 9.36 Arm s , THDv = 0%, THDi = 6%, PF = 0.99, S = 1160 VA, P = 1160 W, Q = 0 VAR. The behavior of ac current and dc voltage is not optimal but satisfies the electrical customer operation conditions acceptably. A second test was provided to demonstrate the capability of the SPAMR to ride through a voltage sag. So, Fig. 5 shows a voltage sag to 72% of the nominal voltage magnitude occurring at t = 0.45 s. An excellent behavior of the closed-loop SPAMR is depicted with a steady-state dc voltage ripple of less than 10%
peak to peak. Note that at the start and at the end of the sag, the dc voltage variation has a maximum of 10%. The last test consisted in simultaneously applying a dynamic load in combination with several voltage sags, starting at time t = 1.5 s. With this test, the robust performance of the GPIcontrolled SPAMR in delivering an excellent response with enhanced robustness was demonstrated. Most importantly, the requirement of any sag detection algorithm is bypassed. This is demonstrated in Fig. 6 where the obtained simulation results are depicted. B. Experimental Results In order to ascertain the validity of the proposed control scheme, a 1-kVA prototype was built and tested. The controller was programmed in a DSP board TMS320F28335. The prototype parameters and controller gains are the same used in simulations and they are shown in Table I. The switching frequency was of 6 kHz and to obtain the switch pulses, a sinusoidal PWM strategy was used. Fig. 7 shows a picture of the implemented prototype used for experimental validation of the theoretical analysis.
LIRA et al.: ROBUST NONLINEAR CONTROL SCHEME FOR A SAG COMPENSATOR ACTIVE MULTILEVEL RECTIFIER
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Fig. 6. Simulation results with dynamical load and multiple sags applied simultaneously. From top to bottom: dc bus voltage vd c , ac mains current is , ac mains voltage v s , and load current Ir 1 .
Fig. 7.
1-kVA SPAMR prototype.
Fig. 8 shows the steady-state behavior with the following measured results vs = 123.31 Vrm s , is = 9.23 Arm s , THDv = 3.96%, THDi = 5.98%, PF = 0.98, S = 1138 VA, P = 1121 W, Q = 200.7 VAR. As it can be seen, the performance is quite similar to those obtained in the simulations. This demonstrates the feasibility of the proposed feedback control scheme. The original design of the SPAMR inductor was made considering a switching frequency of 20 kHz. However, simulations and experimental tests were carried out using 6 kHz in order to probe the robustness provided to the system by the controller. Thereby, the current ripple is more significant and as a consequence, the THD is higher. Therefore, this behavior is related with the topology but not with the controller performance. A test with a sag to 72% was implemented to demonstrate the performance of the closed-loop system under such a change of operation conditions. Fig. 9 shows the results; it is important to recognize that, comparing with Fig. 5, the results are similar. We emphasize the capability of the closed–loop-controlled SPAMR to compensate the sag event without using a sag detection algorithm.
Fig. 8. Experimental results in steady state. From top to bottom: dc bus voltage v d c , ac mains current is , and ac mains voltage v s .
Fig. 9. Experimental results with voltage sag to 72%. From top to bottom: dc bus voltage v d c , ac mains voltage v s , and ac mains current is .
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ACKNOWLEDGMENT The authors would like to thank the participation of Bachelor Student Y. Guill´en during the elaboration of this paper. REFERENCES
Fig. 10. Experimental results with dynamical load and multiple sags. From top to bottom: dc bus voltage v d c , ac mains current is , ac mains voltage v s , and load current Ir 1 .
Finally, a test was conducted on the SPAMR prototype which simultaneously used a significant load variation along with several induced voltage sags. Fig. 10 shows the experimental results, where it can be observed that the dc voltage is efficiently regulated. Moreover, the ripple was always kept below a 10% amplitude deviation.
V. CONCLUSION A nonlinear control scheme for an SPAMR has been proposed. The main motivations for this proposal were to provide to the SPAMR with the capability to work well in the operation range while exhibiting a good dynamic behavior. At the same time, this approach enjoys added robustness properties with respect to ac mains voltage perturbations and dynamical load changes while eliminating the need for a sag detection algorithm. This is, particularly, relevant from a power electronics viewpoint. It is important to mention that the controller parameters, both, in the simulations and in the experimental tests, were kept to be the same. A systematic procedure was developed to study the feasibility of this proposal. This consisted on obtaining a model in the dq synchronous reference frame of the system, achieving the exact linearization via feedback, and designing GPI controllers. Simulation and experimental results allow us to assert that it is possible to compensate voltage sags in active rectifiers without the use of detection algorithms. In the author’s opinion, this allows for a more reliable system given that sensors for sag detection were shown to be unnecessary. Moreover, it was experimentally demonstrated that the SPAMR maintains both good dynamical quality and excellent steady-state behavior. This points to the benefits that a good, robust, compensation scheme makes unnecessary the use of sag detection algorithms without compromising the basic performance features expected from an SPAMR.
[1] H. G. Sarmiento and E. Estrada, “A voltage sag study in an industry with adjustable speed-drives,” IEEE Ind. Appl. Mag., vol. 2, no. 1, pp. 16–19, Jan./Feb. 1996. [2] M. H. Bollen Understanding Power Quality Problems, Voltage Sags and Interruptions (Series Power Engineering), Piscataway, NJ: IEEE Press, 2000, ch. 1. [3] J. Wang, S. Chen, and T. T. Lie, “Estimating economic impact of voltage sags,” in Proc. Int. Conf. Power Syst. Technol., 2004, pp. 350–355. [4] N. N. Jangle, A. M. Jain, and B. E. Kushare, “An algorithm to detect point on wave initiation of voltage sag wavelet using discrete wavelet transform,” in Proc. Int. Power Energy Eng. Conf., 2010, pp. 921–926. [5] Z. Yan, X. Yonghai, X. Xiangning, Z. Yongqiang, and G. Chunlin, “Power quality disturbances identification based on dq conversion, wavelet transform and FFT,” in Proc. Power Energy Eng. Conf., 2010, pp. 1–4. [6] M. Gonz´alez, V. C´ardenas, and R. Alvarez, “A fast detection algorithm for sags, swells, and interruptions based on digital RMS calculation and Kalman filtering,” in Proc. IEEE Int. Conf. Power Electron., 2006, pp. 1–6. [7] C. Ngai Ho and H. S.-H. Chung, “Implementation and performance evaluation of a fast dynamic control scheme for capacitor-supported interline DVR,” IEEE Trans. Power Electron., vol. 25, no. 8, pp. 1975–1988, Aug. 2010. [8] S. Subramanian and M. Kumar, “Interphase AC–AC topology for voltage sag supporter,” IEEE Trans. Power Electron., vol. 25, no. 2, pp. 514–518, Feb. 2010. [9] A. Teke, K. Bayindir, and M. Tumay, “Fast sag/swell detection method for fuzzy logic controlled dynamic voltage restorer,” IET Generat. Transmiss. Distrib., vol. 4, no. 1, pp. 1–12, Jan. 2010. [10] Y. H. Chung, H. J. Kim, G. H. Kwon, T. B. Park, S. H. Kim, K. S. Kim, and J. I. Moon, “Medium voltage dynamic voltage restorer with neural network controlled voltage disturbance detector,” in Proc. Int. Conf. Power Syst. Technol., 2006, pp. 1–7. [11] C. Meyer, R. W. De Doncker, Y. W. Li, and F. Blaabjerg, “Optimized control strategy for a medium-voltage DVR—Theoretical investigations and experimental results,” IEEE Trans. Power Electron., vol. 23, no. 6, pp. 2746–2754, Nov. 2008. [12] J. G. Nielsen, F. Blaabjerg, and N. Mohan, “Control strategies for dynamic voltage restorer compensating voltage sags with phase jump,” in Proc. Appl. Power Electron. Conf. Expo., 2001, vol. 2, pp. 1267–1273. [13] J. L. Duran-Gomez, P. N. Enjeti, and B. O. Woo, “Effect of voltage sags on adjustable-speed drives: A critical evaluation and an approach to improve performance,” IEEE Trans. Ind. Appl., vol. 35, no. 6, pp. 1440–1449, Nov. 1999. ´ [14] J. Lira, C. Nunez, M. Flota, R. Alvarez, and F. J. Perez-Pinal, “Five-level, single-phase active rectifier with extended functions,” Int. Rev. Electr. Eng., vol. 2, pp. 180–187, Mar. 2007. [15] Y. S. Kim and S. K. Sul, “A novel ride-through system for adjustablespeed drives using common-mode voltage,” IEEE Trans. Ind. Appl., vol. 37, no. 5, pp. 1373–1382, Aug. 2002. [16] T. Lu, Z. Zhao, Y. Zhang, and L. Yuan, “A novel direct power control strategy with wide input voltage range for three-level PWM rectifier,” in Proc. Power Electron. Motion Control Conf., 2009, pp. 897–902. [17] Y. Tang, P. Chiang, P. Wang, and F. H. Choo, “One-cycle-controlled threephase PWM rectifiers with improved regulation under unbalanced and distorted input-voltage conditions,” IEEE Trans. Power Electron., vol. 25, no. 11, pp. 2786–2796, Nov. 2010. [18] M. Lobo, S. A. Mussa, and I. Barbi, “Three-phase multilevel PWM rectifiers based on conventional bidirectional converters,” IEEE Trans. Power Electron., vol. 25, no. 3, pp. 545–549, Mar. 2010. [19] B. R. Lin and H. H. Lu, “A new control scheme for single-phase PWM multilevel rectifier with power factor correction,” IEEE Trans. Ind. Electron., vol. 46, no. 4, pp. 820–829, Aug. 2002. [20] A. R. Ram´ırez-L´opez, N. Visairo-Cruz, C. A. Nunez-Guti´errez, J. J. LiraP´erez, and H. Sira-Ram´ırez, “Input–output linearization and generalized pi control of a single-phase active multilevel rectifier,” in Proc. 7th Int. Conf. Elect. Eng., Comput. Sci. Autom. Control, 2010, pp. 22–27. [21] A. Isidori, Nonlinear Control Systems, 3rd ed. New York: Springer, 1994, ch. 5.
LIRA et al.: ROBUST NONLINEAR CONTROL SCHEME FOR A SAG COMPENSATOR ACTIVE MULTILEVEL RECTIFIER
Jesus Lira was born in San Luis Potos´ı, M´exico, on June 1957. He received the B.S. degree in ingenier´ıa electr´onica y comunicaciones from the Instituto Tecnol´ogico y de Estudios Superiores de Monterrey, Monterrey, M´exico, in 1978, and the M.S. and Ph.D. degrees in ingenier´ıa el´ectrica from the Universidad Aut´onoma de San Luis Potos´ı, San Luis Potos´ı, M´exico, in 2004 and 2009, respectively. Since 1987, he has been a Researcher at the Universidad Aut´onoma de San Luis Potos´ı. His research interests include power factor correction, control of power converters, power electronics, and power quality. Dr. Lira is a member of the IEEE Power Electronics Society and a member of the Sociedad Mexicana de Electr´onica de Potencia.
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Adrian Ramirez (S’12) was born in San Luis Potos´ı, M´exico, on August 1984. He received the B.S. degree in ingenier´ıa mecatr´onica from the Instituto Tecnol´ogico de San Luis Potos´ı, San Luis Potos´ı, and the M.S. degree in ingenier´ıa el´ectrica from the Universidad Aut´onoma de San Luis Potos´ı, San Luis Potos´ı, in 2008 and 2010, respectively. He is currently working toward the Ph.D. degree at the Centro de Investigaci´on y Estudios Avanzados, Instituto Polit´ecnico Nacional, M´exico City, M´exico. His research interests include power quality, power converters, and control of time delay systems.
Nancy Visairo was born in Oaxaca, M´exico. She received the M.S. and Ph.D. degrees in ingenier´ıa electr´onica from the Centro Nacional de Investigaci´on y Desarrollo Tecnol´ogico, Cuernavaca, M´exico, in 1999 and 2004, respectively. Since 2005, she has been a Researcher at the Universidad Aut´onoma de San Luis Potos´ı, San Luis Potos´ı, M´exico. Her main research interests include automatic control and fault diagnosis of dynamical systems. Dr. Visairo is a member of the IEEE Power Electronics Society.
Ciro Nunez (M’95) was born in Tampico, M´exico, on December 1970. He received the M.S. and Ph.D. degrees in ingenier´ıa electr´onica from the Centro Nacional de Investigaci´on y Desarrollo Tecnol´ogico, Cuernavaca, M´exico, in 1997 and 2002, respectively. Since 2002, he has been a Researcher at the Universidad Aut´onoma de San Luis Potos´ı, San Luis Potos´ı, M´exico. His main research interests include power electronics, power quality, smart grids, and control converters. Dr. Nunez is a member of the IEEE Power Electronics Society and a member of the Sociedad Mexicana de Electr´onica de Potencia.
Hebertt Sira-Ram´ırez was born in San Cristobal, Venezuela, on December 1948. He received the Graduate degree in ingeniero electricista from the Universidad de Los Andes, M´erida, Venezuela, in 1970, the M.S.E.E. and E.E. degrees in 1974 and the Ph.D. degree in electrical engineering in 1977 from the Massachusetts Institute of Technology, Cambridge. Since 1998, he has been an Emeritus Professor from the Universidad de Los Andes. Since 1998, he has been a Titular Researcher at the Centro de Investigaci´on y Estudios Avanzados, Instituto Polit´ecnico Nacional, Mexico City, Mexico. He has coauthored five books, 27 book chapters, 145 journal articles, and has participated in 260 international conferences in the field of automatic control. His main research interests include nonlinear systems theory and its applications in power electronics, variable structure systems, and systems identification.
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 27, NO. 8, AUGUST 2012
A Robust Nonlinear Control Scheme for a Sag Compensator Active Multilevel Rectifier Without Sag Detection Algorithm Jesus Lira, Nancy Visairo, Ciro Nunez, Member, IEEE, Adrian Ramirez, Student Member, IEEE, and Hebertt Sira-Ram´ırez
Abstract—In this paper, a robust nonlinear control scheme is proposed for the single-phase active multilevel rectifier (SPAMR) subject to voltage input sags. The scheme is based on the input– output model of the rectifier system combined with exact linearization achieved via generalized proportional-integral (GPI) control. The GPI controller provides enhanced robustness for the SPAMR against unexpected voltage sags and load changes. The main contribution of this paper resides on avoiding the need for voltage sags detection algorithms while improving the dynamic response of the SPAMR. Simulation and experimental results obtained on a 1-kVA SPAMR laboratory prototype are presented. Index Terms—Active multilevel rectifier, generalized proportional-integral (GPI) controllers, robust nonlinear control, sag compensation.
I. INTRODUCTION OLTAGE sags constitute one of the most harmful events that can occur in electrical networks [1]. Power rectifiers, commonly used inside a motor drive, are one of the most common industrial loads that are particularly sensitive to voltage sags with considerable economic impacts. This issue has been widely recognized in several journal articles and specialized books [2], [3]. Sag detection algorithms have been developed to provide voltage sag robustness in several power electronics topologies. There exist several sag detection algorithms such as wavelet-based, dq transformation-based, Kalman filters, and trigonometry algorithms [4]–[6]. Once a voltage sag is detected, it is necessary to properly compensate it. There exist many research proposals to solve this important power quality problem. In general, from a power electronics standpoint, there are three main approaches addressing this issue.
V
Manuscript received July 22, 2011; revised September 21, 2011 and November 10, 2011; accepted January 5, 2012. Date of current version April 20, 2012. This work was supported in part by the Mexican Council for Science and Technology via Project SEP-84616 and the Universidad Aut´onoma de San Luis Potos´ı—Fondo de Apoyo a la Investigaci´on via Project C10-FAI-05-39.66. Recommended for publication by Associate Editor D. Xu. J. Lira, N. Visairo, and C. Nunez are with the Facultad de Ingenier´ıa, Universidad Aut´onoma de San Luis Potos´ı, 78290 San Luis Potos´ı, M´exico (e-mail: [email protected]; [email protected]; [email protected]). A. Ramirez is with the Departamento of Control Autom´atico, Centro de Investigaci´on de Estudios Avanzados, Instituto Polit´ecnico Nacional, 07300 M´exico City, Mexico (e-mail: [email protected]). H. Sira-Ram´ırez is with the Departamento of Ingenier´ıa El´ectrica, Secci´on of Mecatr´onica, Centro de Investigaci´on de Estudios Avanzados, Instituto Polit´ecnico Nacional, 07300 M´exico City, M´exico (e-mail: [email protected]). Digital Object Identifier 10.1109/TPEL.2012.2185516
1) To carry out the compensation at the ac side. This implies the use of dynamic voltage restorers (DVRs) [7]–[11] that compensate the sag by means of a series voltage injection to the ac mains, thus delivering a regulated sinusoidal waveform to the load. However, the compensation scheme can represent an important active power consumption; this fact is highly dependent on the compensation reference obtained by means of some additional algorithm [12]. 2) To carry out the compensation at the dc side. In this case, there are several topologies whose purpose is to provide a compensation for the step down caused by the sag [13]. Similarly to the DVR case, it is necessary to calculate the missing voltage to be able to ride through the sag. The idea is to maintain a dc constant voltage at the load. 3) To carry out the compensation at the power rectifier. In this case, power switches are used instead of noncontrolled diodes [14]–[18]. In all the precedent references to append the voltage sag ride-through capability, a specific algorithm is required to calculate the missing voltage. Heretofore, all the options for compensating voltage sags, presented in the literature, require a sag detection algorithm which involves a digital, or analogical, signal processing effort causing a significant time delay to ride through the sag event. In this paper, the authors undertook an effort to achieve the sag compensation in an SPAMR without the use of detection algorithms but based only on a suitable control scheme robust with respect to disturbances. This paper is organized as follows. In Section II, the mathematical model of the SPAMR is described and some assumptions are established to obtain the model in the dq synchronous reference frame. In Section III, a robust nonlinear feedback control scheme is proposed which is based on an input–output linearized mode. A generalized proportional-integral (GPI) controller is proposed to guarantee asymptotic stability and to add the required robustness on the entire system. Section IV presents simulation and experimental results considering a 1-kVA SPAMR prototype. A discussion of these results is also provided. Section V contains some conclusions of this contribution. II. CIRCUIT DESCRIPTION AND MATHEMATICAL MODEL The SPAMR is depicted in Fig. 1; the circuit consists on a noncontrolled rectifier bridge and two bidirectional switches. A boost inductor LS is placed between ac mains and the rectifier bridge to minimize the current ripple. The system is also provided with two equal capacitors, C1 = C2 = C.
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LIRA et al.: ROBUST NONLINEAR CONTROL SCHEME FOR A SAG COMPENSATOR ACTIVE MULTILEVEL RECTIFIER
model is given by ⎡ d ⎤ Ls is −Rs ⎢ dt ⎥ ⎦= ⎣ d 2u C vdc dt Fig. 1.
−u −1/R
is vdc
1
+
0
vs .
(5)
B. Single-Phase DQ Transformation
SPAMR.
This topology improves the power factor (PF) and decreases the total harmonic distortion (THD) at the currents. This is achieved by proper operation of the switches, resulting in a three-level pulse width modulation (PWM) voltage between ab terminals when the switches operate synchronously. On the other hand, if the switches operate independently, a five-level PWM pattern is generated between the ab terminals. In order to better understand the properties of the system, the mathematical model is presented in the form of differential equations describing the rectifier dynamics [19] (see Fig. 1) Ls
d is = vs − vab dt
d vC 1 = i1 − ir 1 dt d C2 vC 2 = i2 − ir 2 dt
In a dq synchronous reference frame, all the calculations for control and compensation purposes become simpler. From this standpoint, the dq transformation constitutes a rather useful setup. So, an imaginary orthogonal circuit is generated; this virtual circuit comprises the same components as the real circuit. However, the state variables, in steady state, lag 90◦ with respect to their counterparts in the real circuit. This way, a synchronous reference frame is obtained. Thus, applying the transformation matrix
sin (ωt) − cos (ωt) N= (6) cos (ωt) sin (ωt) the dq representation is obtained. From the rectifier, imaginary and real signals are given by
re im T re im T , vs = v s v s is = is is
C1
re u = us
(1)
where 1 [sgn (is ) + 1] [vC 1 (1 − T1 ) + vC 2 (1 − T2 )] 2 1 + [sgn (is ) − 1] [vC 1 (1 − T2 ) + vC 2 (1 − T1 )] (2) 2 1 1 i1 = [sgn (is ) + 1] (1 − T1 ) is + [sgn (is ) − 1] (1 − T2 ) is 2 2 (3) vab =
i2 =
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1 1 [sgn (is )+1] (1 − T2 ) is + [sgn (is )−1] (1 − T1 ) is . 2 2 (4)
sgn (is ) = 1 if is ≥ 0 and sgn(is ) = −1 if is < 0. T1 is the gate signal for power switch 1 and T2 is the gate signal for power switch 2.
uim s
T .
Using vectors is , vs , and u in (5), the average model of the real and imaginary circuits are obtained. The dq transformation is performed by applying the matrix N; thus, the model of the SPAMR in the dq synchronous reference frame is given by d dq dq dq dq i = ΩLs idq s + vs − Rs is − u vdc dt s T d C vdc = − (1/R) vdc + udq idq s dt
Ls
where Ω=
0 −ω
ω d , idq s = [ is 0
iqs ]T , vsdq = [ vsd
(7)
vsq ]T
and udq = [ ud
uq ]T
III. CONTROL DESIGN A. Average Model In this paper, a three-level PWM technique is considered, i.e., T2 = T1 = T which is defined in the discrete set {0, 1}. The switching function is given by s = (1 − T )sgn(is ), defined in the discrete set {−1, 0, 1}. So, considering that the PWM frequency is high enough with respect to line frequency, an averaged model is valid. Then, the average switching function is given by u which is defined in the continuous set [−1, 1]. Besides, it is considered that the load resistors are equal, i.e., R2 = R1 = R. Thus, a new state variable vdc given by the sum of vC 1 and vC 2 can be defined, and incorporating the effect of a resistance RS in series with the inductor LS , the rectifier average
This section is devoted to introduce the main results of this paper. It considers the need for a disturbance rejection strategy on, both, ac mains voltage and dc dynamic load connected to the SPAMR. The control objectives are: 1) to stabilize the dc voltage at a nominal value rejecting all disturbances that can be produced via the dynamic loads or voltage sags; and 2) to deliver a sinusoidal current with self-adjusting capabilities, depending on the load dynamics. The virtue of the proposed control scheme consists on the suitable combination of the input–output linearization via feedback and generalized PI controllers [20]. The operation of the SPAMR can be decoupled in two control loops: an inner current
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Ls
Fig. 2.
Ls
Block diagram of the proposed control scheme.
loop, whose task is to deliver a sinusoidal current with fast dynamics, and an outer voltage loop, whose purpose is to regulate the dc voltage with slower dynamics. In order to simplify the notation, a change of variables is carried out. The system is rewritten as follows: d x1 = ωLs x2 − Rs x1 + vsd − x3 u1 dt d Ls x2 = −ωLs x1 − Rs x2 + vsq − x3 u2 dt 1 d C x3 = − x3 + x1 u1 + x2 u2 dt R
d ξ1 = ωLs ξ2 − Rs ξ1 + vsd dt 1/2 Ls 2 ξ1 + ξ22 − 2η − u1 C d ξ2 = −ωLs ξ1 − Rs ξ2 + vsq dt 1/2 Ls 2 ξ1 + ξ22 − 2η − u2 C
C
Ls
(8)
where x = [ ids iqs vdc ]T , u = [ ud uq ]T , and y = [ x1 x2 ]T . Fig. 2 shows the block diagram of the proposed control scheme, where x∗ is the reference signal vector, and v 1 and v 2 are auxiliary control variables.
and with the natural condition that R and C are always positive; η = 0 is a globally, exponentially asymptotically stable equilibrium point for the zero dynamics. This means that (8) has a minimum phase zero dynamics. As a consequence, it is possible to design controllers for x1 and x2 . The state feedback current controller after reverting the change of coordinates ϕ−1 (ξ, η) expressed as x1 = ξ1
Considering the output vector y and the input vector u, the relative degree vector [21] is given by [ ρ1 ρ2 ] = [ 1 1 ] and so, the diffeomorphism ⎤ ⎤ ⎡ x1 φ1 (x) ξ1 ⎥ ⎢ ⎥ ⎢ ⎥ ⎢ x2 ϕ (x) = ⎣ φ2 (x) ⎦ = ⎣ ξ2 ⎦ = ⎢ ⎥ ⎣ 2 2 2 ⎦ Ls x1 + x2 + Cx3 η φ3 (x) 2C (9) defines the input–output linearization of the multiple-input multiple-output (MIMO) system (8) and φ3 (x) satisfies the condition LG (x) φ3 (x) = 0 where G(x) is the matrix related with u given by
x2 = ξ2 1/2 Ls 2 2 ξ1 + ξ2 x3 = 2η − C
⎤ ⎡
⎡
x3 − L s ⎢ ⎢ ⎢ G (x) = ⎢ 0 ⎣ x1 C
0 x3 − Ls x2 C
⎤ ⎥ ⎥ ⎥. ⎥ ⎦
(10)
The aforementioned condition guarantees that the input vector u will not appear in the dynamics of η which implies that it becomes unobservable from y, and therefore, there exists an internal dynamics governed by η. Thus, system (8) in its norm form, considering the transformation (9), is given by
(11)
Now, to assure that the internal dynamics is well behaved, the zero dynamics should be evaluated. Setting ξ1 = ξ2 = 0 and substituting them into (11), the zero dynamics results in 2 d η=− η (12) dt RC
A. Current Loop
⎡
d η = ξ1 ωLs ξ2 − Rs ξ1 + vsd dt + ξ2 (−ωLs ξ1 − Rs ξ2 + vsq ) Ls 2 1 ξ1 + ξ22 . − 2η − R C
is given by u1 u2
=
1 x3
ωLs x2 − Rs x1 + vsd − v1 −ωLs x1 − Rs x2 + vsq − v2
(13) .
(14)
This reduces the input–output map to a linear map from the input to the output d y=v dt
(15)
where v = [ v1 v2 ]T is the auxiliary control input to be designed. Consider now the unknown but bounded and sufficiently smooth perturbation input signals p1 (t) and p2 (t) acting in the ac mains voltage and load current, respectively. The perturbed system is, then, considered to be given by d x1 = ωLs x2 − Rs x1 + vsd + pd1 − x3 u1 dt d Ls x2 = −ωLs x1 − Rs x2 + vsq + pq1 − x3 u2 dt 1 d C x3 = − x3 − p2 (t) + x1 u1 + x2 u2 dt R Ls
(16)
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where the dq components pd1 and pq1 of p1 (t)were obtained following the procedure described in Section II-B. Thus, applying (14), the perturbed input–output system becomes d y = v + pdq dt
(17)
where pdq = [ pd1 pq1 ]T . Assuming that pdq is well approximated by a second-degree polynomial, a third-order GPI controller vector is proposed as ∗ v = kC 3 (y −y) + kC 2 (y∗ − y) dt + kC 1
(y∗ − y) dt2 + kc0
2
x1 (s) kC 3 s + kC 2 s + kC 1 s + kC 0 = 4 x∗1 (s) s + kC 3 s3 + kC 2 s2 + kC 1 s + kC 0 kC 3 s3 + kC 2 s2 + kC 1 s + kC 0 x2 (s) = . x∗2 (s) s4 + kC 3 s3 + kC 2 s2 + kC 1 s + kC 0
(19)
On the other hand, the reference signal x∗1 can be calculated offline from the steady-state solution of (8). Thus, considering a unity PF (x2 = 0), the steady-state equations of (8) are vsd = Rs x∗1 + x∗3 U1 0 = ωLs x∗1 + x∗3 U2 i∗L = x∗1 U1
GPI controller of the dc bus output voltage loop. TABLE I NOMINAL PARAMETERS OF THE SPAMR
(y∗ − y) dt3 (18)
where the reference signal is y∗ = [ x∗1 x∗2 ]T . Equation (18) adds robustness with respect to unknown perturbations of the form p1 (t) suddenly appearing. It is important to note that p1 (t) represents a voltage sag in this particular case. Now, observe that (17) and (18) represent a linear controller. This is an additional advantage of the proposed feedback control scheme. So, performing the Laplace transform to (17) in closed loop with (18) and taking pdq as perturbation vector, the transfer functions from references to outputs are given by 3
Fig. 3.
(20)
where U1 and U2 are the nominal values of u1 and u2 , respectively, x∗3 is the desired dc bus voltage and i∗L = x∗3 /R is the nominal load current. Solving (20) for x∗1 and taking the solution that consumes less energy, the reference signal is given by ⎡ ⎤ 2 2 d ∗ d vs 1 v 4 (x3 ) ⎦ x∗1 = ⎣ s − . (21) − 2 Rs Rs RRs B. Voltage Loop Since reference signal x∗1 is calculated offline using the nominal parameters of the system and the load resistance, the current control becomes very sensitive to model uncertainties and load changes. In this paper, instead of estimating or measuring the load current, the available dc voltage is used to cope with this problem. This fact represents another contribution of this study. So, consider the perturbed dc voltage equation from (16) 1 d (22) C x3 = − x3 − p2 (t) + x1 u1 + x2 u2 . dt R
The dynamics of the current loop is designed to be much faster than the dynamics of the dc voltage loop; it is considered that u1 is always at its nominal value U1 . Thus, neglecting RS from (20), U1 ≈ vsd /x∗3 and considering a unity PF, the dc bus output voltage can be rewritten as d vs d ∗ C x3 = x1 + γ (t) (23) dt x∗3 where γ (t) = − (1/R) x3 − p2 (t) is a function that describes the unknown load current demand, considered like a perturbation depending of time t. Once again, assuming that γ (t) is well approximated by a second-degree polynomial, a third-order GPI controller is proposed x∗1 = kv 3 (x∗3 − x3 ) + kv 2 (x∗3 − x3 ) dt + kv 1
(x∗3
− x3 ) dt + kv 0 2
(x∗3 − x3 ) dt3 (24)
allowing the regulation of the dc bus output voltage under an unknown load. The block diagram of (23) with the GPI controller is shown in Fig. 3 and the closed-loop transfer function taking γ (t) as a perturbation is given by kv 3 s3 + kv 2 s2 + kv 1 s + kv 0 vsd x3 (s) = . (25) x∗3 (s) Cx∗3 s4 + (kv 3 s3 + kv 2 s2 + kv 1 s + kv 0 ) vsd IV. SIMULATION AND EXPERIMENTAL RESULTS A 1-kVA SPAMR prototype was built and tested; likewise, simulations were performed using the mathematical model with the proposed control scheme in order to evaluate the theoretical analysis. Table I shows the parameters of the prototype that were used to carry out simulations.
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Fig. 4.
Simulations in steady state. From top to bottom: dc bus voltage v d c , ac mains current is , and ac mains voltage v s .
Fig. 5.
Simulation results with voltage sag to 72% at t = 0.45 s. From top to bottom: regulated dc bus voltage vd c , ac mains current is , and ac mains voltage v s .
A. Simulation Results Two types of tests were proposed to validate the nonlinear control scheme ability to achieve the control objectives. The first one is concerned with the quality of the steady-state behavior and the second one is the ability to compensate voltage sags without using detection algorithms. The performance of the scheme on the entire operation range was also tested. For this purpose, an ac mains voltage sag was induced at the same time of several load changes. Fig. 4 shows the simulation results in steady state. A good response can be observed according to the numerical results presented in that figure, which are vs = 124 Vrm s , is = 9.36 Arm s , THDv = 0%, THDi = 6%, PF = 0.99, S = 1160 VA, P = 1160 W, Q = 0 VAR. The behavior of ac current and dc voltage is not optimal but satisfies the electrical customer operation conditions acceptably. A second test was provided to demonstrate the capability of the SPAMR to ride through a voltage sag. So, Fig. 5 shows a voltage sag to 72% of the nominal voltage magnitude occurring at t = 0.45 s. An excellent behavior of the closed-loop SPAMR is depicted with a steady-state dc voltage ripple of less than 10%
peak to peak. Note that at the start and at the end of the sag, the dc voltage variation has a maximum of 10%. The last test consisted in simultaneously applying a dynamic load in combination with several voltage sags, starting at time t = 1.5 s. With this test, the robust performance of the GPIcontrolled SPAMR in delivering an excellent response with enhanced robustness was demonstrated. Most importantly, the requirement of any sag detection algorithm is bypassed. This is demonstrated in Fig. 6 where the obtained simulation results are depicted. B. Experimental Results In order to ascertain the validity of the proposed control scheme, a 1-kVA prototype was built and tested. The controller was programmed in a DSP board TMS320F28335. The prototype parameters and controller gains are the same used in simulations and they are shown in Table I. The switching frequency was of 6 kHz and to obtain the switch pulses, a sinusoidal PWM strategy was used. Fig. 7 shows a picture of the implemented prototype used for experimental validation of the theoretical analysis.
LIRA et al.: ROBUST NONLINEAR CONTROL SCHEME FOR A SAG COMPENSATOR ACTIVE MULTILEVEL RECTIFIER
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Fig. 6. Simulation results with dynamical load and multiple sags applied simultaneously. From top to bottom: dc bus voltage vd c , ac mains current is , ac mains voltage v s , and load current Ir 1 .
Fig. 7.
1-kVA SPAMR prototype.
Fig. 8 shows the steady-state behavior with the following measured results vs = 123.31 Vrm s , is = 9.23 Arm s , THDv = 3.96%, THDi = 5.98%, PF = 0.98, S = 1138 VA, P = 1121 W, Q = 200.7 VAR. As it can be seen, the performance is quite similar to those obtained in the simulations. This demonstrates the feasibility of the proposed feedback control scheme. The original design of the SPAMR inductor was made considering a switching frequency of 20 kHz. However, simulations and experimental tests were carried out using 6 kHz in order to probe the robustness provided to the system by the controller. Thereby, the current ripple is more significant and as a consequence, the THD is higher. Therefore, this behavior is related with the topology but not with the controller performance. A test with a sag to 72% was implemented to demonstrate the performance of the closed-loop system under such a change of operation conditions. Fig. 9 shows the results; it is important to recognize that, comparing with Fig. 5, the results are similar. We emphasize the capability of the closed–loop-controlled SPAMR to compensate the sag event without using a sag detection algorithm.
Fig. 8. Experimental results in steady state. From top to bottom: dc bus voltage v d c , ac mains current is , and ac mains voltage v s .
Fig. 9. Experimental results with voltage sag to 72%. From top to bottom: dc bus voltage v d c , ac mains voltage v s , and ac mains current is .
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ACKNOWLEDGMENT The authors would like to thank the participation of Bachelor Student Y. Guill´en during the elaboration of this paper. REFERENCES
Fig. 10. Experimental results with dynamical load and multiple sags. From top to bottom: dc bus voltage v d c , ac mains current is , ac mains voltage v s , and load current Ir 1 .
Finally, a test was conducted on the SPAMR prototype which simultaneously used a significant load variation along with several induced voltage sags. Fig. 10 shows the experimental results, where it can be observed that the dc voltage is efficiently regulated. Moreover, the ripple was always kept below a 10% amplitude deviation.
V. CONCLUSION A nonlinear control scheme for an SPAMR has been proposed. The main motivations for this proposal were to provide to the SPAMR with the capability to work well in the operation range while exhibiting a good dynamic behavior. At the same time, this approach enjoys added robustness properties with respect to ac mains voltage perturbations and dynamical load changes while eliminating the need for a sag detection algorithm. This is, particularly, relevant from a power electronics viewpoint. It is important to mention that the controller parameters, both, in the simulations and in the experimental tests, were kept to be the same. A systematic procedure was developed to study the feasibility of this proposal. This consisted on obtaining a model in the dq synchronous reference frame of the system, achieving the exact linearization via feedback, and designing GPI controllers. Simulation and experimental results allow us to assert that it is possible to compensate voltage sags in active rectifiers without the use of detection algorithms. In the author’s opinion, this allows for a more reliable system given that sensors for sag detection were shown to be unnecessary. Moreover, it was experimentally demonstrated that the SPAMR maintains both good dynamical quality and excellent steady-state behavior. This points to the benefits that a good, robust, compensation scheme makes unnecessary the use of sag detection algorithms without compromising the basic performance features expected from an SPAMR.
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LIRA et al.: ROBUST NONLINEAR CONTROL SCHEME FOR A SAG COMPENSATOR ACTIVE MULTILEVEL RECTIFIER
Jesus Lira was born in San Luis Potos´ı, M´exico, on June 1957. He received the B.S. degree in ingenier´ıa electr´onica y comunicaciones from the Instituto Tecnol´ogico y de Estudios Superiores de Monterrey, Monterrey, M´exico, in 1978, and the M.S. and Ph.D. degrees in ingenier´ıa el´ectrica from the Universidad Aut´onoma de San Luis Potos´ı, San Luis Potos´ı, M´exico, in 2004 and 2009, respectively. Since 1987, he has been a Researcher at the Universidad Aut´onoma de San Luis Potos´ı. His research interests include power factor correction, control of power converters, power electronics, and power quality. Dr. Lira is a member of the IEEE Power Electronics Society and a member of the Sociedad Mexicana de Electr´onica de Potencia.
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Adrian Ramirez (S’12) was born in San Luis Potos´ı, M´exico, on August 1984. He received the B.S. degree in ingenier´ıa mecatr´onica from the Instituto Tecnol´ogico de San Luis Potos´ı, San Luis Potos´ı, and the M.S. degree in ingenier´ıa el´ectrica from the Universidad Aut´onoma de San Luis Potos´ı, San Luis Potos´ı, in 2008 and 2010, respectively. He is currently working toward the Ph.D. degree at the Centro de Investigaci´on y Estudios Avanzados, Instituto Polit´ecnico Nacional, M´exico City, M´exico. His research interests include power quality, power converters, and control of time delay systems.
Nancy Visairo was born in Oaxaca, M´exico. She received the M.S. and Ph.D. degrees in ingenier´ıa electr´onica from the Centro Nacional de Investigaci´on y Desarrollo Tecnol´ogico, Cuernavaca, M´exico, in 1999 and 2004, respectively. Since 2005, she has been a Researcher at the Universidad Aut´onoma de San Luis Potos´ı, San Luis Potos´ı, M´exico. Her main research interests include automatic control and fault diagnosis of dynamical systems. Dr. Visairo is a member of the IEEE Power Electronics Society.
Ciro Nunez (M’95) was born in Tampico, M´exico, on December 1970. He received the M.S. and Ph.D. degrees in ingenier´ıa electr´onica from the Centro Nacional de Investigaci´on y Desarrollo Tecnol´ogico, Cuernavaca, M´exico, in 1997 and 2002, respectively. Since 2002, he has been a Researcher at the Universidad Aut´onoma de San Luis Potos´ı, San Luis Potos´ı, M´exico. His main research interests include power electronics, power quality, smart grids, and control converters. Dr. Nunez is a member of the IEEE Power Electronics Society and a member of the Sociedad Mexicana de Electr´onica de Potencia.
Hebertt Sira-Ram´ırez was born in San Cristobal, Venezuela, on December 1948. He received the Graduate degree in ingeniero electricista from the Universidad de Los Andes, M´erida, Venezuela, in 1970, the M.S.E.E. and E.E. degrees in 1974 and the Ph.D. degree in electrical engineering in 1977 from the Massachusetts Institute of Technology, Cambridge. Since 1998, he has been an Emeritus Professor from the Universidad de Los Andes. Since 1998, he has been a Titular Researcher at the Centro de Investigaci´on y Estudios Avanzados, Instituto Polit´ecnico Nacional, Mexico City, Mexico. He has coauthored five books, 27 book chapters, 145 journal articles, and has participated in 260 international conferences in the field of automatic control. His main research interests include nonlinear systems theory and its applications in power electronics, variable structure systems, and systems identification.
