A Simple Model of Double-Loop Hysteresis Behavior in Memristive ...
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 60, NO. 8, AUGUST 2013
487
A Simple Model of Double-Loop Hysteresis Behavior in Memristive Elements A. S. Elwakil, Senior Member, IEEE, M. E. Fouda, and A. G. Radwan, Senior Member, IEEE
Abstract—This brief investigates the double-loop hysteresis behavior in memristive elements. Here, we propose a very simple dimensionless equation to model the double-loop behavior and then show how physical voltage- and current-controlled memristor models can be derived. Furthermore, we introduce the incremental/decremental positive/negative memristance/ transmemristance and present circuit emulators which are capable of emulating these devices. Experimental results are given.
variable xd (t) which is the ratio between the doped region length and the full length D of the memristor and is given by dxd = ki(t). dt
Integrating (2) and substituting in (1), assuming zero initial condition for the current, the memristance Rm can then be given by
Index Terms—Memristive elements, memristor, memristor circuits.
I. I NTRODUCTION
A
LTHOUGH memristive behavior was discovered nearly two centuries ago [1], the existence of a new circuit element different from the conventional R, L, and C elements was only postulated in [2] and [3] to represent the missing relation between the charge q and the flux φ. The memristor behavior is characterized by a pinched hysteresis loop, indicative of its inherent memory. In [4], a new device showing memristive behavior was reported. This memristor consists of a cube of titanium dioxide (TiO2 ) in two layers: The lower TiO2 layer has a perfect 2 : 1 oxygen-to-titanium ratio, making it an insulator. By contrast, the upper TiO2 layer is missing 0.5% of its oxygen (TiO2−x ). The vacancies make the TiO2−x material metallic and conductive [5]. Recently, many applications for memristors have been reported, including high-density nonvolatile memories [6]–[8], digital circuits [9], and analog circuits [10]–[12]. Moreover, memristors can be used to model neural spikes of the brain synapse [13], [14]. For all applications, a simple and accurate model of the memristor is needed. In [4], the memristor current–voltage relationship was described by v(t) = [xd (t)Ron + (1 − xd (t)) Roff ] i(t)
(1)
where i(t) represents the current through the memristor, v(t) is the voltage across the memristor, and Ron and Roff are the minimum and maximum achievable resistances of the memristor, respectively. The memristor resistance depends on state Manuscript received January 7, 2013; revised April 8, 2013; accepted May 31, 2013. Date of publication July 3, 2013; date of current version August 10, 2013. This brief was recommended by Associate Editor Y. Nishio. A. S. Elwakil is with the Department of Electrical and Computer Engineering, University of Sharjah, Sharjah, United Arab Emirates (e-mail: elwakil@ ieee.org). M. E. Fouda and A. G. Radwan are with the Department of Engineering Mathematics and Physics, College of Engineering, Cairo University, Giza 12316, Egypt (e-mail: [email protected]). Color versions of one or more of the figures in this brief are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TCSII.2013.2268376
(2)
Rm = Rin − kq(t)
(3)
where k = (μv Ron (Roff − Ron )/D2 )Ω/C, μv is the ion mobility, and Rin is the initial resistance of the memristor. In this brief, we propose a simple model that produces a double-loop hysteresis behavior similar to that of memristive elements and further clarify how this model can be used to design memristance emulator circuits. II. P ROPOSED M ODEL A symmetrical double-loop hysteresis behavior can be produced with the following model: ⎛ ⎞ t 1 y(t) = x(t) ⎝±a ± x(τ )dτ ⎠ (4) T 0
where y(t) is the normalized output, x(t) is the normalized input signal, a is a scaling constant, and T is an integration time constant which, when increased, leads to decreasing the memristive behavior. Fig. 1 shows the observed double-loop behavior for a = T = 1 when x(t) = cos(ωt) and ω = 1. Note that two cases are plotted in Fig. 1, namely the (+, +) and the (−, −) cases of (4) resulting in either a positively inclined loop or a negatively inclined loop, respectively. Two more cases, the (+, −) and the (−, +) cases, are also possible and lead to similar positively inclined and negatively inclined loops, respectively. It is clear that, for x(t) = cos(ωt), y(t)/x(t) = a + (1/T ω) sin(ωt) ∈ [a − (1/T ω), a + (1/T ω)]. Therefore, y = ±ax is a symmetry line, and the polarity of a determines the quadrant in which the hysteresis loop appears. The implementation of the double-loop hysteresis could be done using current or voltage signals; when x(t) is represented by a current and y(t) is represented by a voltage, the implementation is current controlled. Alternatively, when y(t) is represented by a current and x(t) is represented by a voltage, a voltage-controlled memristive device is obtained. It is worth noting that the authors of [15] have recently proposed conditions for symmetric pinched hysteresis. The aforementioned model satisfies these conditions and is simpler than the one in [15].
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Fig. 2. I–V characteristics of an incremental Rm at different frequencies with Iref = 1 μA and Rs = 10 kΩ.
Fig. 1. Double-loop hysteresis from (4) for T = 1 and x(t) = cos(t).
A. Current-Controlled Memristor Setting x(t) = i(t)/Iref and y(t) = v(t)/Iref Rs , where Iref is an arbitrary reference current and Rs is an arbitrary resistance, and substituting into (4), the current-controlled memristor equation is given by i(t)Rs v(t) = ±i(t)Rs ± T Iref
t i(τ )dτ
(5)
0
and hence, the memristance Rm = v(t)/i(t) is given by Rm = ±Rs ±
Rs q(t). T Iref
Fig. 3.
(6)
It is seen here that Rm is a function of the accumulated current which is essentially the charge q(t), similar to (3). In terms of the four different possibilities for Rm , which are (+, +), (+, −), (−, +), and (−, −), they represent incremental/decremental Rm and incremental/decremental negative Rm , respectively, as demonstrated hereinafter. B. Voltage-Controlled Memristor Setting x(t) = v(t)/Vref and y(t) = i(t)/Vref Gs , where Vref is an arbitrary reference voltage and Gs is an arbitrary transconductance, and substituting into (4), the voltage-controlled memristor equation is given by v(t) i(t) = ±v(t)Gs ± Gs T Vref
t v(τ )dτ
(7)
0
and hence, the transmemristance Gm is Gm = ±Gs ±
Gs φ(t) T Vref
(8)
where φ(t) is the accumulated flux. Similarly, there are four different possibilities representing incremental/decremental Gm and incremental/decremental negative Gm , respectively.
Maximum and minimum incremental Rm values when Rs = 10 kΩ.
III. S IMULATION R ESULTS Numerical simulations of selected cases are presented in this section, assuming that T = 1. Fig. 2 shows the I–V characteristics for an incremental Rm for four different frequencies of the sinusoidal input current i(t) with Iref = 1 μA and Rs = 10 kΩ. The maximum and minimum values of Rm are shown in Fig. 3, respectively, plotted once for the range of Iref spanning from 0.1 μA to 1 mA and another for the frequency range of from 0.1 Hz to 1 kHz of the input signal. In Fig. 4, the I–V characteristics for an incremental but negative Rm are also shown for four different frequencies of the sinusoidal input current i(t) with Iref = 1 μA and Rs = 10 kΩ. IV. C IRCUIT E MULATORS A memristor emulator circuit has been recently proposed in [16]. Emulator circuits are important to experiment with memristive devices in various applications due to the absence of physical commercially available devices. Here, we propose two emulator circuits, one for the current-controlled memristor and the other for the voltage-controlled memristor discussed previously. The two circuits are shown in Figs. 5 and 6, respectively, where two current conveyor (CCII) devices (built using the commercial AD844 current feedback operational amplifiers), a voltage multiplier (built using the commercial AD633 multiplier), and a noninverting or inverting buffer (built using a general-purpose operational amplifier such as the TL082) are
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Fig. 6. Voltage-controlled decremental/incremental memristor emulator.
Fig. 4. I–V characteristics of an incremental negative Rm at different frequencies with Iref = 1 μA and Rs = 10 kΩ.
noting that the circuit emulators in Figs. 5 and 6 can easily be implemented in integrated circuit form by using any of the available CMOS designs for current conveyors [17] and fourquadrant multipliers [18]. V. N ONSYMMETRICAL L OOP G ENERATION It is noted that (4) produces a symmetrical loop with the origin as the pinchoff point. It is possible to obtain nonsymmetrical loops through the modified model ⎛ ⎞ t dx(t) y(t) = x(t) ⎝±a ± c x(τ )dτ ⎠ ± b (13) dt 0
Fig. 5.
Current-controlled decremental/incremental memristor emulator.
needed. Analysis of Fig. 5 reveals that the input current is given by iin (t) =
Vin − Vfb Rs
(9)
where Vin is the applied voltage and Vfb is the feedback voltage given by Vfb
R2 = Kη 1 iin (t) R2 C
t
R2 iin (τ )dτ = Kη 1 iin (t)qin (t). R2 C
0
(10) Depending on the buffer operation, η is either 1 or −1 for an incremental/decremental memristor, respectively. The memristance is thus given by Rm (t) = Rs + Kη
R12 qin (t) R2 C
(11)
where K is the multiplier’s gain conversion with units of V −1 (K = 1/10 for the AD633). The aforementioned equation is similar to (3) if Rs /T Iref = K(R12 /R2 C). For the voltage-controlled memristor in Fig. 6, it can be shown that the transmemristance is given by Gm (t) = Gs − Kη
R22 φ(t). 2 R1 R3 R4 C
(12)
Note that there is an extra CCII in Fig. 6, compared to Fig. 5, which is employed as a voltage-to-current converter. It is worth
where a derivate term has been added to (4) and c = 1/T . If x(t) = cos(ωt), then (13) yields c y(t) = ax(t) ∓ bω − x(t) 1 − x2 (t). (14) ω It can be shown that the pinchoff point, which corresponds to the vanishing of the second term of (14), is given by
b ab 2 [xp , yp ] = ω 2 , ω (15) c c where xp ≤ 1. Moreover, the generated loop always passes by the three points: (x, y) = (1, a), (−1, −a) and (x, y) = (0, ±bω). Fig. 7(a) shows the observed nonsymmetrical loops for different values of a when b = c = 1 at f = 0.1 Hz. A 3-D view of these nonsymmetrical loops for different values of c when a = 0 and b = 1 is shown in Fig. 7(b), while Fig. 7(c) shows the case when a = b = 1, with both figures having f = 0.5 Hz. Note that, if xp = (b/c)ω 2 > 1, then there is no pinchoff point and a single loop is observed. VI. E XPERIMENTAL R ESULTS The circuit in Fig. 5 was practically implemented as shown in Fig. 8(a) with Rs = R1 = 1 kΩ and with R2 set as a 500-Ω variable resistor. The buffer sign was chosen to be +1, enabling a direct connection of the multiplier output to the noninverting input of U1 . The observed double-loop hysteresis is shown in Fig. 8(b) when C = 1 μF and the sinusoidal input voltage has a frequency f = 150 Hz. Note that the Y -axis in Fig. 8(b) is the voltage Vout1 of the operational amplifier U1 , which is also equal to −iin R1 . Similar double loops were observed for (C = 0.1 μF, f = 2 kHz) and
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Fig. 7. Nonsymmetrical loops generated using (13) when (a) (b, c) = (1, 1), (b) (a, b) = (0, 1), and (c) (a, b) = (1, 1).
(C = 2.2 nF, f = 100 kHz) which confirms the persistence of the behavior over a wide range of input frequencies. Fig. 8(c) shows the experimentally observed nonsymmetrical loop after connecting the differentiator circuit, shown in a box within Fig. 8(a), between the points labeled X and Y (i.e., across Rs ). The selected values for the differentiator were Cd = 10 μF, Rd1 = 200 Ω, and Rd2 = 5 kΩ. VII. L OOP G ENERATION W ITH A S WITCHING M ODEL From a circuit design perspective, reducing the complexity of implementing (4) requires finding an alternative to the analog
Fig. 8. Experimental results of a current-controlled memristor. (a) Implemented circuit, (b) Vin − Vout1 showing a symmetrical loop at R2 = 270 Ω, and (c) Vin − Vout1 showing a nonsymmetrical loop after adding the differentiator subcircuit.
multiplier block. A technique previously introduced in [19] implies replacing the multiplication function by a bipolar nonlinear switching function. Applying this technique to (4) yields the following model: t x(t) x(τ )dτ > 0 0t y(t) = ±ax(t) ± b (16) −x(t) 0 x(τ )dτ ≤ 0.
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square-wave input instead of the sinusoid. A typical four-corner hysteresis loop [shown in the corner of Fig. 9(c)] is observed. With no excitation, the charge stored on the capacitor eventually disappears through the operational amplifier output resistance and other leakage paths.
VIII. C ONCLUSION A simple model capable of producing double-loop hysteresis behavior has been proposed and experimentally verified. Two modified versions, one capable of producing nonsymmetrical loops and another based on a switching-type nonlinearity, have also been proposed and experimentally verified. R EFERENCES
Fig. 9. Circuit realization of the double-loop switching model with Spice and experimental results.
The hysteresis loop is confined between the two lines y = (±a ± b)x and y = (±a ∓ b)x. For memristive behavior, the condition |b| < 1 must hold. Fig. 9(a) shows a circuit implementation using a comparator (operational amplifier U3 ) and two ideal switches (S1 and S2 ). A Spice simulation is shown in Fig. 9(b) with Rs = R1 = 1 kΩ, R2 = 270 Ω, C = 1 μF, and b = 0.7. The experimentally observed loop is shown in Fig. 9(c) for the same component values, R2 = 250 Ω, and the frequency of the sinusoid Vin set to 100 Hz while its amplitude is set at 6V and b = (1/3). The switches were realized with NMOS and PMOS transistors from an LM4007 chip, respectively, while the two sources ±bVin in Fig. 9(a) were obtained from Vin through simple inverting and noninverting operational amplifiers. It is worth noting that the proposed emulator circuits show nonvolatility so long as they are excited. This is experimentally verified through exciting Fig. 9(a) with a
[1] T. Prodromakis, C. Toumazou, and L. Chua, “Two centuries of memristors,” Nature Mater., vol. 11, no. 6, pp. 478–481, Jun. 2012. [2] L. Chua, “Memristor—The missing circuit element,” IEEE Trans. Circuit Theory, vol. CT-18, no. 5, pp. 507–519, Sep. 1971. [3] L. O. Chua and S. M. Kang, “Memristive devices and systems,” Proc. IEEE, vol. 64, no. 2, pp. 209–223, Feb. 1976. [4] D. Strukov, G. Snider, D. Stewart, and R. Williams, “The missing memristor found,” Nature, vol. 453, no. 7191, pp. 80–83, May 2008. [5] R. Williams, “How we found the missing memristor,” IEEE Spectr., vol. 45, no. 12, pp. 28–35, Dec. 2008. [6] J. Cong and B. Xiao, “mrFPGA: A novel FPGA architecture with memristor-based reconfiguration,” in Proc. IEEE/ACM Int. Symp. NANOARCH, 2011, pp. 1–8. [7] Y. Ho, G. Huang, and P. Li, “Dynamical properties and design analysis for nonvolatile memristor memories,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 58, no. 4, pp. 724–736, Apr. 2011. [8] P. Vontobel, W. Robinett, P. Kuekes, D. Stewart, J. Straznicky, and R. Williams, “Writing to and reading from a nano-scale crossbar memory based on memristors,” Nanotechnology, vol. 20, no. 42, p. 425 204, Oct. 2009. [9] Q. Xia, W. Robinett, M. W. Cumbie, N. Banerjee, T. J. Cardinali, J. J. Yang, W. Wu, X. Li, W. M. Tong, D. B. Strukov, G. S. Snider, G. Medeiros-Ribeiro, and R. S. Williams, “Memristor hybrid integrated circuits for reconfigurable logic,” Nano Lett., vol. 9, no. 10, pp. 3640– 3645, Oct. 2009. [10] Y. Pershin and M. Di Ventra, “Practical approach to programmable analog circuits with memristors,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 57, no. 8, pp. 1857–1864, Aug. 2010. [11] S. Shin, K. Kim, and S. M. Kang, “Memristor applications for programmable analog integrated circuits,” IEEE Trans. Nanotechnol., vol. 10, no. 2, pp. 266–274, Mar. 2011. [12] M. Zidan, H. Omran, A. G. Radwan, and K. N. Salama, “Memristor-based reactance-less oscillator,” Electron. Lett., vol. 47, no. 22, pp. 1220–1221, Oct. 2011. [13] H. Kim, M. Sah, C. Yang, T. Roska, and L. Chua, “Neural synaptic weighting with a pulse-based memristor circuit,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 59, no. 1, pp. 148–158, Jan. 2012. [14] L. Chua, V. Sbitnev, and H. Kim, “Hodgkin–Huxley axon is made of memristors,” Int. J. Bifurcation Chaos, vol. 22, no. 3, pp. 1 230 011-1– 1 230 011-48, Nov. 2012. [15] D. Biolek, Z. Biolek, and V. Biolkova, “Pinched hysteretic loops of ideal memristors, memcapacitors and meminductors must be “self-crossing”,” Electron. Lett., vol. 47, no. 25, pp. 1385–1387, Dec. 2011. [16] H. Kim, M. Sah, C. Yang, S. Cho, and L. Chua, “Memristor emulator for memristor circuit applications,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 59, no. 10, pp. 2422–2431, Oct. 2012. [17] B. Calvo, S. Celma, P. Martinez, and M. T. Sanz, “High-speed highprecision CMOS current conveyor,” Analog Integr. Circuits Signal Process., vol. 36, no. 3, pp. 235–238, Sep. 2003. [18] S. Li, “LV/LP CMOS four-quadrant analog multiplier cell in modified bridged-triode scheme,” Analog Integr. Circuits Signal Process., vol. 33, no. 1, pp. 43–56, Oct. 2002. [19] A. S. Elwakil and M. P. Kennedy, “Construction of classes of circuitindependent chaotic oscillators using passive-only nonlinear devices,” IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 48, no. 3, pp. 289–307, Mar. 2001.
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A Simple Model of Double-Loop Hysteresis Behavior in Memristive Elements A. S. Elwakil, Senior Member, IEEE, M. E. Fouda, and A. G. Radwan, Senior Member, IEEE
Abstract—This brief investigates the double-loop hysteresis behavior in memristive elements. Here, we propose a very simple dimensionless equation to model the double-loop behavior and then show how physical voltage- and current-controlled memristor models can be derived. Furthermore, we introduce the incremental/decremental positive/negative memristance/ transmemristance and present circuit emulators which are capable of emulating these devices. Experimental results are given.
variable xd (t) which is the ratio between the doped region length and the full length D of the memristor and is given by dxd = ki(t). dt
Integrating (2) and substituting in (1), assuming zero initial condition for the current, the memristance Rm can then be given by
Index Terms—Memristive elements, memristor, memristor circuits.
I. I NTRODUCTION
A
LTHOUGH memristive behavior was discovered nearly two centuries ago [1], the existence of a new circuit element different from the conventional R, L, and C elements was only postulated in [2] and [3] to represent the missing relation between the charge q and the flux φ. The memristor behavior is characterized by a pinched hysteresis loop, indicative of its inherent memory. In [4], a new device showing memristive behavior was reported. This memristor consists of a cube of titanium dioxide (TiO2 ) in two layers: The lower TiO2 layer has a perfect 2 : 1 oxygen-to-titanium ratio, making it an insulator. By contrast, the upper TiO2 layer is missing 0.5% of its oxygen (TiO2−x ). The vacancies make the TiO2−x material metallic and conductive [5]. Recently, many applications for memristors have been reported, including high-density nonvolatile memories [6]–[8], digital circuits [9], and analog circuits [10]–[12]. Moreover, memristors can be used to model neural spikes of the brain synapse [13], [14]. For all applications, a simple and accurate model of the memristor is needed. In [4], the memristor current–voltage relationship was described by v(t) = [xd (t)Ron + (1 − xd (t)) Roff ] i(t)
(1)
where i(t) represents the current through the memristor, v(t) is the voltage across the memristor, and Ron and Roff are the minimum and maximum achievable resistances of the memristor, respectively. The memristor resistance depends on state Manuscript received January 7, 2013; revised April 8, 2013; accepted May 31, 2013. Date of publication July 3, 2013; date of current version August 10, 2013. This brief was recommended by Associate Editor Y. Nishio. A. S. Elwakil is with the Department of Electrical and Computer Engineering, University of Sharjah, Sharjah, United Arab Emirates (e-mail: elwakil@ ieee.org). M. E. Fouda and A. G. Radwan are with the Department of Engineering Mathematics and Physics, College of Engineering, Cairo University, Giza 12316, Egypt (e-mail: [email protected]). Color versions of one or more of the figures in this brief are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TCSII.2013.2268376
(2)
Rm = Rin − kq(t)
(3)
where k = (μv Ron (Roff − Ron )/D2 )Ω/C, μv is the ion mobility, and Rin is the initial resistance of the memristor. In this brief, we propose a simple model that produces a double-loop hysteresis behavior similar to that of memristive elements and further clarify how this model can be used to design memristance emulator circuits. II. P ROPOSED M ODEL A symmetrical double-loop hysteresis behavior can be produced with the following model: ⎛ ⎞ t 1 y(t) = x(t) ⎝±a ± x(τ )dτ ⎠ (4) T 0
where y(t) is the normalized output, x(t) is the normalized input signal, a is a scaling constant, and T is an integration time constant which, when increased, leads to decreasing the memristive behavior. Fig. 1 shows the observed double-loop behavior for a = T = 1 when x(t) = cos(ωt) and ω = 1. Note that two cases are plotted in Fig. 1, namely the (+, +) and the (−, −) cases of (4) resulting in either a positively inclined loop or a negatively inclined loop, respectively. Two more cases, the (+, −) and the (−, +) cases, are also possible and lead to similar positively inclined and negatively inclined loops, respectively. It is clear that, for x(t) = cos(ωt), y(t)/x(t) = a + (1/T ω) sin(ωt) ∈ [a − (1/T ω), a + (1/T ω)]. Therefore, y = ±ax is a symmetry line, and the polarity of a determines the quadrant in which the hysteresis loop appears. The implementation of the double-loop hysteresis could be done using current or voltage signals; when x(t) is represented by a current and y(t) is represented by a voltage, the implementation is current controlled. Alternatively, when y(t) is represented by a current and x(t) is represented by a voltage, a voltage-controlled memristive device is obtained. It is worth noting that the authors of [15] have recently proposed conditions for symmetric pinched hysteresis. The aforementioned model satisfies these conditions and is simpler than the one in [15].
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Fig. 2. I–V characteristics of an incremental Rm at different frequencies with Iref = 1 μA and Rs = 10 kΩ.
Fig. 1. Double-loop hysteresis from (4) for T = 1 and x(t) = cos(t).
A. Current-Controlled Memristor Setting x(t) = i(t)/Iref and y(t) = v(t)/Iref Rs , where Iref is an arbitrary reference current and Rs is an arbitrary resistance, and substituting into (4), the current-controlled memristor equation is given by i(t)Rs v(t) = ±i(t)Rs ± T Iref
t i(τ )dτ
(5)
0
and hence, the memristance Rm = v(t)/i(t) is given by Rm = ±Rs ±
Rs q(t). T Iref
Fig. 3.
(6)
It is seen here that Rm is a function of the accumulated current which is essentially the charge q(t), similar to (3). In terms of the four different possibilities for Rm , which are (+, +), (+, −), (−, +), and (−, −), they represent incremental/decremental Rm and incremental/decremental negative Rm , respectively, as demonstrated hereinafter. B. Voltage-Controlled Memristor Setting x(t) = v(t)/Vref and y(t) = i(t)/Vref Gs , where Vref is an arbitrary reference voltage and Gs is an arbitrary transconductance, and substituting into (4), the voltage-controlled memristor equation is given by v(t) i(t) = ±v(t)Gs ± Gs T Vref
t v(τ )dτ
(7)
0
and hence, the transmemristance Gm is Gm = ±Gs ±
Gs φ(t) T Vref
(8)
where φ(t) is the accumulated flux. Similarly, there are four different possibilities representing incremental/decremental Gm and incremental/decremental negative Gm , respectively.
Maximum and minimum incremental Rm values when Rs = 10 kΩ.
III. S IMULATION R ESULTS Numerical simulations of selected cases are presented in this section, assuming that T = 1. Fig. 2 shows the I–V characteristics for an incremental Rm for four different frequencies of the sinusoidal input current i(t) with Iref = 1 μA and Rs = 10 kΩ. The maximum and minimum values of Rm are shown in Fig. 3, respectively, plotted once for the range of Iref spanning from 0.1 μA to 1 mA and another for the frequency range of from 0.1 Hz to 1 kHz of the input signal. In Fig. 4, the I–V characteristics for an incremental but negative Rm are also shown for four different frequencies of the sinusoidal input current i(t) with Iref = 1 μA and Rs = 10 kΩ. IV. C IRCUIT E MULATORS A memristor emulator circuit has been recently proposed in [16]. Emulator circuits are important to experiment with memristive devices in various applications due to the absence of physical commercially available devices. Here, we propose two emulator circuits, one for the current-controlled memristor and the other for the voltage-controlled memristor discussed previously. The two circuits are shown in Figs. 5 and 6, respectively, where two current conveyor (CCII) devices (built using the commercial AD844 current feedback operational amplifiers), a voltage multiplier (built using the commercial AD633 multiplier), and a noninverting or inverting buffer (built using a general-purpose operational amplifier such as the TL082) are
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Fig. 6. Voltage-controlled decremental/incremental memristor emulator.
Fig. 4. I–V characteristics of an incremental negative Rm at different frequencies with Iref = 1 μA and Rs = 10 kΩ.
noting that the circuit emulators in Figs. 5 and 6 can easily be implemented in integrated circuit form by using any of the available CMOS designs for current conveyors [17] and fourquadrant multipliers [18]. V. N ONSYMMETRICAL L OOP G ENERATION It is noted that (4) produces a symmetrical loop with the origin as the pinchoff point. It is possible to obtain nonsymmetrical loops through the modified model ⎛ ⎞ t dx(t) y(t) = x(t) ⎝±a ± c x(τ )dτ ⎠ ± b (13) dt 0
Fig. 5.
Current-controlled decremental/incremental memristor emulator.
needed. Analysis of Fig. 5 reveals that the input current is given by iin (t) =
Vin − Vfb Rs
(9)
where Vin is the applied voltage and Vfb is the feedback voltage given by Vfb
R2 = Kη 1 iin (t) R2 C
t
R2 iin (τ )dτ = Kη 1 iin (t)qin (t). R2 C
0
(10) Depending on the buffer operation, η is either 1 or −1 for an incremental/decremental memristor, respectively. The memristance is thus given by Rm (t) = Rs + Kη
R12 qin (t) R2 C
(11)
where K is the multiplier’s gain conversion with units of V −1 (K = 1/10 for the AD633). The aforementioned equation is similar to (3) if Rs /T Iref = K(R12 /R2 C). For the voltage-controlled memristor in Fig. 6, it can be shown that the transmemristance is given by Gm (t) = Gs − Kη
R22 φ(t). 2 R1 R3 R4 C
(12)
Note that there is an extra CCII in Fig. 6, compared to Fig. 5, which is employed as a voltage-to-current converter. It is worth
where a derivate term has been added to (4) and c = 1/T . If x(t) = cos(ωt), then (13) yields c y(t) = ax(t) ∓ bω − x(t) 1 − x2 (t). (14) ω It can be shown that the pinchoff point, which corresponds to the vanishing of the second term of (14), is given by
b ab 2 [xp , yp ] = ω 2 , ω (15) c c where xp ≤ 1. Moreover, the generated loop always passes by the three points: (x, y) = (1, a), (−1, −a) and (x, y) = (0, ±bω). Fig. 7(a) shows the observed nonsymmetrical loops for different values of a when b = c = 1 at f = 0.1 Hz. A 3-D view of these nonsymmetrical loops for different values of c when a = 0 and b = 1 is shown in Fig. 7(b), while Fig. 7(c) shows the case when a = b = 1, with both figures having f = 0.5 Hz. Note that, if xp = (b/c)ω 2 > 1, then there is no pinchoff point and a single loop is observed. VI. E XPERIMENTAL R ESULTS The circuit in Fig. 5 was practically implemented as shown in Fig. 8(a) with Rs = R1 = 1 kΩ and with R2 set as a 500-Ω variable resistor. The buffer sign was chosen to be +1, enabling a direct connection of the multiplier output to the noninverting input of U1 . The observed double-loop hysteresis is shown in Fig. 8(b) when C = 1 μF and the sinusoidal input voltage has a frequency f = 150 Hz. Note that the Y -axis in Fig. 8(b) is the voltage Vout1 of the operational amplifier U1 , which is also equal to −iin R1 . Similar double loops were observed for (C = 0.1 μF, f = 2 kHz) and
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Fig. 7. Nonsymmetrical loops generated using (13) when (a) (b, c) = (1, 1), (b) (a, b) = (0, 1), and (c) (a, b) = (1, 1).
(C = 2.2 nF, f = 100 kHz) which confirms the persistence of the behavior over a wide range of input frequencies. Fig. 8(c) shows the experimentally observed nonsymmetrical loop after connecting the differentiator circuit, shown in a box within Fig. 8(a), between the points labeled X and Y (i.e., across Rs ). The selected values for the differentiator were Cd = 10 μF, Rd1 = 200 Ω, and Rd2 = 5 kΩ. VII. L OOP G ENERATION W ITH A S WITCHING M ODEL From a circuit design perspective, reducing the complexity of implementing (4) requires finding an alternative to the analog
Fig. 8. Experimental results of a current-controlled memristor. (a) Implemented circuit, (b) Vin − Vout1 showing a symmetrical loop at R2 = 270 Ω, and (c) Vin − Vout1 showing a nonsymmetrical loop after adding the differentiator subcircuit.
multiplier block. A technique previously introduced in [19] implies replacing the multiplication function by a bipolar nonlinear switching function. Applying this technique to (4) yields the following model: t x(t) x(τ )dτ > 0 0t y(t) = ±ax(t) ± b (16) −x(t) 0 x(τ )dτ ≤ 0.
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square-wave input instead of the sinusoid. A typical four-corner hysteresis loop [shown in the corner of Fig. 9(c)] is observed. With no excitation, the charge stored on the capacitor eventually disappears through the operational amplifier output resistance and other leakage paths.
VIII. C ONCLUSION A simple model capable of producing double-loop hysteresis behavior has been proposed and experimentally verified. Two modified versions, one capable of producing nonsymmetrical loops and another based on a switching-type nonlinearity, have also been proposed and experimentally verified. R EFERENCES
Fig. 9. Circuit realization of the double-loop switching model with Spice and experimental results.
The hysteresis loop is confined between the two lines y = (±a ± b)x and y = (±a ∓ b)x. For memristive behavior, the condition |b| < 1 must hold. Fig. 9(a) shows a circuit implementation using a comparator (operational amplifier U3 ) and two ideal switches (S1 and S2 ). A Spice simulation is shown in Fig. 9(b) with Rs = R1 = 1 kΩ, R2 = 270 Ω, C = 1 μF, and b = 0.7. The experimentally observed loop is shown in Fig. 9(c) for the same component values, R2 = 250 Ω, and the frequency of the sinusoid Vin set to 100 Hz while its amplitude is set at 6V and b = (1/3). The switches were realized with NMOS and PMOS transistors from an LM4007 chip, respectively, while the two sources ±bVin in Fig. 9(a) were obtained from Vin through simple inverting and noninverting operational amplifiers. It is worth noting that the proposed emulator circuits show nonvolatility so long as they are excited. This is experimentally verified through exciting Fig. 9(a) with a
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