A Simple Nonlinear Gain Scheduling Method in
A Simple Nonlinear Gain Scheduling Method in Digital PWM Converter Control Hao Peng1 and Chin Chang2 [email protected], 2580 N 1st St., Semtech Corp., San Jose, CA 95131, U.S.A [email protected], 200 Flynn Rd, Semtech Corp., Camarillo, CA 93012, U.S.A
1 2
Abstract - In this paper, we analyze a simple, yet effective nonlinear digital control approach -- gain scheduling of the A/D converter, in PWM converters to achieve system stability and improved dynamic performance. It is shown that a nonlinear gain scheduling could be conveniently realized and implemented, e.g. right after the A/D converter in digital controlled PWM converters. Several simple gain scheduling schemes are analyzed with describing function method, and associated gains are derived and provided. Experimental results on a FPGA system showed that the Buck converter transient response could be improved via nonlinear gain scheduling method. However, in Boost and Buck-Boost converters, it is necessary to make proper controller adjustment (pole and zero) so that the system stability is guaranteed not only with normal gain, but also with reduced gain.
I.
INTRODUCTION
Digital control in power converters has the advantages of programmability, flexibility and more built-in intelligence over analog control. These advantages have been proven to be feasible at cost comparable to or even lower than the corresponding analog solutions. Recent endeavor on power converter digital control has resulted in numerous publications [1-5] and several important IC chip releases [6-7]. Among the benefits offered by digital control, one could conveniently develop nonlinear control scheme to improve converter transient response performance while still maintain solid system stability. While there are many different ways and schemes to implement nonlinear control method, [8] presented a nonlinear time optimal control based digital implementation, and [9] studied hybrid digital adaptive control laws for DC-DC converters. In this paper, we analyze a simple, yet effective nonlinear digital control approach -- gain scheduling of the A/D converter, to achieve system stability and improved dynamic performance. In this approach, the nonlinearity is introduced by selectively modifying the output of the linear A/D converter. When the A/D error signal is small, a lower gain is applied. It makes the closed loop system less sensitive to noise. When the A/D error signal is greater than a certain threshold value, a higher gain is applied. It provides larger corrective action during the load transient. Even though some variant of this gain scheduling method has been applied in some places [6], this paper addresses this approach in a systematic manner. Specifically, Section II introduces the nonlinear gain in A/D and its role in digital control of PWM converter. In Section III, we used the describing function
method [10] to evaluate the nonlinear gain at different region along with two important examples. To verify the effectiveness of this nonlinear gain scheduling on system dynamic response improvement, experimental results on an FPGA system are provided in Section IV. Section V discusses applications of this gain scheduling method and the effect on compensator design. Some conclusions are provided in section VI. II.
DIGITAL CONTROL OF PWM CONVERTERS WITH NONLINEAR GAIN SCHEDULING
A proposed digital controlled DC-DC PWM converter diagram is shown in Fig.1. Where the A/D converter is of linear type and samples once per each switching period. High resolution DPWM is assumed for the precise regulation of the PWM converter. The compensator Gc(z) is a typical PID with time domain expression as d [n] = d [n − 1] + b0 e[n] − b1e[n − 1] + b2 e[n − 2] . (2.1) The corresponding Z-domain transfer function is:
Gc (z) =
b0z2 − b1z + b2 . z(z −1)
(2.2)
Between the linear compensator Gc(z) and the linear A/D, in digital domain, a simple nonlinear gain scheduling block is inserted as shown in Fig.1. A typical characteristic of the gain scheduling block is shown in Fig. 2, and its characteristics are expressed in the following equations.
Power Stage
Gain Scheduling Block
DPWM
GC(z)
A/D
- Vref +
Compensator
Figure 1: Block diagram of a digital controlled PWM converter with gain scheduling
G = α1, a < a1 ⎡ 1⎛ 4 ⎛ a1 ⎞ 2 ⎛ ⎛ a1 ⎞ ⎞ ⎞⎤ ⎢α1 + (α 2 − α1) × ⎜⎜ 2 − arcsin⎜ ⎟ + sin⎜⎜ 2 arcsin⎜ ⎟ ⎟⎟ ⎟⎟⎥ π 2⎝ ⎝a⎠ π ⎝ ⎝ a ⎠ ⎠ ⎠⎥ ⎢ = ⎢ ⎥, a1 < a < a2 a a 1 4 1 ⎛ ⎞ ⎥ ⎢− (α 2 − α1) × × cos(arcsin⎜ ⎟) a π ⎝a⎠ ⎦⎥ ⎣⎢
α3
b2
α2 -a2
-a1
b1 α1 a1 -b1
a2
-b2
Figure 2: Typical input-output characteristics of the gain scheduling block e[n] = f(e) = α1× e, e < a1
⎡ 1⎛ 4 ⎛ a1 ⎞ 2 ⎛ ⎛ a1 ⎞ ⎞ ⎞⎤ ⎢α1 + (α 2 − α1) × ⎜⎜ 2 − arcsin⎜ ⎟ + sin⎜⎜ 2 arcsin⎜ ⎟ ⎟⎟ ⎟⎟⎥ π 2⎝ ⎝a⎠ π ⎝ ⎝ a ⎠ ⎠ ⎠⎥ ⎢ ⎥ ⎢ a a 1 4 1 ⎛ ⎞ ⎥ ⎢− (α 2 − α1) × × cos(arcsin⎜ ⎟) ⎥ ⎢ a π ⎝a⎠ = ⎢ ⎥, a 2 < a ⎢ 1 ⎛⎜ 4 ⎛ a2 ⎞ 2 ⎛ ⎛ a2 ⎞ ⎞ ⎞⎟ ⎥ ⎟ ⎜ ⎢+ (α 3 − α 2) × ⎜ 2 − arcsin⎜ ⎟ + sin⎜ 2 arcsin⎜ ⎟ ⎟ ⎟ ⎥ π 2⎝ ⎝ a ⎠ π ⎝ ⎝ a ⎠⎠⎠ ⎥ ⎢ ⎥ ⎢ a2 4 ⎛ a2 ⎞ ⎥ ⎢− (α 3 − α 2) × × cos(arcsin⎜ ⎟) a π a ⎥⎦ ⎢⎣ ⎝ ⎠
(2.3)
With the above derived nonlinear gains, we can conduct the stability analysis of the digital controlled PWM converters. In the following, we discuss two important examples.
In the above notations, it is assumed that the A/D has good resolution and the quantization effect does not affect the stability.
Example 1: Figure 4 a) shows one practical gain scheduling scheme. The benefit of this scheme is that it provides no sensitivity around the steady state point, thus noise will have little effect in the regular operation. In this case, α 1 = 0, α 2 = α 3
= b1 + α 2 × (e − a1), a 2 ≥ e ≥ a1
= - b1 + α 2 × (e + a1),−a1 ≥ e ≥ −a 2 = b2 + α 3 × (e − a 2), e ≥ a 2
= - b2 + α 3 × (e + a 2 ), e ≤ −a 2
ANALYSIS OF NONLINEAR GAIN SCHEDULING
When the digital control loop contains nonlinear component, a simple way to study its effect on the loop stability is using describing function [10]. The describing function method is illustrated in Figure 3. With sinusoidal input to the nonlinear component as: x(t ) = a sin(ωt ) , the Fourier expansion of the output y(t) is y (t ) = b0 + b1 sin(ωt ) + b2 sin( 2ωt ) + L , the gain G of the nonlinear components can be found as b G= 1 . a This gain could be amplitude or frequency dependent. Applying the describing function method to the nonlinear gain characteristics shown in Figure 2, one could derive the following interesting gain factors.
α2 -a1 a1
(a) Gain vs Amplitude 1.2 1 0.8 gain
III.
0.6 0.4 0.2
x(t)
Nonlinear Block
Figure 3: Describing function method
y(t)
0 0
20
40
60
80
100
a/a1
(b) Figure 4 (a) Gain scheduling scheme (b) Gain through the A/D The gain through the A/D can be simplified as:
G = 0, a < a1 ⎡ ⎛ 1⎛ 4 ⎛ a1 ⎞ 2 ⎛ a1 ⎞ ⎞ ⎞⎤ ⎢α 2 × ⎜⎜ 2 − arcsin⎜ ⎟ + sin ⎜⎜ 2 arcsin⎜ ⎟ ⎟⎟ ⎟⎟⎥ π 2⎝ ⎝a⎠ π ⎝ a ⎠ ⎠ ⎠⎥ ⎝ = ⎢⎢ ⎥, a1 < a ⎥ ⎢− α 2 × a1 × 4 cos(arcsin⎛⎜ a1 ⎞⎟) a π ⎝a⎠ ⎦⎥ ⎣⎢
Figure 4 b) plots the gain with α 2 = 1 . It can be seen that the gain initially has a small value. When the input signal amplitude increases, the gain increases with a nonlinear relation. The upper limit for the gain through the A/D is 1. Example 2: Another commonly encountered gain scheduling scheme is shown in figure 5 a), which actually models the saturation effect of the A/D. In this gain scheduling scheme, α1 = α 2, α 3 = 0 and the gain in this gain scheduling scheme is:
α1 = 1 . It is clear that this gain has an initial value of 1 and decreases nonlinearly when the amplitude of the input sinusoidal signal increases. IV.
EXPERIMENTAL VERIFICATION
An FPGA system is developed to verify the digital control of DC-DC converters with and without nonlinear gain scheduling. The DC-DC Buck converter power stage parameters are L = 1.4 µH, Cout = 630 µF, Vin = 12V, Vout = 2V, the switching frequency is 500 kHz, and the error A/D has 9 bits with LSB resolution of 0.5mV. The A/D characteristics of the conventional digital control versus with gain scheduling are shown in Figure 6 a) and b), respectively.
2
-a2
-a2
G = α1, a < a1
-a1
a2
1
1 a1
a2
⎡ ⎛ 1⎛ 4 ⎛ a2 ⎞ 2 ⎛ a 2 ⎞ ⎞ ⎞⎤ ⎢α1 + (− α1)× ⎜⎜ 2 − arcsin⎜ ⎟ + sin ⎜⎜ 2 arcsin⎜ ⎟ ⎟⎟ ⎟⎟⎥ 2 π π a ⎝ ⎠ ⎝ a ⎠ ⎠ ⎠⎥ ⎝ ⎝ = ⎢⎢ ⎥, a 2 < a ⎢+ (α1)× a 2 × 4 cos(arcsin⎛⎜ a 2 ⎞⎟) ⎥ ⎢⎣ ⎥⎦ a π ⎝ a ⎠
(a)
(b)
Figure 6 (a) A/D characteristic with conventional scheme (b) A/D characteristic with gain scheduling α1
The gain of the A/D converter with saturation characteristics in Fig. 6 a) can be found from Fig. 5 b). The gain of the A/D converter gain scheduling characteristic in Fig. 6 b) is plotted in Fig. 7. The maximum gain is around 1.92 when the amplitude of the input sinusoidal signal reaches the saturation limit. Based on these gain calculation results, a compensator is designed and implemented for both schemes. 7 ⎞⎛ 31 ⎞ ⎛ ⎜ z − ⎟⎜ z − ⎟ 8 ⎠⎝ 32 ⎠ Gc ( z ) = 1.5 ⎝ z (z − 1)
-a2 a2
(a) Gain vs Amplitude 1.2 1
Gain vs Amplitude 2.5
0.6 0.4
2
0.2
1.5
gain
gain
0.8
0 0
5
10
15
1
20
a/a2
(b) Figure 5 (a) Gain scheduling scheme (b) Gain through the A/D The plot in Figure 5 b) shows the gain of this scheme with
0.5 0 0
5
10
15
20
25
30
35
40
a/a1
Figure 7 Gain of A/D characteristics with gain scheduling as in figure 6 (b) with a1 = 8 mV, a2 = 128 mV
(a)
However, for converters with a right half plane zero (RHZ), such as Boost and Buck-Boost converters, if the compensator is not properly designed, decreasing the gain (due to the nonlinear zero bin or saturation effect) may actually cause a stability problem. To illustrate this effect, the following examples on Boost converters are designed and illustrated. The boost converter power stage parameters are: L = 5 µH, C = 60 µF, Vin = 5V, Vout = 10V, the switching frequency is 500 kHz, the load resistance is 11.6 Ω. The power stage control to output transfer function is: s 1− Vout ωz G vd ( s ) = , 2 1− D ⎛ s ⎞ s ⎟ 1+ +⎜ ω 0 Q ⎜⎝ ω 0 ⎟⎠ where (1 − D )2 R , Q = (1 − D) C 1− D f0 = , fz = 2πL L 2π LC Based on the transfer function, the following digital controller is designed, (z − 0.954)(z − 0.766) G c ( z ) = 6.03 z (z − 1) Figure 9 shows the Bode plot of the designed open loop transfer function.
(b) Figure 8 Load transient responses of Buck converter with A/D characteristic in Fig. 6 a) (a) and in Fig. 6 b) (b) Under this compensator, the digital controlled PWM Buck converter in Fig.1 has the load transient responses shown in Fig. 8. It is seen that for the same 5A load transient, the output undershoot is around 50mV with conventional digital control scheme, and the output undershoot is around 30mV when the nonlinear gain scheduling is applied. V.
DISCUSSIONS
From the analysis in Section III, the gain through the A/D can be very small if there is a zero error bin or saturation effects on the A/D. The maximum gain through the A/D is less than the maximum slope in the gain scheduling method. Practically, the zero error bin and saturation effects always exist because of the resolution of the A/D and the existence of the saturation on the A/D and DPWM. So when design a digital compensator for the power stage, it has to be kept in mind that the gain could be significantly smaller than the designed value because of the above mentioned nonlinear effects. For buck converters, small gain does not introduce stability problems. The gain scheduling method enables a slow response around the steady state point, to make the closed loop less sensitive to noise; while provides large corrective action in big load transient responses as illustrated in the experimental verification in Section IV.
Figure 9 Bode plot of the targeted boost converter design From the Bode plot, it can be seen that when the loop gain is reduced, without changing the compensator poles and zeroes, there is an area that the system may become unstable. Assume that the gain of the digital controller is reduced due to the nonlinear zero error bin or saturation effect in the A/D (z − 0.954)(z − 0.766) , Gc ( z ) = 0.121 z (z − 1) Figure 10 shows the Bode plot of the system with reduced gain. Figure 11 shows the output voltage and the duty command waveforms before and after the saturation block in simulation with Simulink. Clearly, the system is not stable.
Figure 10 Bode plot of a digital controlled boost converter with reduced gain
Figure 12 Bode plot of a digital controlled boost converter with improved compensator design
Figure 11 Simulated output voltage and duty command waveforms before and after saturation block In order to solve the stability problem caused by the smaller gain introduced by the nonlinear effects mentioned above, another compensator with zero position adjustment is designed with transfer function (z − 0.989)(z − 0.901) . G c ( z ) = 6.03 z (z − 1) The Bode plot of the system is shown in Figure 12. With this compensator, the system is clearly stable with reduced gain. Figure 13 shows the output voltage and duty command waveforms in simulation with Simulink. In Buck converters, such problem may not exist. However, the application of this gain scheduling method is not without limitation. The maximum crossover frequency is limited by the accuracy of the average model. At the same time, overshoot requirement and delays in the loop constraint the minimum phase margin that should be obtained with maximum gain achievable through the nonlinear effects described in the previous sections.
Figure 13 Simulated output voltage and duty command waveforms with improved compensator design VI.
CONCLUSIONS
In digital controlled PWM converters, nonlinear gain scheduling could be conveniently realized and implemented, e.g. right after the A/D converter. Several typical gain scheduling schemes are analyzed with describing function method and the associated gains are derived and provided. The varied nonlinear gain should be considered in digital compensator design. Experimental results on an FPGA system with Buck converter showed that the system transient response can be improved via nonlinear gain scheduling method. However, caution should be paid in applying gain scheduling method to Boost and Buck-Boost converters. It is shown via Simulink simulation that the system stability may change with gain variation in these converters. It is required to guarantee the system stability not only with normal gain, but also with reduced gain.
REFERENCES [1] A. Peterchev, J. Xiao, and S. Sanders, “Architecture and IC implementation of a Digital VRM Controller,” IEEE Trans. Power Electronics, vol. 18, pp. 356–364, Jan. 2003. [2] B. Patella, A. Prodic, A. Zirger, and D. Maksimović, “High-frequency digital PWM controller IC for DC-DC converters,” IEEE Trans. Power Electron., vol. 18, pp. 438–446, Jan. 2003. [3] H. Peng, A. Prodic, E. Alarcon, and D. Maksimović, “Modeling of quantization effects in digitally controlled DC-DC converters,” IEEE Trans. Power Electron., vol. 22, pp. 208–215, Jan. 2007. [4] V. Yousefzadeh and D. Maksimović, “Sensorless optimization of dead times in dc-dc converters with synchronous rectifiers,” IEEE Trans. Power Electron, vol. 21, pp. 994–1002, Nov. 2006. [5] W. Stefanutti, P. Mattavelli, S. Saggini, and M. Ghioni, “Autotuning of digitally controlled DC-DC converters based on relay feedback,” IEEE Trans. Power Electron., vol. 22, pp. 199–207, Jan. 2007. [6] “UCD9240 datasheet,” Texas Instruments Inc., Dallas, USA. [7] “PX7520 datasheet”, Primarion, Torrance, CA, USA. [8] A. Costabeber, L. Corradini, P. Mattavelli, S. Saggini, “Time Optimal, Parameters-insensitive Digital Controller for DC-DC Buck Converters” IEEE PESC 2008, pp. 1243-1249. [9] A. Babazadeh, D. Maksimović, “Hybrid Digital Adaptive Control for Synchronous Buck DC-DC Converters”, IEEE PESC 2008, pp. 1263-1269 [10] E. Davison and D. Constantinesou, “A describing function technique for multiple nonlinearities in a single-loop feedback system,” IEEE Trans. Autom. Control, vol. 16, pp. 56–60, Feb. 1971.
1 2
Abstract - In this paper, we analyze a simple, yet effective nonlinear digital control approach -- gain scheduling of the A/D converter, in PWM converters to achieve system stability and improved dynamic performance. It is shown that a nonlinear gain scheduling could be conveniently realized and implemented, e.g. right after the A/D converter in digital controlled PWM converters. Several simple gain scheduling schemes are analyzed with describing function method, and associated gains are derived and provided. Experimental results on a FPGA system showed that the Buck converter transient response could be improved via nonlinear gain scheduling method. However, in Boost and Buck-Boost converters, it is necessary to make proper controller adjustment (pole and zero) so that the system stability is guaranteed not only with normal gain, but also with reduced gain.
I.
INTRODUCTION
Digital control in power converters has the advantages of programmability, flexibility and more built-in intelligence over analog control. These advantages have been proven to be feasible at cost comparable to or even lower than the corresponding analog solutions. Recent endeavor on power converter digital control has resulted in numerous publications [1-5] and several important IC chip releases [6-7]. Among the benefits offered by digital control, one could conveniently develop nonlinear control scheme to improve converter transient response performance while still maintain solid system stability. While there are many different ways and schemes to implement nonlinear control method, [8] presented a nonlinear time optimal control based digital implementation, and [9] studied hybrid digital adaptive control laws for DC-DC converters. In this paper, we analyze a simple, yet effective nonlinear digital control approach -- gain scheduling of the A/D converter, to achieve system stability and improved dynamic performance. In this approach, the nonlinearity is introduced by selectively modifying the output of the linear A/D converter. When the A/D error signal is small, a lower gain is applied. It makes the closed loop system less sensitive to noise. When the A/D error signal is greater than a certain threshold value, a higher gain is applied. It provides larger corrective action during the load transient. Even though some variant of this gain scheduling method has been applied in some places [6], this paper addresses this approach in a systematic manner. Specifically, Section II introduces the nonlinear gain in A/D and its role in digital control of PWM converter. In Section III, we used the describing function
method [10] to evaluate the nonlinear gain at different region along with two important examples. To verify the effectiveness of this nonlinear gain scheduling on system dynamic response improvement, experimental results on an FPGA system are provided in Section IV. Section V discusses applications of this gain scheduling method and the effect on compensator design. Some conclusions are provided in section VI. II.
DIGITAL CONTROL OF PWM CONVERTERS WITH NONLINEAR GAIN SCHEDULING
A proposed digital controlled DC-DC PWM converter diagram is shown in Fig.1. Where the A/D converter is of linear type and samples once per each switching period. High resolution DPWM is assumed for the precise regulation of the PWM converter. The compensator Gc(z) is a typical PID with time domain expression as d [n] = d [n − 1] + b0 e[n] − b1e[n − 1] + b2 e[n − 2] . (2.1) The corresponding Z-domain transfer function is:
Gc (z) =
b0z2 − b1z + b2 . z(z −1)
(2.2)
Between the linear compensator Gc(z) and the linear A/D, in digital domain, a simple nonlinear gain scheduling block is inserted as shown in Fig.1. A typical characteristic of the gain scheduling block is shown in Fig. 2, and its characteristics are expressed in the following equations.
Power Stage
Gain Scheduling Block
DPWM
GC(z)
A/D
- Vref +
Compensator
Figure 1: Block diagram of a digital controlled PWM converter with gain scheduling
G = α1, a < a1 ⎡ 1⎛ 4 ⎛ a1 ⎞ 2 ⎛ ⎛ a1 ⎞ ⎞ ⎞⎤ ⎢α1 + (α 2 − α1) × ⎜⎜ 2 − arcsin⎜ ⎟ + sin⎜⎜ 2 arcsin⎜ ⎟ ⎟⎟ ⎟⎟⎥ π 2⎝ ⎝a⎠ π ⎝ ⎝ a ⎠ ⎠ ⎠⎥ ⎢ = ⎢ ⎥, a1 < a < a2 a a 1 4 1 ⎛ ⎞ ⎥ ⎢− (α 2 − α1) × × cos(arcsin⎜ ⎟) a π ⎝a⎠ ⎦⎥ ⎣⎢
α3
b2
α2 -a2
-a1
b1 α1 a1 -b1
a2
-b2
Figure 2: Typical input-output characteristics of the gain scheduling block e[n] = f(e) = α1× e, e < a1
⎡ 1⎛ 4 ⎛ a1 ⎞ 2 ⎛ ⎛ a1 ⎞ ⎞ ⎞⎤ ⎢α1 + (α 2 − α1) × ⎜⎜ 2 − arcsin⎜ ⎟ + sin⎜⎜ 2 arcsin⎜ ⎟ ⎟⎟ ⎟⎟⎥ π 2⎝ ⎝a⎠ π ⎝ ⎝ a ⎠ ⎠ ⎠⎥ ⎢ ⎥ ⎢ a a 1 4 1 ⎛ ⎞ ⎥ ⎢− (α 2 − α1) × × cos(arcsin⎜ ⎟) ⎥ ⎢ a π ⎝a⎠ = ⎢ ⎥, a 2 < a ⎢ 1 ⎛⎜ 4 ⎛ a2 ⎞ 2 ⎛ ⎛ a2 ⎞ ⎞ ⎞⎟ ⎥ ⎟ ⎜ ⎢+ (α 3 − α 2) × ⎜ 2 − arcsin⎜ ⎟ + sin⎜ 2 arcsin⎜ ⎟ ⎟ ⎟ ⎥ π 2⎝ ⎝ a ⎠ π ⎝ ⎝ a ⎠⎠⎠ ⎥ ⎢ ⎥ ⎢ a2 4 ⎛ a2 ⎞ ⎥ ⎢− (α 3 − α 2) × × cos(arcsin⎜ ⎟) a π a ⎥⎦ ⎢⎣ ⎝ ⎠
(2.3)
With the above derived nonlinear gains, we can conduct the stability analysis of the digital controlled PWM converters. In the following, we discuss two important examples.
In the above notations, it is assumed that the A/D has good resolution and the quantization effect does not affect the stability.
Example 1: Figure 4 a) shows one practical gain scheduling scheme. The benefit of this scheme is that it provides no sensitivity around the steady state point, thus noise will have little effect in the regular operation. In this case, α 1 = 0, α 2 = α 3
= b1 + α 2 × (e − a1), a 2 ≥ e ≥ a1
= - b1 + α 2 × (e + a1),−a1 ≥ e ≥ −a 2 = b2 + α 3 × (e − a 2), e ≥ a 2
= - b2 + α 3 × (e + a 2 ), e ≤ −a 2
ANALYSIS OF NONLINEAR GAIN SCHEDULING
When the digital control loop contains nonlinear component, a simple way to study its effect on the loop stability is using describing function [10]. The describing function method is illustrated in Figure 3. With sinusoidal input to the nonlinear component as: x(t ) = a sin(ωt ) , the Fourier expansion of the output y(t) is y (t ) = b0 + b1 sin(ωt ) + b2 sin( 2ωt ) + L , the gain G of the nonlinear components can be found as b G= 1 . a This gain could be amplitude or frequency dependent. Applying the describing function method to the nonlinear gain characteristics shown in Figure 2, one could derive the following interesting gain factors.
α2 -a1 a1
(a) Gain vs Amplitude 1.2 1 0.8 gain
III.
0.6 0.4 0.2
x(t)
Nonlinear Block
Figure 3: Describing function method
y(t)
0 0
20
40
60
80
100
a/a1
(b) Figure 4 (a) Gain scheduling scheme (b) Gain through the A/D The gain through the A/D can be simplified as:
G = 0, a < a1 ⎡ ⎛ 1⎛ 4 ⎛ a1 ⎞ 2 ⎛ a1 ⎞ ⎞ ⎞⎤ ⎢α 2 × ⎜⎜ 2 − arcsin⎜ ⎟ + sin ⎜⎜ 2 arcsin⎜ ⎟ ⎟⎟ ⎟⎟⎥ π 2⎝ ⎝a⎠ π ⎝ a ⎠ ⎠ ⎠⎥ ⎝ = ⎢⎢ ⎥, a1 < a ⎥ ⎢− α 2 × a1 × 4 cos(arcsin⎛⎜ a1 ⎞⎟) a π ⎝a⎠ ⎦⎥ ⎣⎢
Figure 4 b) plots the gain with α 2 = 1 . It can be seen that the gain initially has a small value. When the input signal amplitude increases, the gain increases with a nonlinear relation. The upper limit for the gain through the A/D is 1. Example 2: Another commonly encountered gain scheduling scheme is shown in figure 5 a), which actually models the saturation effect of the A/D. In this gain scheduling scheme, α1 = α 2, α 3 = 0 and the gain in this gain scheduling scheme is:
α1 = 1 . It is clear that this gain has an initial value of 1 and decreases nonlinearly when the amplitude of the input sinusoidal signal increases. IV.
EXPERIMENTAL VERIFICATION
An FPGA system is developed to verify the digital control of DC-DC converters with and without nonlinear gain scheduling. The DC-DC Buck converter power stage parameters are L = 1.4 µH, Cout = 630 µF, Vin = 12V, Vout = 2V, the switching frequency is 500 kHz, and the error A/D has 9 bits with LSB resolution of 0.5mV. The A/D characteristics of the conventional digital control versus with gain scheduling are shown in Figure 6 a) and b), respectively.
2
-a2
-a2
G = α1, a < a1
-a1
a2
1
1 a1
a2
⎡ ⎛ 1⎛ 4 ⎛ a2 ⎞ 2 ⎛ a 2 ⎞ ⎞ ⎞⎤ ⎢α1 + (− α1)× ⎜⎜ 2 − arcsin⎜ ⎟ + sin ⎜⎜ 2 arcsin⎜ ⎟ ⎟⎟ ⎟⎟⎥ 2 π π a ⎝ ⎠ ⎝ a ⎠ ⎠ ⎠⎥ ⎝ ⎝ = ⎢⎢ ⎥, a 2 < a ⎢+ (α1)× a 2 × 4 cos(arcsin⎛⎜ a 2 ⎞⎟) ⎥ ⎢⎣ ⎥⎦ a π ⎝ a ⎠
(a)
(b)
Figure 6 (a) A/D characteristic with conventional scheme (b) A/D characteristic with gain scheduling α1
The gain of the A/D converter with saturation characteristics in Fig. 6 a) can be found from Fig. 5 b). The gain of the A/D converter gain scheduling characteristic in Fig. 6 b) is plotted in Fig. 7. The maximum gain is around 1.92 when the amplitude of the input sinusoidal signal reaches the saturation limit. Based on these gain calculation results, a compensator is designed and implemented for both schemes. 7 ⎞⎛ 31 ⎞ ⎛ ⎜ z − ⎟⎜ z − ⎟ 8 ⎠⎝ 32 ⎠ Gc ( z ) = 1.5 ⎝ z (z − 1)
-a2 a2
(a) Gain vs Amplitude 1.2 1
Gain vs Amplitude 2.5
0.6 0.4
2
0.2
1.5
gain
gain
0.8
0 0
5
10
15
1
20
a/a2
(b) Figure 5 (a) Gain scheduling scheme (b) Gain through the A/D The plot in Figure 5 b) shows the gain of this scheme with
0.5 0 0
5
10
15
20
25
30
35
40
a/a1
Figure 7 Gain of A/D characteristics with gain scheduling as in figure 6 (b) with a1 = 8 mV, a2 = 128 mV
(a)
However, for converters with a right half plane zero (RHZ), such as Boost and Buck-Boost converters, if the compensator is not properly designed, decreasing the gain (due to the nonlinear zero bin or saturation effect) may actually cause a stability problem. To illustrate this effect, the following examples on Boost converters are designed and illustrated. The boost converter power stage parameters are: L = 5 µH, C = 60 µF, Vin = 5V, Vout = 10V, the switching frequency is 500 kHz, the load resistance is 11.6 Ω. The power stage control to output transfer function is: s 1− Vout ωz G vd ( s ) = , 2 1− D ⎛ s ⎞ s ⎟ 1+ +⎜ ω 0 Q ⎜⎝ ω 0 ⎟⎠ where (1 − D )2 R , Q = (1 − D) C 1− D f0 = , fz = 2πL L 2π LC Based on the transfer function, the following digital controller is designed, (z − 0.954)(z − 0.766) G c ( z ) = 6.03 z (z − 1) Figure 9 shows the Bode plot of the designed open loop transfer function.
(b) Figure 8 Load transient responses of Buck converter with A/D characteristic in Fig. 6 a) (a) and in Fig. 6 b) (b) Under this compensator, the digital controlled PWM Buck converter in Fig.1 has the load transient responses shown in Fig. 8. It is seen that for the same 5A load transient, the output undershoot is around 50mV with conventional digital control scheme, and the output undershoot is around 30mV when the nonlinear gain scheduling is applied. V.
DISCUSSIONS
From the analysis in Section III, the gain through the A/D can be very small if there is a zero error bin or saturation effects on the A/D. The maximum gain through the A/D is less than the maximum slope in the gain scheduling method. Practically, the zero error bin and saturation effects always exist because of the resolution of the A/D and the existence of the saturation on the A/D and DPWM. So when design a digital compensator for the power stage, it has to be kept in mind that the gain could be significantly smaller than the designed value because of the above mentioned nonlinear effects. For buck converters, small gain does not introduce stability problems. The gain scheduling method enables a slow response around the steady state point, to make the closed loop less sensitive to noise; while provides large corrective action in big load transient responses as illustrated in the experimental verification in Section IV.
Figure 9 Bode plot of the targeted boost converter design From the Bode plot, it can be seen that when the loop gain is reduced, without changing the compensator poles and zeroes, there is an area that the system may become unstable. Assume that the gain of the digital controller is reduced due to the nonlinear zero error bin or saturation effect in the A/D (z − 0.954)(z − 0.766) , Gc ( z ) = 0.121 z (z − 1) Figure 10 shows the Bode plot of the system with reduced gain. Figure 11 shows the output voltage and the duty command waveforms before and after the saturation block in simulation with Simulink. Clearly, the system is not stable.
Figure 10 Bode plot of a digital controlled boost converter with reduced gain
Figure 12 Bode plot of a digital controlled boost converter with improved compensator design
Figure 11 Simulated output voltage and duty command waveforms before and after saturation block In order to solve the stability problem caused by the smaller gain introduced by the nonlinear effects mentioned above, another compensator with zero position adjustment is designed with transfer function (z − 0.989)(z − 0.901) . G c ( z ) = 6.03 z (z − 1) The Bode plot of the system is shown in Figure 12. With this compensator, the system is clearly stable with reduced gain. Figure 13 shows the output voltage and duty command waveforms in simulation with Simulink. In Buck converters, such problem may not exist. However, the application of this gain scheduling method is not without limitation. The maximum crossover frequency is limited by the accuracy of the average model. At the same time, overshoot requirement and delays in the loop constraint the minimum phase margin that should be obtained with maximum gain achievable through the nonlinear effects described in the previous sections.
Figure 13 Simulated output voltage and duty command waveforms with improved compensator design VI.
CONCLUSIONS
In digital controlled PWM converters, nonlinear gain scheduling could be conveniently realized and implemented, e.g. right after the A/D converter. Several typical gain scheduling schemes are analyzed with describing function method and the associated gains are derived and provided. The varied nonlinear gain should be considered in digital compensator design. Experimental results on an FPGA system with Buck converter showed that the system transient response can be improved via nonlinear gain scheduling method. However, caution should be paid in applying gain scheduling method to Boost and Buck-Boost converters. It is shown via Simulink simulation that the system stability may change with gain variation in these converters. It is required to guarantee the system stability not only with normal gain, but also with reduced gain.
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