A Single FPGA Filter-Based Multipath Fading ... - Semantic Scholar
A SINGLE FPGA FILTER-BASED MULTIPATH FADING EMULATOR Saeed Fouladi Fard, Amirhossein Alimohammad
Bruce Cockburn, Christian Schlegel
Ukalta Engineering, 4344 Enterprise Square 10230 Jasper Ave, Edmonton, AB, T5J 4P6, Canada Email: {saeed, amir}@ukalta.com
Department of Electrical and Computer Engineering University of Alberta, Edmonton, AB, T6G 2V4, Canada Email: {cockburn, schlegel}@ece.ualberta.ca
Abstract—Emulation of fading channels is a key step in the design and verification of wireless communication systems. Testing wireless transceivers with actual fading channels is inconvenient due to unrepeatable and uncontrollable channel conditions. In this paper we present a compact field-programmable gate array (FPGA) implementation for a circuit that generates temporallycorrelated fading variates for emulating multipath fading radio channels. The implemented fading emulator is flexible enough to model different propagation scenarios accurately and is compact enough that it can be implemented on the same FPGA with the design under test (DUT) for greater emulation efficiency and speed-up. Several streams of Rayleigh or Rician fading variates are generated by passing independent samples of Gaussian noise through spectrum shaping filters. The new baseband emulator is fully parameterizable and can emulate a wide variety of single and multiple antenna scenarios.
I. M OTIVATION AND BACKGROUND Mobile radio channel emulators are of great importance in the testing and verification of wireless communication systems. Successful design and testing of wireless communication systems requires accurate emulation of the radio propagation environment. Commercially available fading channel emulators are rather bulky and costly. These emulators are standalone units that provide the fading signal in the form of analog or digital samples [1]–[3]. With continuing increases in fieldprogrammable gate array (FPGA) capacity, entire baseband systems can be efficiently mapped onto faster FPGAs for more efficient prototyping, testing, and verification. Larger and faster FPGAs can also permit the integration of a channel emulator along with receiver noise simulator and signal processing blocks for rapid and cost-effective prototyping and design verification. Our goal is to design a compact and accurate fading emulator that can be used for cost-effective and flexible testing and verification of a wide variety of single and multiple antenna systems. Our fading emulator needs to be small enough to be integrated with the rest of the communication system on a single FPGA. In addition, we need to keep our design flexible enough to support the emulation of different fading characteristics ranging from simple Rayleigh and Rician channels to more complicated 802.11n scenarios. Different approaches have been proposed over the past four decades for modeling and simulating mobile radio channels. There are two major techniques for generating fading samples.
Jakes’ model [4] simulates Rayleigh fading by superimposing a sufficient number of sinusoidal waves of appropriate amplitude, frequency, and phase. Although sum-of-sinusoid fading simulators are straightforward to implement, the statistical accuracy of this method has been found wanting [5], [6]. In the second major technique, called filter-based, the fading variates are generated by passing uncorrelated samples of a zero-mean Gaussian process through a spectrum shaping filter (SSF). Compared to the sum-of-sinusoids method, the filterbased technique can be used to accurately simulate a broad range of statistical properties, e.g., generating fading samples for the 802.11n channel model [7]. Until recently, most of the hardware fading simulators have been implemented using digital signal processors [8]. Different hardware designs have been reported in the literature [9]–[16]. Despite its inaccuracies, (see [5], [6]) the sum-of-sinusoids method has been widely used due to its simplicity and efficient implementation [10]–[13], [16]. Because of its sensitivity to quantization errors, using the filter-based technique can be challenging. The fading simulator proposed in [14] is implemented on a hybrid DSP-FPGA platform where the power spectral density of fading samples is roughly approximated with a type-I Chebyshev filter. The authors of [9] used a recursive filter with fixed coefficients in their implementation which limits its flexibility. In addition, due to high-level design, the fading simulator in [9] is inefficiently mapped onto hardware (only two paths could be fitted on a virtex-4 XC4VSX35 FPGA). In this paper, we propose a hardware structure for emulating multipath (i.e., frequency-selective) and multiple-antenna fading in the baseband. The new design is modular, fully parameterizable, and can be customized to generate a wide variety of sample rates and fading characteristics. A new processor block is described for efficiently implementing multiple infinite impulse response (IIR) filters. Also, a compact and parameterizable interpolator is introduced that can up-sample and filter the fading samples for different output rates. In addition, elastic buffers are utilized in our design to facilitate interfacing between different clock domains. The rest of this paper is organized as follows. Section II presents the fading model, simulation structure and filter design procedure. The hardware implementation is detailed in Section III. Simulation and implementation results are
978-1-4244-4148-8/09/$25.00 ©2009 This full text paper was peer reviewed at the direction of IEEE Communications Society subject matter experts for publication in the IEEE "GLOBECOM" 2009 proceedings.
presented in Section IV and Section V makes some concluding remarks.
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Multipath propagation is the situation where the received signal contains different faded copies of the transmitted signal. The effect of the multipath fading on the baseband signal can be modeled with a time-variant linear system with the following impulse response [17] Np −1
α(τ ; t) =
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μn |cn (t)| ej∠cn (t) δ(τ − τn (t)),
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where Np is the number of independent paths, μn is the average attenuation of the n-th path, and cn (t) and τn (t) denote the complex gain and delay of the n-th path. In an isotropic scattering Rayleigh fading channel, the path gains are modeled using a unit-variance zero-mean complex Gaussian process cn (t) = cIn (t) + jcQ n (t) [18] with the power spectral density (PSD) function √ 12 2 if |f | < ζn , Scn (f ) = π ζn −f (2) 0 otherwise, where ζn is the maximum Doppler frequency of the n-th path. In this model cIn (t) and cQ n (t) are independent stochastic processes that have the same autocorrelation function (ACF) Rcn (τ ) = Jo (2πζn τ ), where Jo (·) is the zeroth-order Bessel function of the first kind [4]. Assuming the above model, the √ level-crossing rate (LCR) of |cn (t)| is given by 2 NRn (λ) = 2πζn λe−λ [19], where λ = Rth /Rrms is the specified threshold level Rth normalized to the rms value of the magnitude. To simulate a Rayleigh fading channel we need to generate a suitable sequence of complex path gains {cn (t)} and then superimpose delayed replicas of the transmitted samples with the given delays {τn (t)} and path attenuations {μn }. A common way to generate the path gains with the desired statistics is to pass a stream of independent Gaussian samples through a SSF. For the case of Rayleigh fading, SSF must have a magnitude response equal to the square root of the magnitude of the Jakes’ spectrum given in (2). When a line-of-sight (LOS) or strong specular component is present, the channel is called Rician. In Rician propagation, the nonzero mean complex path gain can be divided into two components. The first component is the LOS part with normalized average power |βn |2 ≤ 1 and the second component is the random scattering part with average power 1 − |βn |2 . For the n-th path (possibly between an antenna pair), the Rician factor |βn |2 Kn is defined as Kn 1−|β 2 . For purely Rayleigh fading n| channels, βn = 0 and hence Kn = 0; for Rician channels |βn | > 0 and hence Kn > 0. To simulate Rician propagation, with the PSD given in (2) and then one can generate {cn (t)} attenuate the samples by 1 − |βn |2 to obtain the power of the random scattering component. The total complex path gain can then be obtained by adding in a scaled LOS component.
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In the design of the SSF, since no constraints are imposed on the phase response, we choose to use infinite impulse response (IIR) filters since they are typically much smaller than their finite impulse response (FIR) counterparts. However, we must ensure that the designed SSF is stable. We approximate the desired magnitude response of the l-th SSF with an IIR filter of order 2NQ [20]. The magnitude response of the SSF is jω
Hl (e ) =
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1 + b1,l,q e−jω + b2,l,q e−j2ω gl,q × 1 + a1,l,q e−jω + a2,l,q e−j2ω
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which is equivalent to the magnitude response of NQ cascaded second-order canonic sections (biquads). In (3), b1,l,q , b2,l,q , a1,l,q and a2,l,q denote the coefficients and gl,q denotes the real-valued scaling factor of the q-th biquad of the l-th SSF. For a typical wireless communication scenario, the Doppler frequency ζn is significantly lower than the signal sample rate Fs . This allows us to design the SSF at a much lower sample rate thereby reducing the required computations. The resulting low-rate signal can then be interpolated to achieve the desired output sample rate. Figure 1 shows the block diagram of our fading emulator. Noise samples are generated by a Gaussian noise generator (GNG) at F1 samples per second and sent to the SSF. The SSF output is then up-sampled I1 times and passed to the elliptic interpolation lowpass filter (EILPF) generating F2 = I1 × F1 samples per second. The samples are further up-sampled and interpolated several times using fading-specific interpolation lowpass filters (SILPF) to obtain the desired output sample rate Fs . The structure of the SILPF will be discussed in more detail later. A. Filter Design Without loss of generality, we base the filter design for the random scattering component of the n-th path assuming the maximum Doppler frequency fD = ζn . We then design the SSF at a sampling frequency F1 , where 4fD < F1 ≤ 8fD . Choosing F1 in this range satisfies the minimum Nyquist rate while keeping the computational complexity low. In addition, we have the opportunity to exploit power-of-2 interpolation factors to further reduce the hardware complexity and simplify the filter design. 1/2 2 − Given the desired frequency response Sc (f ) = (π 2 (fD f 2 ))−1/4 , |f | < fD , we can find the filter coefficients using the MATLAB function iirlpnorm, which calculates the optimal values by minimizing the p-norm. After the initial filter design, the filter is tested with fixed-point variables, and scaling factors gl,q are determined that sufficiently limit the magnitude of the generated samples to keep them within the representable range.
978-1-4244-4148-8/09/$25.00 ©2009 This full text paper was peer reviewed at the direction of IEEE Communications Society subject matter experts for publication in the IEEE "GLOBECOM" 2009 proceedings.
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The generated samples from the SSF are upsampled I1 = 16 times and passed through the EILPF. Since the SILPF stages are designed to operate on narrow-band signals, the first interpolation stage is positioned prior to the SILPF stages. Then the samples are passed through Tg successive SILPFs. The i-th SILPF interpolates the signal 2ki times.
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Architecture of the biquad processor.
B. Multiplication-Free Filters The generated data stream is interpolated up to the target output sample rate Fs . Let P denote the integer upsampling factor. Interpolation of the signal {x[n]} is performed by inserting P − 1 zeros between each pair of successive samples of {x[n]} and then passing the resulting stream through a lowpass filter with cut-off frequency π/P radian/sec. Lowpass filtering is normally done using conventional FIR or IIR filters, but it is more efficient if the interpolation filters are realized with multiplication-free filters (see [21] for example). For example for fading emulation, when fD /Fi 1 we use a multiplication-free filter with frequency response l 1 − e−jωP z DPlz (ejω ) = , lz ≥ 1 (4) P − P e−jω where lz is the number of cascaded stages. III. H ARDWARE I MPLEMENTATION Figure 2 shows a block diagram of the implemented fourpath fading emulator. It can generate Np = 4 independent fading processes with Nf = 4 filters with different correlation properties. The multiple processes can be used to model, for example, frequency-selective channels or fading channels in multiple-input multiple-output (MIMO) systems. The generated Gaussian samples are passed to the first shared filter processor, which runs the designed SSF from (3) in four parallel and independent threads. Each thread of data is then upsampled 16 times and passed through an EILPF that is implemented using another shared filter processor. Each IIR filter processor is capable of processing eight independent streams of input data. The maximum order of each IIR filter is 16 (eight biquads per filter). After the EILPF, the data streams are passed to interpolation filters (IFs). Each IF includes four configurable SILPFs that are interconnected with elastic buffers. Each IF also contains a terminal elastic buffer for interfacing to external hardware. We will explain the hardware structure of the different subsystems in the following subsections.
A. Biquad Processor We found it to be useful to re-use an optimized fixed-point processor to perform the operations of the SSF and the EILPF. Figure 3 shows the architecture of our biquad processor. The main datapath element is a multiplier-accumulator (MAC) that multiplies the in-phase and quadrature data components by real-valued coefficients. The control sequence for running the cascaded biquads is quite straightforward. However, when emulating multiple paths, where each path could have different filter specifications and different sample rates, flexible implementation of the control unit becomes challenging. In addition, the fading emulator might have to generate samples for more than one external system with different clocks. To improve the robustness of our biquad processor, two flags are assigned to every thread of cascaded biquads (i.e., for each individual path labeled in- i and out- j in Fig. 3). These flags govern the data flow through each thread. For example, for the i-th thread (path), if in- i is high, then input data is ready to be read. Also, if out- i is high, then data can be written to the next stage. For each thread, the biquad processor keeps executing the biquads unless either of the input or output flags is de-asserted. To prevent the overwriting of unprocessed data, the biquads in each thread are scheduled to be executed from the last biquad to the first. To generate each Gaussian variate, we simply added 12 uniformly distributed random variables ui ∈ [−0.5, 0.5). Since the fading samples are strongly correlated, generating the uniform samples with a simple linear feedback shift register (LFSR) structure does not change the correlation properties significantly. Also, from the central limit theorem, filtering the input process with the SSF and EILPF will help to improve the Gaussian distribution of the fading samples. However for greater accuracy, we can always substitute a high quality Gaussian noise generator, such as the one proposed in [22]. B. SILPF Figure 4 shows the structure of our proposed SILPF. This structure is a parametric interpolator that uses the
978-1-4244-4148-8/09/$25.00 ©2009 This full text paper was peer reviewed at the direction of IEEE Communications Society subject matter experts for publication in the IEEE "GLOBECOM" 2009 proceedings.
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multiplication-free filter DP2 (ejω ). With this datapath we can up-sample the input signal and perform interpolation filtering. The interpolation factor P is passed to this circuit as a parameter to specify the length of the shift register. After interpolation the signal amplitude can be multiplied by 2−k (shifted to the right), where k is another input parameter passed to this circuit. This multiplication can be used to adjust the signal power. In our design, consecutive blocks are interconnected with elastic buffers that operate in two modes. When operating in the handShaking mode, consecutive blocks are informed about the buffer overflow, or underflow conditions. This mode is more appropriate when all parts operate in the same clock domain. The other mode of the elastic buffers is Continues in which the elastic buffer make the decision to insert (delete) certain samples into (from) the buffer when facing underflow (overflow) conditions. This mode is more suitable for interconnecting digital blocks that operate over different clock domains. It can be shown that the error in the PSD of the resulting fading samples is negligible for small frequency mismatches. C. Multipath Delay For accurate emulation of multipath propagation, fractional delay structures need to be employed. One of the most widely used structures is the Farrow interpolator which is mostly used for accurate timing and synchronization. We implemented the Farrow interpolator with third order polynomial approximation of fractional delay. Approximating fractional path delay to the closest integer delays (tapped-delay), however, can result in significant reduction in hardware complexity. IV. R ESULTS To ensure accuracy, we measured the statistical properties of the bit-true fixed-point software model of our FPGA implementation. Figure 5 shows the autocorrelation and crosscorrelation for the real and imaginary parts of the generated fading process. The Doppler frequency is set to fD = 0.6 Hz and the sample rate is Fs = 2.5 million samples per second for each channel. The theoretical functions are plotted as well for reference. This figure confirms a close match between the desired response and the generated results over up to 60 seconds. In another example we measured the probability density function (pdf) for the amplitude of the generated samples with fD = 200 Hz and Fs = 10 MHz (see Fig. 6 (a)). Note that the measured pdf accurately matches the ideal Rayleigh pdf. The LCR of the generated fading samples in Fig.
Fig. 5. Cross-correlation and autocorrelation between the real and imaginary components of the generated fading process with fD = 0.6 Hz, Fs = 2.5 MHz over 60 seconds. 10
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Fig. 6. (a) Probability density function. The measured and reference pdf are indistinguishable in this figure. (b) Level crossing rate of the generated fading process with fD = 200 Hz and Fs = 10 MHz. In this figure the solid line represents the theoretical reference and the circles are the measured values. TABLE I FPGA I MPLEMENTATION R ESULTS ON D IFFERENT D EVICES Device XCV2000E XC3S1000 XC4VSX35 XCV2000E XC3S1000 XC4VSX35
Number of Paths 4 4 4 8 8 8
18 × 18 MULs 12 (50%) 12 (6%) 12 (50%) 12 (6%)
Max Clock (MHz) 52 62 98.5 52 62 98.5
Number of Slices 5232 (27%) 5149 (67%) 6135 (39%) 7868 (41%) 7108 (92%) 9520 (62%)
6 (b) also shows a good match between theory and generated results (fD = 200 Hz, Fs = 10 MHz). Table I summarizes the FPGA implementation characteristics of four- and eight-path fading emulators on different devices. Note that a four-path fading emulator requires only 39% of the configurable slices of a Xilinx Virtex-4 XC4VSX35 FPGA and can generate up to 4×98.5 million complex fading samples per second. The compactness of our fading emulator allows us to implement a four-path fading emulator along with an accurate Gaussian noise generator (see [22]) on a small FPGA board for testing purposes. We used the Spartan-III FPGA board from Digilent [23], which hosts a Xilinx SpartanIII XC3S1000 FPGA. Figure 7 (a) shows a picture of the Digilent FPGA board along with some other FPGA test boards that were considered. We also implemented a four-path fading emulator on a GVA-290 board [24]. This board hosts two Xilinx VirtexE XCV2000E FPGAs. Figure 7 (b) shows the effect of a threepath fading channel on the transmitted 8-PSK samples. We also measured the bit error rate performance of a 2 × 2 MIMO
978-1-4244-4148-8/09/$25.00 ©2009 This full text paper was peer reviewed at the direction of IEEE Communications Society subject matter experts for publication in the IEEE "GLOBECOM" 2009 proceedings.
channel characteristics. The implementation and emulation results show an accurate match with the theoretical ideal statistics. The emulator is compact enough to fit well within a single FPGA, which should be an important benefit to the rapid prototyping and characterization of wireless systems. R EFERENCES (a)
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Fig. 7. (a) Digilent Spartan-III board and some test boards used for verification of various chips. (b) Oscilloscope output: three-path fading effect on 8-PSK modulated signal. 10
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communication system with our hardware testbed. Figure 8 shows the hardware measured BER of this MIMO system with QAM-modulated symbols. Here fading is uncorrelated over antennas and the Doppler frequency is set to 10 Hz. In the transmitter, information bits are encoded with an extended Golay code and an interleaver of length 16383 is utilized. In the receiver, samples are detected with a maximum-likelihood (ML) detector prior to deinterleaving and decoding. In this hardware, the fading processors are implemented with a 36-bit datapath, fading samples are 16-bits wide and the ML detector is implemented with 10-bit fixed-point samples. Figure 8 shows the uncoded and coded BER performance of this MIMO system. Moreover, 1.5×1010 bits were transmitted to measure each BER point in this measurement. V. C ONCLUSIONS A new computationally-efficient and especially compact hardware emulator for Rayleigh and Rician multipath fading channels was presented. Different streams of fading samples are generated by passing Gaussian noise samples through a spectrum shaping filter. The generated samples are interpolated to achieve the desired sample rate. Elastic buffers are utilized to interconnect different parts of this fading emulator to simplify the filter cascade design and to simplify interfacing with external hardware. The emulator is fully parameterizable in software and can emulate a wide variety of different fading
[1] Wireless Channel Emulator, Spirent Communications, 2006. [2] Baseband Studio for Fading, Agilent Technologies Inc., 2005. [3] Baseband Fading Simulator ABFS, Reduced costs through baseband simulation, Rohde & Schwarz, 1999. [4] W. C. Jakes, Microwave Mobile Communications, Piscataway, NJ: WileyIEEE Press, 1994. [5] M. F. Pop and N. C. Beaulieu, “Limitations of sum-of-sinusoids fading channel simulators,” IEEE Transactions on Communications, vol. 49, pp. 699-708, 2001. [6] Y. R. Zheng and C. Xiao, “Improved models for the generation of multiple uncorrelated Rayleigh fading waveforms,” IEEE Communications Letters, vol. 6, pp. 256-258, 2002. [7] V. Erceg et al., “IEEE P802.11 Wireless LANs: TGn Channel Models,” IEEE 802.11-03/940r4, May 2004. [8] M. Kahrs, and C. Zimmer, “Digital signal processing in a real-time propagation simulator,” IEEE Transactions on Instrumentation and Measurements., vol. 55, no. 1, pp. 197-205, 2006. [9] J. K. Hwang et al., “Fast FPGA prototyping of a multipath fading channel emulator via high-level design,” in Proceedings of the International Symposium on Communications and Information Technologies (ISCIT’07), pp. 168-171, 2007. [10] M. Cui, H. Murata, and K. Araki, “FPGA implementation of 4 × 4 MIMO test-bed for spatial multiplexing systems,” in Proceedings of the IEEE International Symposium on Personal, Indoor and Mobile Radio Communications (PIMRC’04) , vol. 4, pp. 3045-3048, 2004. [11] G. N. Rao, R. Bhattacharjee, and S. Nandi, “VLSI architecture for Rayleigh and Rician fading generators,” in Proceedings of the TENCON’04 IEEE Region 10 Conference, vol. 3, pp. 121-124, 2004. [12] C. C. Fu et al., “A real-time digital baseband channel emulation system for OFDM communications,” in Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems (APCCAS’06), pp. 984-987, 2006. [13] B. Surendra et al., “A prototype architecture for the accurate modeling of Rayleigh fading waveforms,” in Proceedings of the Fourth Pacific Rim Conference, vol. 2, pp. 1101-1105, 2003. [14] J. R. Papenfuss and M. A. Wickert, “Implementation of a real-time, frequency selective, RF channel simulator using a hybrid DSP-FPGA architecture,” in Proceedings of the IEEE Radio and Wireless Conference (RAWCON’00) , pp. 135-138, 2000. [15] M. Kahrs and C. Zimmer, “High speed signal processing in a programmable propagation simulator,” in Proceedings of the IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP’93), vol. 3, pp. 21-24, 1993. [16] A. Alimohammad, S. Fouladi Fard, B. Cockburn, and C. Schlegel., “An improved SOS-based fading channel emulator”, in Proceedings of the IEEE Vehicular Technology Conference (VTC’07), pp. 931-935, 2007. [17] G. L. St¨uber, Principles of Mobile Communication, New York,: Kluwer Academic Publishers, 2001. [18] P. A. Bello, “Characterization of randomly time-invariant linear channels,” IEEE Transactions on Communications, vol. CS-11, pp. 360-393, 1963. [19] T. S. Rappaport, Wireless Communications: Principles and Practice, Prentice Hall, 2002. [20] K. Steiglitz. “Computer-aided design of recursive digital filters,” IEEE Transactions on Audio and Electroacoustics, vol. 18, pp. 123-129, June 1970. [21] T. Saramaki and J. Yli-Kaakinen, “A novel systematic approach for synthesizing multiplication-free highly-selective FIR half-band decimators and interpolators,” In Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems (APCCAS’06), pp. 920-923, 2006. [22] A. Alimohammad, S. Fouladi Fard, B. Cockburn, and C. Schlegel, “A compact and accurate Gaussian variate generator,” IEEE Transactions on Very-Large System Integration (TVLSI), vol. 16, no. 5, pp. 517-527, 2008. [23] Xilinx, “Spartan-III starter kit board user guide”, May 2005. [24] GV & Associates, “GVA-290 Xilinx VirtexE Hardware Accelerator.”
978-1-4244-4148-8/09/$25.00 ©2009 This full text paper was peer reviewed at the direction of IEEE Communications Society subject matter experts for publication in the IEEE "GLOBECOM" 2009 proceedings.
Bruce Cockburn, Christian Schlegel
Ukalta Engineering, 4344 Enterprise Square 10230 Jasper Ave, Edmonton, AB, T5J 4P6, Canada Email: {saeed, amir}@ukalta.com
Department of Electrical and Computer Engineering University of Alberta, Edmonton, AB, T6G 2V4, Canada Email: {cockburn, schlegel}@ece.ualberta.ca
Abstract—Emulation of fading channels is a key step in the design and verification of wireless communication systems. Testing wireless transceivers with actual fading channels is inconvenient due to unrepeatable and uncontrollable channel conditions. In this paper we present a compact field-programmable gate array (FPGA) implementation for a circuit that generates temporallycorrelated fading variates for emulating multipath fading radio channels. The implemented fading emulator is flexible enough to model different propagation scenarios accurately and is compact enough that it can be implemented on the same FPGA with the design under test (DUT) for greater emulation efficiency and speed-up. Several streams of Rayleigh or Rician fading variates are generated by passing independent samples of Gaussian noise through spectrum shaping filters. The new baseband emulator is fully parameterizable and can emulate a wide variety of single and multiple antenna scenarios.
I. M OTIVATION AND BACKGROUND Mobile radio channel emulators are of great importance in the testing and verification of wireless communication systems. Successful design and testing of wireless communication systems requires accurate emulation of the radio propagation environment. Commercially available fading channel emulators are rather bulky and costly. These emulators are standalone units that provide the fading signal in the form of analog or digital samples [1]–[3]. With continuing increases in fieldprogrammable gate array (FPGA) capacity, entire baseband systems can be efficiently mapped onto faster FPGAs for more efficient prototyping, testing, and verification. Larger and faster FPGAs can also permit the integration of a channel emulator along with receiver noise simulator and signal processing blocks for rapid and cost-effective prototyping and design verification. Our goal is to design a compact and accurate fading emulator that can be used for cost-effective and flexible testing and verification of a wide variety of single and multiple antenna systems. Our fading emulator needs to be small enough to be integrated with the rest of the communication system on a single FPGA. In addition, we need to keep our design flexible enough to support the emulation of different fading characteristics ranging from simple Rayleigh and Rician channels to more complicated 802.11n scenarios. Different approaches have been proposed over the past four decades for modeling and simulating mobile radio channels. There are two major techniques for generating fading samples.
Jakes’ model [4] simulates Rayleigh fading by superimposing a sufficient number of sinusoidal waves of appropriate amplitude, frequency, and phase. Although sum-of-sinusoid fading simulators are straightforward to implement, the statistical accuracy of this method has been found wanting [5], [6]. In the second major technique, called filter-based, the fading variates are generated by passing uncorrelated samples of a zero-mean Gaussian process through a spectrum shaping filter (SSF). Compared to the sum-of-sinusoids method, the filterbased technique can be used to accurately simulate a broad range of statistical properties, e.g., generating fading samples for the 802.11n channel model [7]. Until recently, most of the hardware fading simulators have been implemented using digital signal processors [8]. Different hardware designs have been reported in the literature [9]–[16]. Despite its inaccuracies, (see [5], [6]) the sum-of-sinusoids method has been widely used due to its simplicity and efficient implementation [10]–[13], [16]. Because of its sensitivity to quantization errors, using the filter-based technique can be challenging. The fading simulator proposed in [14] is implemented on a hybrid DSP-FPGA platform where the power spectral density of fading samples is roughly approximated with a type-I Chebyshev filter. The authors of [9] used a recursive filter with fixed coefficients in their implementation which limits its flexibility. In addition, due to high-level design, the fading simulator in [9] is inefficiently mapped onto hardware (only two paths could be fitted on a virtex-4 XC4VSX35 FPGA). In this paper, we propose a hardware structure for emulating multipath (i.e., frequency-selective) and multiple-antenna fading in the baseband. The new design is modular, fully parameterizable, and can be customized to generate a wide variety of sample rates and fading characteristics. A new processor block is described for efficiently implementing multiple infinite impulse response (IIR) filters. Also, a compact and parameterizable interpolator is introduced that can up-sample and filter the fading samples for different output rates. In addition, elastic buffers are utilized in our design to facilitate interfacing between different clock domains. The rest of this paper is organized as follows. Section II presents the fading model, simulation structure and filter design procedure. The hardware implementation is detailed in Section III. Simulation and implementation results are
978-1-4244-4148-8/09/$25.00 ©2009 This full text paper was peer reviewed at the direction of IEEE Communications Society subject matter experts for publication in the IEEE "GLOBECOM" 2009 proceedings.
presented in Section IV and Section V makes some concluding remarks.
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Multipath propagation is the situation where the received signal contains different faded copies of the transmitted signal. The effect of the multipath fading on the baseband signal can be modeled with a time-variant linear system with the following impulse response [17] Np −1
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where Np is the number of independent paths, μn is the average attenuation of the n-th path, and cn (t) and τn (t) denote the complex gain and delay of the n-th path. In an isotropic scattering Rayleigh fading channel, the path gains are modeled using a unit-variance zero-mean complex Gaussian process cn (t) = cIn (t) + jcQ n (t) [18] with the power spectral density (PSD) function √ 12 2 if |f | < ζn , Scn (f ) = π ζn −f (2) 0 otherwise, where ζn is the maximum Doppler frequency of the n-th path. In this model cIn (t) and cQ n (t) are independent stochastic processes that have the same autocorrelation function (ACF) Rcn (τ ) = Jo (2πζn τ ), where Jo (·) is the zeroth-order Bessel function of the first kind [4]. Assuming the above model, the √ level-crossing rate (LCR) of |cn (t)| is given by 2 NRn (λ) = 2πζn λe−λ [19], where λ = Rth /Rrms is the specified threshold level Rth normalized to the rms value of the magnitude. To simulate a Rayleigh fading channel we need to generate a suitable sequence of complex path gains {cn (t)} and then superimpose delayed replicas of the transmitted samples with the given delays {τn (t)} and path attenuations {μn }. A common way to generate the path gains with the desired statistics is to pass a stream of independent Gaussian samples through a SSF. For the case of Rayleigh fading, SSF must have a magnitude response equal to the square root of the magnitude of the Jakes’ spectrum given in (2). When a line-of-sight (LOS) or strong specular component is present, the channel is called Rician. In Rician propagation, the nonzero mean complex path gain can be divided into two components. The first component is the LOS part with normalized average power |βn |2 ≤ 1 and the second component is the random scattering part with average power 1 − |βn |2 . For the n-th path (possibly between an antenna pair), the Rician factor |βn |2 Kn is defined as Kn 1−|β 2 . For purely Rayleigh fading n| channels, βn = 0 and hence Kn = 0; for Rician channels |βn | > 0 and hence Kn > 0. To simulate Rician propagation, with the PSD given in (2) and then one can generate {cn (t)} attenuate the samples by 1 − |βn |2 to obtain the power of the random scattering component. The total complex path gain can then be obtained by adding in a scaled LOS component.
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In the design of the SSF, since no constraints are imposed on the phase response, we choose to use infinite impulse response (IIR) filters since they are typically much smaller than their finite impulse response (FIR) counterparts. However, we must ensure that the designed SSF is stable. We approximate the desired magnitude response of the l-th SSF with an IIR filter of order 2NQ [20]. The magnitude response of the SSF is jω
Hl (e ) =
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which is equivalent to the magnitude response of NQ cascaded second-order canonic sections (biquads). In (3), b1,l,q , b2,l,q , a1,l,q and a2,l,q denote the coefficients and gl,q denotes the real-valued scaling factor of the q-th biquad of the l-th SSF. For a typical wireless communication scenario, the Doppler frequency ζn is significantly lower than the signal sample rate Fs . This allows us to design the SSF at a much lower sample rate thereby reducing the required computations. The resulting low-rate signal can then be interpolated to achieve the desired output sample rate. Figure 1 shows the block diagram of our fading emulator. Noise samples are generated by a Gaussian noise generator (GNG) at F1 samples per second and sent to the SSF. The SSF output is then up-sampled I1 times and passed to the elliptic interpolation lowpass filter (EILPF) generating F2 = I1 × F1 samples per second. The samples are further up-sampled and interpolated several times using fading-specific interpolation lowpass filters (SILPF) to obtain the desired output sample rate Fs . The structure of the SILPF will be discussed in more detail later. A. Filter Design Without loss of generality, we base the filter design for the random scattering component of the n-th path assuming the maximum Doppler frequency fD = ζn . We then design the SSF at a sampling frequency F1 , where 4fD < F1 ≤ 8fD . Choosing F1 in this range satisfies the minimum Nyquist rate while keeping the computational complexity low. In addition, we have the opportunity to exploit power-of-2 interpolation factors to further reduce the hardware complexity and simplify the filter design. 1/2 2 − Given the desired frequency response Sc (f ) = (π 2 (fD f 2 ))−1/4 , |f | < fD , we can find the filter coefficients using the MATLAB function iirlpnorm, which calculates the optimal values by minimizing the p-norm. After the initial filter design, the filter is tested with fixed-point variables, and scaling factors gl,q are determined that sufficiently limit the magnitude of the generated samples to keep them within the representable range.
978-1-4244-4148-8/09/$25.00 ©2009 This full text paper was peer reviewed at the direction of IEEE Communications Society subject matter experts for publication in the IEEE "GLOBECOM" 2009 proceedings.
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Block diagram of the implemented four-path fading emulator. handshaking
The generated samples from the SSF are upsampled I1 = 16 times and passed through the EILPF. Since the SILPF stages are designed to operate on narrow-band signals, the first interpolation stage is positioned prior to the SILPF stages. Then the samples are passed through Tg successive SILPFs. The i-th SILPF interpolates the signal 2ki times.
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Architecture of the biquad processor.
B. Multiplication-Free Filters The generated data stream is interpolated up to the target output sample rate Fs . Let P denote the integer upsampling factor. Interpolation of the signal {x[n]} is performed by inserting P − 1 zeros between each pair of successive samples of {x[n]} and then passing the resulting stream through a lowpass filter with cut-off frequency π/P radian/sec. Lowpass filtering is normally done using conventional FIR or IIR filters, but it is more efficient if the interpolation filters are realized with multiplication-free filters (see [21] for example). For example for fading emulation, when fD /Fi 1 we use a multiplication-free filter with frequency response l 1 − e−jωP z DPlz (ejω ) = , lz ≥ 1 (4) P − P e−jω where lz is the number of cascaded stages. III. H ARDWARE I MPLEMENTATION Figure 2 shows a block diagram of the implemented fourpath fading emulator. It can generate Np = 4 independent fading processes with Nf = 4 filters with different correlation properties. The multiple processes can be used to model, for example, frequency-selective channels or fading channels in multiple-input multiple-output (MIMO) systems. The generated Gaussian samples are passed to the first shared filter processor, which runs the designed SSF from (3) in four parallel and independent threads. Each thread of data is then upsampled 16 times and passed through an EILPF that is implemented using another shared filter processor. Each IIR filter processor is capable of processing eight independent streams of input data. The maximum order of each IIR filter is 16 (eight biquads per filter). After the EILPF, the data streams are passed to interpolation filters (IFs). Each IF includes four configurable SILPFs that are interconnected with elastic buffers. Each IF also contains a terminal elastic buffer for interfacing to external hardware. We will explain the hardware structure of the different subsystems in the following subsections.
A. Biquad Processor We found it to be useful to re-use an optimized fixed-point processor to perform the operations of the SSF and the EILPF. Figure 3 shows the architecture of our biquad processor. The main datapath element is a multiplier-accumulator (MAC) that multiplies the in-phase and quadrature data components by real-valued coefficients. The control sequence for running the cascaded biquads is quite straightforward. However, when emulating multiple paths, where each path could have different filter specifications and different sample rates, flexible implementation of the control unit becomes challenging. In addition, the fading emulator might have to generate samples for more than one external system with different clocks. To improve the robustness of our biquad processor, two flags are assigned to every thread of cascaded biquads (i.e., for each individual path labeled in- i and out- j in Fig. 3). These flags govern the data flow through each thread. For example, for the i-th thread (path), if in- i is high, then input data is ready to be read. Also, if out- i is high, then data can be written to the next stage. For each thread, the biquad processor keeps executing the biquads unless either of the input or output flags is de-asserted. To prevent the overwriting of unprocessed data, the biquads in each thread are scheduled to be executed from the last biquad to the first. To generate each Gaussian variate, we simply added 12 uniformly distributed random variables ui ∈ [−0.5, 0.5). Since the fading samples are strongly correlated, generating the uniform samples with a simple linear feedback shift register (LFSR) structure does not change the correlation properties significantly. Also, from the central limit theorem, filtering the input process with the SSF and EILPF will help to improve the Gaussian distribution of the fading samples. However for greater accuracy, we can always substitute a high quality Gaussian noise generator, such as the one proposed in [22]. B. SILPF Figure 4 shows the structure of our proposed SILPF. This structure is a parametric interpolator that uses the
978-1-4244-4148-8/09/$25.00 ©2009 This full text paper was peer reviewed at the direction of IEEE Communications Society subject matter experts for publication in the IEEE "GLOBECOM" 2009 proceedings.
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multiplication-free filter DP2 (ejω ). With this datapath we can up-sample the input signal and perform interpolation filtering. The interpolation factor P is passed to this circuit as a parameter to specify the length of the shift register. After interpolation the signal amplitude can be multiplied by 2−k (shifted to the right), where k is another input parameter passed to this circuit. This multiplication can be used to adjust the signal power. In our design, consecutive blocks are interconnected with elastic buffers that operate in two modes. When operating in the handShaking mode, consecutive blocks are informed about the buffer overflow, or underflow conditions. This mode is more appropriate when all parts operate in the same clock domain. The other mode of the elastic buffers is Continues in which the elastic buffer make the decision to insert (delete) certain samples into (from) the buffer when facing underflow (overflow) conditions. This mode is more suitable for interconnecting digital blocks that operate over different clock domains. It can be shown that the error in the PSD of the resulting fading samples is negligible for small frequency mismatches. C. Multipath Delay For accurate emulation of multipath propagation, fractional delay structures need to be employed. One of the most widely used structures is the Farrow interpolator which is mostly used for accurate timing and synchronization. We implemented the Farrow interpolator with third order polynomial approximation of fractional delay. Approximating fractional path delay to the closest integer delays (tapped-delay), however, can result in significant reduction in hardware complexity. IV. R ESULTS To ensure accuracy, we measured the statistical properties of the bit-true fixed-point software model of our FPGA implementation. Figure 5 shows the autocorrelation and crosscorrelation for the real and imaginary parts of the generated fading process. The Doppler frequency is set to fD = 0.6 Hz and the sample rate is Fs = 2.5 million samples per second for each channel. The theoretical functions are plotted as well for reference. This figure confirms a close match between the desired response and the generated results over up to 60 seconds. In another example we measured the probability density function (pdf) for the amplitude of the generated samples with fD = 200 Hz and Fs = 10 MHz (see Fig. 6 (a)). Note that the measured pdf accurately matches the ideal Rayleigh pdf. The LCR of the generated fading samples in Fig.
Fig. 5. Cross-correlation and autocorrelation between the real and imaginary components of the generated fading process with fD = 0.6 Hz, Fs = 2.5 MHz over 60 seconds. 10
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Fig. 6. (a) Probability density function. The measured and reference pdf are indistinguishable in this figure. (b) Level crossing rate of the generated fading process with fD = 200 Hz and Fs = 10 MHz. In this figure the solid line represents the theoretical reference and the circles are the measured values. TABLE I FPGA I MPLEMENTATION R ESULTS ON D IFFERENT D EVICES Device XCV2000E XC3S1000 XC4VSX35 XCV2000E XC3S1000 XC4VSX35
Number of Paths 4 4 4 8 8 8
18 × 18 MULs 12 (50%) 12 (6%) 12 (50%) 12 (6%)
Max Clock (MHz) 52 62 98.5 52 62 98.5
Number of Slices 5232 (27%) 5149 (67%) 6135 (39%) 7868 (41%) 7108 (92%) 9520 (62%)
6 (b) also shows a good match between theory and generated results (fD = 200 Hz, Fs = 10 MHz). Table I summarizes the FPGA implementation characteristics of four- and eight-path fading emulators on different devices. Note that a four-path fading emulator requires only 39% of the configurable slices of a Xilinx Virtex-4 XC4VSX35 FPGA and can generate up to 4×98.5 million complex fading samples per second. The compactness of our fading emulator allows us to implement a four-path fading emulator along with an accurate Gaussian noise generator (see [22]) on a small FPGA board for testing purposes. We used the Spartan-III FPGA board from Digilent [23], which hosts a Xilinx SpartanIII XC3S1000 FPGA. Figure 7 (a) shows a picture of the Digilent FPGA board along with some other FPGA test boards that were considered. We also implemented a four-path fading emulator on a GVA-290 board [24]. This board hosts two Xilinx VirtexE XCV2000E FPGAs. Figure 7 (b) shows the effect of a threepath fading channel on the transmitted 8-PSK samples. We also measured the bit error rate performance of a 2 × 2 MIMO
978-1-4244-4148-8/09/$25.00 ©2009 This full text paper was peer reviewed at the direction of IEEE Communications Society subject matter experts for publication in the IEEE "GLOBECOM" 2009 proceedings.
channel characteristics. The implementation and emulation results show an accurate match with the theoretical ideal statistics. The emulator is compact enough to fit well within a single FPGA, which should be an important benefit to the rapid prototyping and characterization of wireless systems. R EFERENCES (a)
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Fig. 7. (a) Digilent Spartan-III board and some test boards used for verification of various chips. (b) Oscilloscope output: three-path fading effect on 8-PSK modulated signal. 10
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communication system with our hardware testbed. Figure 8 shows the hardware measured BER of this MIMO system with QAM-modulated symbols. Here fading is uncorrelated over antennas and the Doppler frequency is set to 10 Hz. In the transmitter, information bits are encoded with an extended Golay code and an interleaver of length 16383 is utilized. In the receiver, samples are detected with a maximum-likelihood (ML) detector prior to deinterleaving and decoding. In this hardware, the fading processors are implemented with a 36-bit datapath, fading samples are 16-bits wide and the ML detector is implemented with 10-bit fixed-point samples. Figure 8 shows the uncoded and coded BER performance of this MIMO system. Moreover, 1.5×1010 bits were transmitted to measure each BER point in this measurement. V. C ONCLUSIONS A new computationally-efficient and especially compact hardware emulator for Rayleigh and Rician multipath fading channels was presented. Different streams of fading samples are generated by passing Gaussian noise samples through a spectrum shaping filter. The generated samples are interpolated to achieve the desired sample rate. Elastic buffers are utilized to interconnect different parts of this fading emulator to simplify the filter cascade design and to simplify interfacing with external hardware. The emulator is fully parameterizable in software and can emulate a wide variety of different fading
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