A Two-Stage Capacitive-Feedback Differencing Amplifier for Temporal ...
A Two-Stage Capacitive-Feedback Differencing Amplifier for Temporal Contrast IR Sensors Christoph Posch, Daniel Matolin, Rainer Wohlgenannt Austrian Research Centers GmbH - ARC, Vienna, Austria Abstract—This paper presents a small-area, ultra low-power, low-mismatch differencing amplifier for use in transient pixels of micro-bolometer based temporal contrast IR sensors. The two-stage capacitive-feedback amplifier works in the sub-threshold domain, has a voltage gain of 46dB, a 3dB bandwidth of about 10kHz and consumes 85nW of static power. The amplifier circuit has been fabricated in a 0.35µm standard CMOS process and consumes less than 2000µm2 of silicon area, enabling a square pixel size of 50µm×50µm.
I.
INTRODUCTION
Over the past few years, a novel species of biologyinspired, or neuromorphic, vision sensors, the so called temporal contrast or optical transient sensor, has been proposed, developed and published [1][2][3]. These devices are gaining increasing popularity and find their way into various fields of machine vision like industrial automation, surveillance and automotive applications [4][5][6]. The pixels employed in these sensors operate autonomously and respond with low latency and high temporal resolution to changes in intensity by generating asynchronous spike events. The events are used to trigger the transmission of data packets containing the respective pixel’s address and are referred to as ‘address-events’ (AE). The output volume of such a data-driven sensor depends on the dynamic contents of the target scene; pixels that are not stimulated visually do not produce output. This leads to a complete suppression of image data redundancy as compared to traditional, frame-based image sensors. Because output bandwidth is automatically dedicated to dynamic parts of the scene, these devices are especially suited for applications in surveillance and motion analysis. Surveillance scenarios often involve low or zero visible illumination of the target scene. Uncooled microbolometers are the sensors of choice when it comes to lowcost infrared (IR) vision solutions, as they are sensitive in the thermal IR spectral range of 8µm – 15µm wavelength and can be readily integrated with CMOS readout circuitry. A temporal contrast IR sensor, based on a microbolometer thermistor array and on asynchronous temporal contrast pixel circuits with their inherent motion detection capability, appears to be a promising solution to certain surveillance and motion detection/analysis problems at low/zero visible light and enables low data rate, low latency machine vision in the thermal IR spectral range. In order to realize a bolometer-based temporal contrast IR sensor, a differencing amplifier for the voltage signal delivered by the bolometer-frontend in response to the small variations in resistance of the bolometer thermistor is called for. The amplifier amplifies only input signal changes irrespective of the exact DC input level and provides a reset mechanism which is used to encode the difference in received IR radiation in the time domain.
Taking into account a time constant of about 10ms for the bolometer element, high bandwidth operation is not required. As the amplifier is to be used in each pixel of a thousands-of-pixels imager array, area and power consumption are of major concern, ruling out the use of OTAs. Furthermore, precautions have to be taken in order to maximize gain matching to reduce fixed pattern noise (FPN). In this paper we present topology, design and characterization of a two-stage capacitive-feedback differencing amplifier for micro-bolometer based temporal contrast IR sensor pixels. The pixel circuit has been fabricated in a 0.35µm standard CMOS process and has been tested and characterized. Design specifications have been met by the chosen circuit topology. II.
ELECTRICAL CHARACTERISTICS BOLOMETER FRONTEND
OF THE
Resistive bolometers are temperature-sensitive electrical resistors, whose operation is based on changes in temperature due to the absorption of thermal infrared radiation. The bolometer elements used for this sensor are made of a thin membrane of amorphous silicon (a-Si), exhibiting a resistance/temperature dependency with a negative temperature coefficient (NTC). A widely used first-order approximation describing that temperature dependency for small changes in temperature is given by:
R(T ) = R(T0 ) ⋅ (1 + α ⋅ ΔT ) where R0 is the thermistor resistance at reference temperature T0 and α is the temperature coefficient (TCR) around T0. In the presented implementation the bolometer element is biased with a constant current source I0 (cf Fig. 1) Therefore, a variation in thermistor temperature causes a change of the voltage Vbolo across the bolometer. To specify requirements for the subsequent processing stages, signal amplitudes for typically surveillance scenarios, e.g. the detection of a human face with skin temperature of 37°C at 20°C ambient temperature, were investigated. The head at a distance of 20 meters from the sensor yields 0.1K temperature shift at the involved thermistor elements. A minimum resolvable bolometer temperature of 1/10 of this value (ΔT = 0.01K) has been chosen to ensure adequate temperature resolution for various surveillance applications. Using typical values R0=4MΩ, I0=500nA, α = –1% / K and ΔT = 0.01K yields a signal voltage amplitude at the bolometer frontend of 200µV.
III.
TEMPORAL CONTRAST PIXEL AMPLIFIER
Previously a temporal contrast pixel circuit for visible light vision sensors has been developed [1][2]. These vision sensors use self-timed, differencing capacitive-feedback amplifiers to amplify changes in the photoreceptor voltage. The implementation of a temporal contrast pixel for microbolometer sensors was based on this prior work, however due to the different nature and magnitude of the input signal, changes in amplifier circuit topology and modifications of the reset scheme were necessary.
total gain of the two-stage amplifier is given by A = A1·ASF·A2 ≈ C1/C2·C3/C4. Using C2 = C4 = 20fF, this configuration results in C1 and C3 capacitance values of 270fF. Thus, the total capacitance of a two-stage amplifier is 580fF compared to 3.6pF for a one-stage amplifier implementation with equal voltage gain, saving about a factor 6 in silicon area. Calculating the total gain based on process parameters, operating points and device dimensions yields A = 48.2dB. Eventually, the output VDiff2 of the second amplifier stage is connected to the inputs of two tuneable threshold comparators which generate events representing a fractional increase or decrease in bolometer temperature. A small digital part, implementing a handshake protocol with an asynchronous bus arbiter [1] completes the pixel circuit. These building blocks are out of the scope of this paper. IV.
Fig. 1
Pixel block diagram
Fig. 1 shows the block diagram of the bolometerfrontend and the differencing amplifier. The input signal to the differencing amplifier is the voltage at the output node of the bolometer frontend Vbolo. IR radiation is sensed by the bolometer thermistor and is converted to a voltage signal. Voltage transients at the node Vbolo are processed and appear as an amplified deviation from a defined reset voltage level at the output node VDiff2. The amplifier stages are (repeatedly) balanced by means of reset switches when a certain output signal condition has been detected, resulting in a defined reset voltage level by reestablishing the amplifier’s DC operating point. The reset condition is defined as the voltage deviation at VDiff2 reaching a tunable threshold. Consequently only variations of Vbolo and therefore only temporal changes in temperature are amplified. The magnitude of the temperature transients is encoded in the time domain in the form of inter-event intervals. Due to the small input voltage swing and requirements of the subsequent processing stages in terms of sensitivity and SNR, a voltage gain of above 45dB is needed. Practical constraints in terms of area and power-consumption combined with the stringent gain matching requirements prohibit the use of OTAs. In order to minimize gain mismatch and, as a consequence, inter-pixel fixed pattern noise (FPN), the use of, in CMOS technology well-defined capacitor ratios was chosen for setting the amplifier gain. In operation mode (reset switches are not conducting) the closed-loop gain of the first amplifier stage is approximately given by A1 = C1/C2. To reach the desired voltage gain, a one-stage amplifier implementation with a minimum reasonable capacitor value (with respect to matching properties and effects of parasitic capacitances) of C2 = 20fF would result in an unacceptably large capacitor C1 of about 3.6pF. To meet all of the above listed requirements, a twostage topology of single-ended inverting common-source stages operating in the sub-threshold region, separated by a follower buffer, was chosen. The optimum distribution of gain between the two stages in terms of silicon area is achieved when both gains are made equal (A1 = A2). The
CIRCUIT DETAILS
The frontend and amplifier circuit (Fig. 2) consists of the bolometer bias current generator (M1), two voltagemode capacitive-feedback amplifier stages (M3, M4, C1, C2; M8, M9, C3, C4), a source follower (M5, M6) and the reset control circuit (M10 – M16, C5) with reset transistors M2 and M7. We distinguish between reset and normal operation mode. The reset mode is used to determine the DC operating point of the capacitive-feedback amplifiers. During normal operation, AC input signals are amplified with a well defined gain.
Fig. 2
Schematic of the pixel circuit
A. Reset Circuit A reset cycle is initiated by the arbiter [1] by activating the “ackX” and “ackY” signals simultaneously. This pulls down the “!reset” signal which starts to rise when the reset is deactivated. The rise time is termed “refractory period” and can be adjusted by the “biasRef” voltage which determines the charge current of C5. This “refractory period” is used to control event rates at the pixel level. During reset, the drain source voltage of the reset transistors M2 and M7 is approximately zero and thus M3 and M8 are diode connected. The resulting gate source
voltage of M3 and M8 determines the DC operating point of the switched capacitor amplifiers (VD3≈VG3 = VDD –VTH3; VD8≈VG8 = VDD – VTH8). During normal operation, the gates of M3 and M8 have a high impedance connection to ground and thus are very susceptible to injected charge. Therefore, when switching off the reset transistors M2 and M7, special care has to be taken that the remaining charges in the channels of M2 and M7 do not alter the DC operating point (channel charge injection [7]). When switching off a transistor, the distribution of charges to drain and source can hardly be controlled [8][9]. Therefore, a novel and approach has been taken in this design, guaranteeing its functionality independent of the channel charge distribution: If both amplifier stages are in normal operation mode (non reset), any changes of the “Diff1” output signal are amplified by the subsequent stages. Therefore, the charge injection of M2 has a much greater impact on the output signal than that of M7. To eliminate the effect of the charge injection of M2 on the output signal “Diff2”, it must be guaranteed that the second stage is turned on (V!reset = VDD) after the first stage. This is achieved by two different reset signals “breset” and “!reset”. The transistor M7 will stop conducting when its gate source voltage reaches the threshold voltage (approximately VG7 = VDD – VTH8 – VTH7 = 1.9V @ VDD = 3.3V). Transistor M2 will stop conducting when the input voltage of the inverter formed by M13 and M14 reaches approximately 0.9V, depending on the dimensions of M13 and M14. If the slope of the “!reset” signal is limited, the second stage is held in its reset phase for the settling time of the charge injection transients from the first stage. Hence, effects due to charge injection in the first stage are suppressed. Additionally, clock feedthrough effects [10] must be taken into consideration. For the same reasons as stated in the preceding paragraph, clock feedthrough errors of the first stage are not transferred to the output signal. Clock feedthrough effects increase with the slope of the gate voltage pulses. To reduce the clock feedthrough of the second stage, the slowly rising “!reset” sawtooth signal is used as control signal of M7. B. Layout The pixel layout is shown in Fig. 3. The two big light colored rectangles represent the capacitors C1 and C3. The squares in the lower left and upper right corner are the bonding pads where the bolometer is connected to the pixel. C2, C4 and C7 are placed at the lower side of the layout. At the top, enclosed by a guard-ring, sits the digital part implementing the communication protocol. Using the chosen topology allowed to fit the complete amplifier circuit into an area of < 2000µm2.
Fig. 3
Pixel layout (50µm×50µm including bolometer connection pads)
V.
RESULTS
A test pixel has been implemented on the chip next to the imager array, where internal signals (“Diff1”, “Diff2”, “Fout”, “breset”, “!reset”) were buffered and connected to output pads. The gate voltages of M3 and M8 have not been connected to output buffers as they are very high impedance nodes and the capacitive load would prevent the amplifiers from working. A comparison of calculation, simulation and measurement of the gains of the stages of the amplifier is given in TABLE I. The results are in very good agreement. At the operating point yielding the results in TABLE I. , the static power consumption of the amplifier is 85nW. A. Frequency Response In Fig. 4, the measured frequency response of the test pixel is shown. The –3dB corner frequency for the simulation with parasitic extraction is about f3dB = 10kHz. At lower frequencies, the measurements results agree very well with the simulation results. In measurements, the corner frequency of the test pixel is reduced as compared to the simulations. This disagreement is caused by the additional capacitive load from the parasitic capacitances of the metal line connections to the internal nodes of the test pixel. TABLE I.
GAIN SIMULATION AND MEASUREMENT RESULTS.
f = 1000 Hz
A1 (dB)
ASF (dB)
A2 (dB)
A (dB)
Calculation
24.9
-1.5
24.8
48.2
Simulation
24.7
-1.57
24.63
47.79
Parasitic Simulation
24.23
-1.57
23.06
46.93
Measurement
23.06
-1.39
24.81
46.48
VI.
Fig. 4
Measured amplifier frequency response
CONCLUSIONS
A small-area, ultra low-power, low-mismatch differencing amplifier for use in transient pixels of micro-bolometer based temporal contrast IR sensors has been designed, fabricated and characterized. The two-stage amplifier works in the sub-threshold domain, has a voltage gain of 46dB, a 3dB bandwidth of about 10kHz and consumes 85nW of static power. The amplifier circuit has been fabricated in a 0.35µm 4M2P standard CMOS process and consumes < 2000µm2 of silicon area, enabling a square pixel size of 50µm×50µm. The chosen circuit topology meets all design specifications and will initially be used in a 64×64 micro-bolometer array sensor for surveillance applications. ACKNOWLEDGEMENTS
B. Transient Response In Fig. 5, the measured transient response for a sinusoidal input stimulus with a frequency of 100Hz and 30mV peak-peak is shown. The bias voltages VBiasDiff1 and VBiasDiff2 have been set equal which results in the same DC operating point (reset voltage) of both stages (VDiff1, VDiff2) of approximately 2.63V.
The authors would like to acknowledge Tobi Delbrück and Patrick Lichtsteiner from the Institute of Neuroinformatics at the ETH/UNI Zurich for original temporal contrast pixel circuit design, continuous support and numerous discussions.
The different amplitude of the peaks in the output signal VDiff2 for rising and falling input voltage Vbolo is caused by different relative comparator threshold voltages of approximately 0.57V for the higher and –0.15V for the lower threshold. When VDiff2 exceeds one of these threshold voltages, an event is generated and the reset sequence is initiated (Vbreset in Fig. 5).
[1]
It is clearly visible that the charge injection at the first stage output VDiff1 (marked with arrows in the transient response) is not fed through to the output signal VDiff2 of the second stage. In the output signal VDiff2 neither charge injection nor clock feedthrough effects are observable.
Fig. 5
Measured transient response
REFERENCES Lichtsteiner, P.; Posch, C.; Delbruck, T., "A 128 × 128 120db 30mw asynchronous vision sensor that responds to relative intensity change," Solid-State Circuits, 2006 IEEE International Conference, Dig. of Tech. Papers, pp. 2060- 2069, Feb. 6-9, 2006 [2] Lichtsteiner, P.; Delbruck, T.; Posch, C., "A 100dB dynamic range high-speed dual-line optical transient sensor with asynchronous readout," Circuits and Systems, 2006 IEEE International Symposium on, Proceedings, 21-24 May 2006 [3] Posch, C.; Hofstätter, M.; Matolin, D.; et. al., "A dual-line optical transient sensor with on-chip precision time-stamp generation," Solid-State Circuits, 2007 IEEE International Conference, Dig. of Tech. Papers, pp. 500-501, Feb. 11-15, 2007 [4] D. Bauer, A. N. Belbachir, N. Donath, G. Gritsch, B. Kohn, M. Litzenberger, C. Posch, P. Schön, and S. Schraml, "Embedded Vehicle Speed Estimation System Using an Asynchronous Temporal Contrast Vision Sensor", EURASIP Journal on Embedded Systems, Article ID 82174, 12 p., Volume 2007, doi:10.1155/2007/82174, 2007 [5] Belbachir, A.N.; Litzenberger, M.; Posch, C.; Donath, N.; Gritsch, G.; Kohn, B.; Schraml, S.; Garn, H., "Estimation of Vehicle Speed Based on Asynchronous Data from a Silicon Retina Optical Sensor," Intelligent Transportation Systems, 2006. Proceedings. 2006 IEEE, vol., no., pp. 653- 658, Sep 17-20, 2006 [6] C. Posch, M. Hofstätter, M. Litzenberger, D. Matolin, N. Donath, P. Schön, H. Garn, " Wide dynamic range, high-speed machine vision with a 2×256 pixel temporal contrast vision sensor," Circuits and Systems,. ISCAS 2007. Proceedings. 2007 IEEE International Symposium on, vol., no., pp, May 29-31, 2007 [7] Wegmann, G.; Vittoz E.A.; Rahali F., "Charge Injection in Analog MOS Switches," Solid-State Circuits, IEEE Journal of, vol. SC-22, pp. 1091-1097, Dec. 1987 [8] Sheu B.J.; Hu C., “Switch-Induced Error Voltage on a Switched Capacitor,” Solid-State Circuits, IEEE Journal of, vol. SC-19, pp. 519-525, Aug. 1984 [9] Eichenberger “Dummy Transistor Compensation of Analog MOS Switches” Solid-State Circuits, IEEE Journal of, vol. 24, pp. 11431145, Aug. 1989 [10] Razavi B., “Design Of Analog CMOS Integrated Circuits,” McGraw-Hill International Edition, 2001
I.
INTRODUCTION
Over the past few years, a novel species of biologyinspired, or neuromorphic, vision sensors, the so called temporal contrast or optical transient sensor, has been proposed, developed and published [1][2][3]. These devices are gaining increasing popularity and find their way into various fields of machine vision like industrial automation, surveillance and automotive applications [4][5][6]. The pixels employed in these sensors operate autonomously and respond with low latency and high temporal resolution to changes in intensity by generating asynchronous spike events. The events are used to trigger the transmission of data packets containing the respective pixel’s address and are referred to as ‘address-events’ (AE). The output volume of such a data-driven sensor depends on the dynamic contents of the target scene; pixels that are not stimulated visually do not produce output. This leads to a complete suppression of image data redundancy as compared to traditional, frame-based image sensors. Because output bandwidth is automatically dedicated to dynamic parts of the scene, these devices are especially suited for applications in surveillance and motion analysis. Surveillance scenarios often involve low or zero visible illumination of the target scene. Uncooled microbolometers are the sensors of choice when it comes to lowcost infrared (IR) vision solutions, as they are sensitive in the thermal IR spectral range of 8µm – 15µm wavelength and can be readily integrated with CMOS readout circuitry. A temporal contrast IR sensor, based on a microbolometer thermistor array and on asynchronous temporal contrast pixel circuits with their inherent motion detection capability, appears to be a promising solution to certain surveillance and motion detection/analysis problems at low/zero visible light and enables low data rate, low latency machine vision in the thermal IR spectral range. In order to realize a bolometer-based temporal contrast IR sensor, a differencing amplifier for the voltage signal delivered by the bolometer-frontend in response to the small variations in resistance of the bolometer thermistor is called for. The amplifier amplifies only input signal changes irrespective of the exact DC input level and provides a reset mechanism which is used to encode the difference in received IR radiation in the time domain.
Taking into account a time constant of about 10ms for the bolometer element, high bandwidth operation is not required. As the amplifier is to be used in each pixel of a thousands-of-pixels imager array, area and power consumption are of major concern, ruling out the use of OTAs. Furthermore, precautions have to be taken in order to maximize gain matching to reduce fixed pattern noise (FPN). In this paper we present topology, design and characterization of a two-stage capacitive-feedback differencing amplifier for micro-bolometer based temporal contrast IR sensor pixels. The pixel circuit has been fabricated in a 0.35µm standard CMOS process and has been tested and characterized. Design specifications have been met by the chosen circuit topology. II.
ELECTRICAL CHARACTERISTICS BOLOMETER FRONTEND
OF THE
Resistive bolometers are temperature-sensitive electrical resistors, whose operation is based on changes in temperature due to the absorption of thermal infrared radiation. The bolometer elements used for this sensor are made of a thin membrane of amorphous silicon (a-Si), exhibiting a resistance/temperature dependency with a negative temperature coefficient (NTC). A widely used first-order approximation describing that temperature dependency for small changes in temperature is given by:
R(T ) = R(T0 ) ⋅ (1 + α ⋅ ΔT ) where R0 is the thermistor resistance at reference temperature T0 and α is the temperature coefficient (TCR) around T0. In the presented implementation the bolometer element is biased with a constant current source I0 (cf Fig. 1) Therefore, a variation in thermistor temperature causes a change of the voltage Vbolo across the bolometer. To specify requirements for the subsequent processing stages, signal amplitudes for typically surveillance scenarios, e.g. the detection of a human face with skin temperature of 37°C at 20°C ambient temperature, were investigated. The head at a distance of 20 meters from the sensor yields 0.1K temperature shift at the involved thermistor elements. A minimum resolvable bolometer temperature of 1/10 of this value (ΔT = 0.01K) has been chosen to ensure adequate temperature resolution for various surveillance applications. Using typical values R0=4MΩ, I0=500nA, α = –1% / K and ΔT = 0.01K yields a signal voltage amplitude at the bolometer frontend of 200µV.
III.
TEMPORAL CONTRAST PIXEL AMPLIFIER
Previously a temporal contrast pixel circuit for visible light vision sensors has been developed [1][2]. These vision sensors use self-timed, differencing capacitive-feedback amplifiers to amplify changes in the photoreceptor voltage. The implementation of a temporal contrast pixel for microbolometer sensors was based on this prior work, however due to the different nature and magnitude of the input signal, changes in amplifier circuit topology and modifications of the reset scheme were necessary.
total gain of the two-stage amplifier is given by A = A1·ASF·A2 ≈ C1/C2·C3/C4. Using C2 = C4 = 20fF, this configuration results in C1 and C3 capacitance values of 270fF. Thus, the total capacitance of a two-stage amplifier is 580fF compared to 3.6pF for a one-stage amplifier implementation with equal voltage gain, saving about a factor 6 in silicon area. Calculating the total gain based on process parameters, operating points and device dimensions yields A = 48.2dB. Eventually, the output VDiff2 of the second amplifier stage is connected to the inputs of two tuneable threshold comparators which generate events representing a fractional increase or decrease in bolometer temperature. A small digital part, implementing a handshake protocol with an asynchronous bus arbiter [1] completes the pixel circuit. These building blocks are out of the scope of this paper. IV.
Fig. 1
Pixel block diagram
Fig. 1 shows the block diagram of the bolometerfrontend and the differencing amplifier. The input signal to the differencing amplifier is the voltage at the output node of the bolometer frontend Vbolo. IR radiation is sensed by the bolometer thermistor and is converted to a voltage signal. Voltage transients at the node Vbolo are processed and appear as an amplified deviation from a defined reset voltage level at the output node VDiff2. The amplifier stages are (repeatedly) balanced by means of reset switches when a certain output signal condition has been detected, resulting in a defined reset voltage level by reestablishing the amplifier’s DC operating point. The reset condition is defined as the voltage deviation at VDiff2 reaching a tunable threshold. Consequently only variations of Vbolo and therefore only temporal changes in temperature are amplified. The magnitude of the temperature transients is encoded in the time domain in the form of inter-event intervals. Due to the small input voltage swing and requirements of the subsequent processing stages in terms of sensitivity and SNR, a voltage gain of above 45dB is needed. Practical constraints in terms of area and power-consumption combined with the stringent gain matching requirements prohibit the use of OTAs. In order to minimize gain mismatch and, as a consequence, inter-pixel fixed pattern noise (FPN), the use of, in CMOS technology well-defined capacitor ratios was chosen for setting the amplifier gain. In operation mode (reset switches are not conducting) the closed-loop gain of the first amplifier stage is approximately given by A1 = C1/C2. To reach the desired voltage gain, a one-stage amplifier implementation with a minimum reasonable capacitor value (with respect to matching properties and effects of parasitic capacitances) of C2 = 20fF would result in an unacceptably large capacitor C1 of about 3.6pF. To meet all of the above listed requirements, a twostage topology of single-ended inverting common-source stages operating in the sub-threshold region, separated by a follower buffer, was chosen. The optimum distribution of gain between the two stages in terms of silicon area is achieved when both gains are made equal (A1 = A2). The
CIRCUIT DETAILS
The frontend and amplifier circuit (Fig. 2) consists of the bolometer bias current generator (M1), two voltagemode capacitive-feedback amplifier stages (M3, M4, C1, C2; M8, M9, C3, C4), a source follower (M5, M6) and the reset control circuit (M10 – M16, C5) with reset transistors M2 and M7. We distinguish between reset and normal operation mode. The reset mode is used to determine the DC operating point of the capacitive-feedback amplifiers. During normal operation, AC input signals are amplified with a well defined gain.
Fig. 2
Schematic of the pixel circuit
A. Reset Circuit A reset cycle is initiated by the arbiter [1] by activating the “ackX” and “ackY” signals simultaneously. This pulls down the “!reset” signal which starts to rise when the reset is deactivated. The rise time is termed “refractory period” and can be adjusted by the “biasRef” voltage which determines the charge current of C5. This “refractory period” is used to control event rates at the pixel level. During reset, the drain source voltage of the reset transistors M2 and M7 is approximately zero and thus M3 and M8 are diode connected. The resulting gate source
voltage of M3 and M8 determines the DC operating point of the switched capacitor amplifiers (VD3≈VG3 = VDD –VTH3; VD8≈VG8 = VDD – VTH8). During normal operation, the gates of M3 and M8 have a high impedance connection to ground and thus are very susceptible to injected charge. Therefore, when switching off the reset transistors M2 and M7, special care has to be taken that the remaining charges in the channels of M2 and M7 do not alter the DC operating point (channel charge injection [7]). When switching off a transistor, the distribution of charges to drain and source can hardly be controlled [8][9]. Therefore, a novel and approach has been taken in this design, guaranteeing its functionality independent of the channel charge distribution: If both amplifier stages are in normal operation mode (non reset), any changes of the “Diff1” output signal are amplified by the subsequent stages. Therefore, the charge injection of M2 has a much greater impact on the output signal than that of M7. To eliminate the effect of the charge injection of M2 on the output signal “Diff2”, it must be guaranteed that the second stage is turned on (V!reset = VDD) after the first stage. This is achieved by two different reset signals “breset” and “!reset”. The transistor M7 will stop conducting when its gate source voltage reaches the threshold voltage (approximately VG7 = VDD – VTH8 – VTH7 = 1.9V @ VDD = 3.3V). Transistor M2 will stop conducting when the input voltage of the inverter formed by M13 and M14 reaches approximately 0.9V, depending on the dimensions of M13 and M14. If the slope of the “!reset” signal is limited, the second stage is held in its reset phase for the settling time of the charge injection transients from the first stage. Hence, effects due to charge injection in the first stage are suppressed. Additionally, clock feedthrough effects [10] must be taken into consideration. For the same reasons as stated in the preceding paragraph, clock feedthrough errors of the first stage are not transferred to the output signal. Clock feedthrough effects increase with the slope of the gate voltage pulses. To reduce the clock feedthrough of the second stage, the slowly rising “!reset” sawtooth signal is used as control signal of M7. B. Layout The pixel layout is shown in Fig. 3. The two big light colored rectangles represent the capacitors C1 and C3. The squares in the lower left and upper right corner are the bonding pads where the bolometer is connected to the pixel. C2, C4 and C7 are placed at the lower side of the layout. At the top, enclosed by a guard-ring, sits the digital part implementing the communication protocol. Using the chosen topology allowed to fit the complete amplifier circuit into an area of < 2000µm2.
Fig. 3
Pixel layout (50µm×50µm including bolometer connection pads)
V.
RESULTS
A test pixel has been implemented on the chip next to the imager array, where internal signals (“Diff1”, “Diff2”, “Fout”, “breset”, “!reset”) were buffered and connected to output pads. The gate voltages of M3 and M8 have not been connected to output buffers as they are very high impedance nodes and the capacitive load would prevent the amplifiers from working. A comparison of calculation, simulation and measurement of the gains of the stages of the amplifier is given in TABLE I. The results are in very good agreement. At the operating point yielding the results in TABLE I. , the static power consumption of the amplifier is 85nW. A. Frequency Response In Fig. 4, the measured frequency response of the test pixel is shown. The –3dB corner frequency for the simulation with parasitic extraction is about f3dB = 10kHz. At lower frequencies, the measurements results agree very well with the simulation results. In measurements, the corner frequency of the test pixel is reduced as compared to the simulations. This disagreement is caused by the additional capacitive load from the parasitic capacitances of the metal line connections to the internal nodes of the test pixel. TABLE I.
GAIN SIMULATION AND MEASUREMENT RESULTS.
f = 1000 Hz
A1 (dB)
ASF (dB)
A2 (dB)
A (dB)
Calculation
24.9
-1.5
24.8
48.2
Simulation
24.7
-1.57
24.63
47.79
Parasitic Simulation
24.23
-1.57
23.06
46.93
Measurement
23.06
-1.39
24.81
46.48
VI.
Fig. 4
Measured amplifier frequency response
CONCLUSIONS
A small-area, ultra low-power, low-mismatch differencing amplifier for use in transient pixels of micro-bolometer based temporal contrast IR sensors has been designed, fabricated and characterized. The two-stage amplifier works in the sub-threshold domain, has a voltage gain of 46dB, a 3dB bandwidth of about 10kHz and consumes 85nW of static power. The amplifier circuit has been fabricated in a 0.35µm 4M2P standard CMOS process and consumes < 2000µm2 of silicon area, enabling a square pixel size of 50µm×50µm. The chosen circuit topology meets all design specifications and will initially be used in a 64×64 micro-bolometer array sensor for surveillance applications. ACKNOWLEDGEMENTS
B. Transient Response In Fig. 5, the measured transient response for a sinusoidal input stimulus with a frequency of 100Hz and 30mV peak-peak is shown. The bias voltages VBiasDiff1 and VBiasDiff2 have been set equal which results in the same DC operating point (reset voltage) of both stages (VDiff1, VDiff2) of approximately 2.63V.
The authors would like to acknowledge Tobi Delbrück and Patrick Lichtsteiner from the Institute of Neuroinformatics at the ETH/UNI Zurich for original temporal contrast pixel circuit design, continuous support and numerous discussions.
The different amplitude of the peaks in the output signal VDiff2 for rising and falling input voltage Vbolo is caused by different relative comparator threshold voltages of approximately 0.57V for the higher and –0.15V for the lower threshold. When VDiff2 exceeds one of these threshold voltages, an event is generated and the reset sequence is initiated (Vbreset in Fig. 5).
[1]
It is clearly visible that the charge injection at the first stage output VDiff1 (marked with arrows in the transient response) is not fed through to the output signal VDiff2 of the second stage. In the output signal VDiff2 neither charge injection nor clock feedthrough effects are observable.
Fig. 5
Measured transient response
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