A wide-band multipath CMOS OTA for high speed applications
IEICE Electronics Express, Vol.8, No.7, 449–453
A wide-band multipath CMOS OTA for high speed applications Ali Vatanjou1a) , Z D Koozehkanani, Jafar Sobhi, and Farhad Nobakht Daghdaghan2b) 1
Faculty of Electrical and Computer Engineering, University of Tabriz
Emam Khomeini Ave., Tabriz, Iran P.O. Box 5166616471 2
IC Design Laboratory, Faculty of Electrical and Computer Engineering,
University of Tabriz a) [email protected] b) [email protected]
Abstract: A fast settling multipath CMOS OTA for high speed switched capacitor applications is presented here. With the basic topology similar to folded-cascode, bandwidth and DC gain of the OTA are enhanced by adding extra paths for signal from input to output. Designed circuit is simulated with HSPICE using level 49 parameters (BSIM 3v3) in 0.35 um standard CMOS technology. The DC gain achieved is 56.7 db and the Unity Gain Bandwidth (UGB) obtained is 1.15 GHz. Keywords: OTA (Operational Transconductance Amplifier), DC gain, Unity Gain Bandwidth (UGBW) Classification: Integrated circuits References [1] B. Razavi, Design of CMOS analog integrated circuits, McGraw-Hill, 2001. [2] S. M. Mallya and J. H. Nevin, “Design procedure for fully differential folded-cascode CMOS operational amplifier,” IEEE J. Solid-State Circuits, vol. 24, no. 6, pp. 1737–1740, Dec. 1989. [3] F. Roewer and U. Kleine, “A Novel Class of Complementary FoldedCascode Op-amps for Low Voltage,” IEEE J. Solid-State Circuits, vol. 37, no. 8, pp. 1080–1083, Aug. 2002. [4] C. A. Laber and P. R. Gray, “A positive-feedback transconductance amplifier with applications to high-frequency, high-Q CMOS switched-capacitor filters,” IEEE J. Solid-State Circuits, vol. 23, no. 6, pp. 1370–1378, Dec. 1988. [5] J. Lioyd and J. Hae-Seung, “A CMOS op-amp with fully differential gain enhancement,” IEEE J. Solid-State Circuits, vol. 41, no. 3, pp. 241–243, March 1994. [6] W. Sanseze and Z. Y. Zhang, “Feed-forward Compensation Techniques For High-Frequency CMOS Amplifiers,” IEEE J. Solid-State Circuits, vol. 25, no. 6, pp. 1590–1595, Dec. 1990. c
IEICE 2011
DOI: 10.1587/elex.8.449 Received February 05, 2011 Accepted February 28, 2011 Published April 10, 2011
449
IEICE Electronics Express, Vol.8, No.7, 449–453
1
Introduction
In design of most closed loop systems, OTAs are the most challenging unit from design perspective. It has to achieve high DC gain and low thermal and flicker noise, also high bandwidth required for systems with high frequency clock especially in switched capacitor applications. Additionally, power consumption of the OTA is one of the critical issues for applications with low power consumption target. Slew-rate and input common mode range are other important aspects of the OTA [1, 2]. Telescopic and folded-cascode structures are two common structures for single stage op-amps. Two main drawbacks of the telescopic OTA are low input common mode range and large voltage headroom in output and main drawbacks of the folded OTA are higher power consumption and lower UGBW. In this work, to benefit from the high input common mode range of the conventional folded-cascode and also to have higher DC gain and UGBW, total transconductance of the amplifier is increased by adding extra paths for signal from input to output [3]. Other techniques for increasing DC gain of the op-amp such as using positive feedback or gain boosting are based on increasing output resistance of the op-amp and so, only DC gain of the op-amp increases and with these techniques UGBW remains constant [4, 5]. This paper is divided into following parts. In section2 proposed multi path OTA is analyzed. Simulation results are indicated in section 3 and section 4 concludes the paper.
2
Design of a Fast Settling Op-amp
2.1 Basic topology Main idea is to increase the DC gain and UGBW of the folded-cascode OTA by increasing its total transconductance. To do so, extra paths for signal from input to output are provided. Basic fully differential topology of the designed OTA is shown in Fig. 1. Two extra paths are provided in addition to signal path in the conventional folded-cascode. The first path is constructed by m3: m5 current mirrors (1:M) and the second one is constructed by m3: m4 current mirrors (1:N) and since three paths exist the OTA is called a three-path OTA. Common mode feedback is applied to p-type transistors of m9 which are not located on signal path. 2.2 Small signal Analysis The voltage gain transfer function of the op-amp is obtained as Av (w) = Gm (w).Zout (w)
(1)
Where the total transconductance of the op-amp is denoted by Gm (w) and achieved by adding the transconductances of all of the existing signal paths. M gm1 (1 + s/wpy )(1 + s/wpx ) N gm1 gm2 + + (1 + s/wpy ) (1 + s/wpz )(1 + s/wpx ) Gm (s) =
c
IEICE 2011
DOI: 10.1587/elex.8.449 Received February 05, 2011 Accepted February 28, 2011 Published April 10, 2011
(2)
450
IEICE Electronics Express, Vol.8, No.7, 449–453
Fig. 1. Topology of designed OTA Where 1 = Rx Cx gm3 (Cd1 + Cd3 + Cg3 + Cg4 + Cg5 )
wpx ∼ =
(3)
wpy ∼ =
1 gm6 = Ry Cy (Cs6 + Cd5 + Cd2 )
(4)
wpz ∼ =
1 gm7 = Rz Cz (cd8 + Cd4 + Cs7 )
(5)
are the poles associated with the nodes X, Y and Z. In equation (2), zeros due to gate-drain capacitance of m1-m5 are neglected since they are located on higher frequencies. Capacitance of Cc is used to generate a left-hand located zero which appears on current mirror signal paths of m3:m4 and m3:m5. This zero equals to gm1 (6) wzc = − Cc By proper selection of Cc , wzc can negate the effect of wpx and feed forward compensation could be done [6]. So Cc is obtained as equation (7).
Cc =
gm1 .(Cd1 + Cd3 + Cg3 + Cg4 + Cg5 ) gm3
(7)
By omitting wpx from equation (2) and doing some algebraic efforts, equation (2) can be simplified as equation (8). Gm (s) =
(gm2 + (M + N )gm1 )(1 + s/wzph ) (1 + s/wpy )(1 + s/wpz )
(8)
In above equation wzph is a phantom zero and could be calculated by some mathematical operations as equation (9). This zero is located on a higher frequency than wpy and has less effect on frequency response of the op-amp. c
IEICE 2011
DOI: 10.1587/elex.8.449 Received February 05, 2011 Accepted February 28, 2011 Published April 10, 2011
wzph =
(gm2 + (M + N )gm1 )(wpy wpz ) (gm2 + M gm1 )(wpy ) + N gm1 wpz
(9)
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IEICE Electronics Express, Vol.8, No.7, 449–453
Finally, Zout as an output impedance of the OTA can be obtained by equation (10). Rout (10) Zout = 1 + Rout Cout s Where Cout = Cd7 + Cd6 + CL
(11)
Rout = (gm6 ro6 (ro5 ||ro2 ))||(gm7 ro7 (ro8 ||ro4 ))
(12)
By the use of the calculations above, the DC gain and UGBW of the OTA is achieved by equations (13) and (14), respectively. Av = (gm2 + (M + N )gm1 ).(Rout ) wu =
3
gm2 + (M + N )gm1 Cout
(13) (14)
Simulation Results
Three-path OTA and folded-cascode OTA are designed in 0.35 um standard CMOS technology and simulated with HSPICE software. To have a fair comparison between the conventional folded-cascode and three-path OTA, load capacitances, the size of the input transistors and power consumption are selected the same for both OTAs. Table I lists the specifications of the conventional folded-cascode and three-path OTAs. In this table, for both OTAs the load capacitance is 1 pF, input transistors size is equal to w/l = 140/0.35 and power consumption is 12.1 mw. To evaluate settling time of both folded-cascode and three-path OTAs a routine closed loop setup with feedback coefficient equal to 0.5 (β = 0.5), sampling capacitance equal to 1 pF, feedback capacitance equal to 0.5 pF and load capacitance equal to 1 pF is used. Variations of the designed three-path OTA with process corners is shown in Fig. 2 which shows a reduction of about %20 in DC gain in FF corner and %15 in UGBW in SS corner. Also, the designed OTA shows slight variations in SF and FS corners. Table I. Specifications of folded-cascode and three-path OTAs
c
IEICE 2011
DOI: 10.1587/elex.8.449 Received February 05, 2011 Accepted February 28, 2011 Published April 10, 2011
452
IEICE Electronics Express, Vol.8, No.7, 449–453
Fig. 2. Open loop Bodeplot showing variations of threepath OTA with process corners
4
Conclusion
In this paper, the aim of increasing total transconductance of the foldedcascode OTA in fully differential mode is done by adding two current mirror paths additional to cascode path. Consequently, with the same input transistors and the same power consumption and load capacitance, DC gain and UGBW of the folded-cascode are improved approximately by three and two times, respectively.
c
IEICE 2011
DOI: 10.1587/elex.8.449 Received February 05, 2011 Accepted February 28, 2011 Published April 10, 2011
453
A wide-band multipath CMOS OTA for high speed applications Ali Vatanjou1a) , Z D Koozehkanani, Jafar Sobhi, and Farhad Nobakht Daghdaghan2b) 1
Faculty of Electrical and Computer Engineering, University of Tabriz
Emam Khomeini Ave., Tabriz, Iran P.O. Box 5166616471 2
IC Design Laboratory, Faculty of Electrical and Computer Engineering,
University of Tabriz a) [email protected] b) [email protected]
Abstract: A fast settling multipath CMOS OTA for high speed switched capacitor applications is presented here. With the basic topology similar to folded-cascode, bandwidth and DC gain of the OTA are enhanced by adding extra paths for signal from input to output. Designed circuit is simulated with HSPICE using level 49 parameters (BSIM 3v3) in 0.35 um standard CMOS technology. The DC gain achieved is 56.7 db and the Unity Gain Bandwidth (UGB) obtained is 1.15 GHz. Keywords: OTA (Operational Transconductance Amplifier), DC gain, Unity Gain Bandwidth (UGBW) Classification: Integrated circuits References [1] B. Razavi, Design of CMOS analog integrated circuits, McGraw-Hill, 2001. [2] S. M. Mallya and J. H. Nevin, “Design procedure for fully differential folded-cascode CMOS operational amplifier,” IEEE J. Solid-State Circuits, vol. 24, no. 6, pp. 1737–1740, Dec. 1989. [3] F. Roewer and U. Kleine, “A Novel Class of Complementary FoldedCascode Op-amps for Low Voltage,” IEEE J. Solid-State Circuits, vol. 37, no. 8, pp. 1080–1083, Aug. 2002. [4] C. A. Laber and P. R. Gray, “A positive-feedback transconductance amplifier with applications to high-frequency, high-Q CMOS switched-capacitor filters,” IEEE J. Solid-State Circuits, vol. 23, no. 6, pp. 1370–1378, Dec. 1988. [5] J. Lioyd and J. Hae-Seung, “A CMOS op-amp with fully differential gain enhancement,” IEEE J. Solid-State Circuits, vol. 41, no. 3, pp. 241–243, March 1994. [6] W. Sanseze and Z. Y. Zhang, “Feed-forward Compensation Techniques For High-Frequency CMOS Amplifiers,” IEEE J. Solid-State Circuits, vol. 25, no. 6, pp. 1590–1595, Dec. 1990. c
IEICE 2011
DOI: 10.1587/elex.8.449 Received February 05, 2011 Accepted February 28, 2011 Published April 10, 2011
449
IEICE Electronics Express, Vol.8, No.7, 449–453
1
Introduction
In design of most closed loop systems, OTAs are the most challenging unit from design perspective. It has to achieve high DC gain and low thermal and flicker noise, also high bandwidth required for systems with high frequency clock especially in switched capacitor applications. Additionally, power consumption of the OTA is one of the critical issues for applications with low power consumption target. Slew-rate and input common mode range are other important aspects of the OTA [1, 2]. Telescopic and folded-cascode structures are two common structures for single stage op-amps. Two main drawbacks of the telescopic OTA are low input common mode range and large voltage headroom in output and main drawbacks of the folded OTA are higher power consumption and lower UGBW. In this work, to benefit from the high input common mode range of the conventional folded-cascode and also to have higher DC gain and UGBW, total transconductance of the amplifier is increased by adding extra paths for signal from input to output [3]. Other techniques for increasing DC gain of the op-amp such as using positive feedback or gain boosting are based on increasing output resistance of the op-amp and so, only DC gain of the op-amp increases and with these techniques UGBW remains constant [4, 5]. This paper is divided into following parts. In section2 proposed multi path OTA is analyzed. Simulation results are indicated in section 3 and section 4 concludes the paper.
2
Design of a Fast Settling Op-amp
2.1 Basic topology Main idea is to increase the DC gain and UGBW of the folded-cascode OTA by increasing its total transconductance. To do so, extra paths for signal from input to output are provided. Basic fully differential topology of the designed OTA is shown in Fig. 1. Two extra paths are provided in addition to signal path in the conventional folded-cascode. The first path is constructed by m3: m5 current mirrors (1:M) and the second one is constructed by m3: m4 current mirrors (1:N) and since three paths exist the OTA is called a three-path OTA. Common mode feedback is applied to p-type transistors of m9 which are not located on signal path. 2.2 Small signal Analysis The voltage gain transfer function of the op-amp is obtained as Av (w) = Gm (w).Zout (w)
(1)
Where the total transconductance of the op-amp is denoted by Gm (w) and achieved by adding the transconductances of all of the existing signal paths. M gm1 (1 + s/wpy )(1 + s/wpx ) N gm1 gm2 + + (1 + s/wpy ) (1 + s/wpz )(1 + s/wpx ) Gm (s) =
c
IEICE 2011
DOI: 10.1587/elex.8.449 Received February 05, 2011 Accepted February 28, 2011 Published April 10, 2011
(2)
450
IEICE Electronics Express, Vol.8, No.7, 449–453
Fig. 1. Topology of designed OTA Where 1 = Rx Cx gm3 (Cd1 + Cd3 + Cg3 + Cg4 + Cg5 )
wpx ∼ =
(3)
wpy ∼ =
1 gm6 = Ry Cy (Cs6 + Cd5 + Cd2 )
(4)
wpz ∼ =
1 gm7 = Rz Cz (cd8 + Cd4 + Cs7 )
(5)
are the poles associated with the nodes X, Y and Z. In equation (2), zeros due to gate-drain capacitance of m1-m5 are neglected since they are located on higher frequencies. Capacitance of Cc is used to generate a left-hand located zero which appears on current mirror signal paths of m3:m4 and m3:m5. This zero equals to gm1 (6) wzc = − Cc By proper selection of Cc , wzc can negate the effect of wpx and feed forward compensation could be done [6]. So Cc is obtained as equation (7).
Cc =
gm1 .(Cd1 + Cd3 + Cg3 + Cg4 + Cg5 ) gm3
(7)
By omitting wpx from equation (2) and doing some algebraic efforts, equation (2) can be simplified as equation (8). Gm (s) =
(gm2 + (M + N )gm1 )(1 + s/wzph ) (1 + s/wpy )(1 + s/wpz )
(8)
In above equation wzph is a phantom zero and could be calculated by some mathematical operations as equation (9). This zero is located on a higher frequency than wpy and has less effect on frequency response of the op-amp. c
IEICE 2011
DOI: 10.1587/elex.8.449 Received February 05, 2011 Accepted February 28, 2011 Published April 10, 2011
wzph =
(gm2 + (M + N )gm1 )(wpy wpz ) (gm2 + M gm1 )(wpy ) + N gm1 wpz
(9)
451
IEICE Electronics Express, Vol.8, No.7, 449–453
Finally, Zout as an output impedance of the OTA can be obtained by equation (10). Rout (10) Zout = 1 + Rout Cout s Where Cout = Cd7 + Cd6 + CL
(11)
Rout = (gm6 ro6 (ro5 ||ro2 ))||(gm7 ro7 (ro8 ||ro4 ))
(12)
By the use of the calculations above, the DC gain and UGBW of the OTA is achieved by equations (13) and (14), respectively. Av = (gm2 + (M + N )gm1 ).(Rout ) wu =
3
gm2 + (M + N )gm1 Cout
(13) (14)
Simulation Results
Three-path OTA and folded-cascode OTA are designed in 0.35 um standard CMOS technology and simulated with HSPICE software. To have a fair comparison between the conventional folded-cascode and three-path OTA, load capacitances, the size of the input transistors and power consumption are selected the same for both OTAs. Table I lists the specifications of the conventional folded-cascode and three-path OTAs. In this table, for both OTAs the load capacitance is 1 pF, input transistors size is equal to w/l = 140/0.35 and power consumption is 12.1 mw. To evaluate settling time of both folded-cascode and three-path OTAs a routine closed loop setup with feedback coefficient equal to 0.5 (β = 0.5), sampling capacitance equal to 1 pF, feedback capacitance equal to 0.5 pF and load capacitance equal to 1 pF is used. Variations of the designed three-path OTA with process corners is shown in Fig. 2 which shows a reduction of about %20 in DC gain in FF corner and %15 in UGBW in SS corner. Also, the designed OTA shows slight variations in SF and FS corners. Table I. Specifications of folded-cascode and three-path OTAs
c
IEICE 2011
DOI: 10.1587/elex.8.449 Received February 05, 2011 Accepted February 28, 2011 Published April 10, 2011
452
IEICE Electronics Express, Vol.8, No.7, 449–453
Fig. 2. Open loop Bodeplot showing variations of threepath OTA with process corners
4
Conclusion
In this paper, the aim of increasing total transconductance of the foldedcascode OTA in fully differential mode is done by adding two current mirror paths additional to cascode path. Consequently, with the same input transistors and the same power consumption and load capacitance, DC gain and UGBW of the folded-cascode are improved approximately by three and two times, respectively.
c
IEICE 2011
DOI: 10.1587/elex.8.449 Received February 05, 2011 Accepted February 28, 2011 Published April 10, 2011
453
