ADC - Semantic Scholar
Analog Baseband Chain with Analog to Digital Converter (ADC) of Synthetic Aperture Radar (SAR) Receiver Faizah Abu Bakar, Tero Nieminen, Qaiser Nehal, Pekka Ukkonen, Ville Saari1 and Kari Halonen Aalto University School of Electrical Engineering SMARAD-2, Department of Micro- and Nanosciences P.0 Box 11000, FIN-00076 Aalto, Finland Email: [email protected]
Abstract—An analog baseband chain together with an analog to digital converter (ADC) for a Synthetic Aperture Radar (SAR) receiver implemented in 130nm CMOS technology is presented in this paper. The baseband and the ADC are integrated on a single chip, occupying 1.6mm2 (I and Q branch) of active silicon area. The baseband is selectable between 50MHz and 160MHz bandwidth through switches and the voltage gain can be controlled between 22dB and 27dB. The ADC has selectable mode of 5, 6, 7 and 8 bits via control switches. The baseband and the ADC achieve measured spurious-free dynamic range more than 45dBc over the 160MHz band. The circuits, which use a 1.2V supply voltage, dissipates minimum power of 214mW with 50MHz baseband and 5 bit mode ADC, and maximum power of 344mW with 160MHz baseband and 8 bit mode ADC.
C-BAND Balun RF In
Mixer Source follower IDAC Analogue Test Input
Analogue Test Obuf Output
ADC Test Input
50-MHz LPF Obuf
VGA1
160-MHz LPF
ADC
I out
ADC
Q out
VGA2
L-BAND IDAC RF In
X-BAND RF In
This work
Fig. 1.
I. I NTRODUCTION
SAR receiver.
The main advantageous feature of SAR is the insensitivity to weather conditions to process images regardless of day and night. Because of this attractive attribute, SAR is playing a major role in earth observation [1]. The receive antenna consists of multiple parallel sub-apertures to obtain wide swadth, high resolution image. Therefore, it is desirable to realize the receive cells with integrated circuits (ICs) in order to reduce size and power consumption. A high-performance analog baseband chain and an ADC implemented in a 130nm CMOS technology for such a SAR receive cell is described in this paper. The paper is organized as follows. Section II describes the SAR receiver architecture. Section III presents the circuit design of the baseband and section IV explains the ADC circuit design. The measured performances are reported in section V and the conclusions are presented in Section VI.
The quadrature mixer to separate between I/Q baseband is followed by source followers to drive a large parasitic capacitive loads of the following variable gain amplifier 1 (VGA1). DC-offset of the baseband is compensated by a 9bit current-steering digital-to-analog converter (IDAC). Analogue test input and output pins are available to measure the baseband alone, excluding the source follower. In order to measure the ADC as a stand alone structure, the ADC test input is connected after the output buffer (OBUF), just before the ADC. All the blocks in the receiver and the ADC are dc-coupled to each other. The baseband has two available bandwidths, 50MHz and 160MHz, and is connected to the multi-mode (5,6,7 and 8 bits) ADC. The selection of baseband bandwidth and ADC mode are controlled by digital control bits.
II. S YSTEM A RCHITECTURE
III. BASEBAND
The main objective of this work is to integrate a receiver together with an ADC on a single chip. The integrated SAR receiver as shown in Fig. 1 employs a direct conversion architecture. The receiver is able to receive 3 bands, C-band, L-band and X-band which can be selected to be connected to the baseband and ADC one at a time, by using switches controlled by digital control bits. 1 Currently
with Epcos, Finland.
978-1-4577-0704-9/10/$26.00 ©2011 IEEE
A. Variable Gain Amplifier The most important requirement of the VGA is that it should have 1GHz bandwidth over its entire gain tuning range. This ensures that the shape of the filter response is not affected by the VGA. The amplifier was divided into two design blocks: the variable gain stage (VGA1) and a fixed gain stage (VGA2). The first gain stage, shown in Fig. 2, is a variable gain degenerated differential pairs. It uses negative Miller capacitors (NMCs) (Cc1a and Cc1b ) to cancel the parasitic
207
VDD RD1a
RD1b RCM1
RCM2
Cc1a
VCMFB Cc1b
VOUT2 CL1 Realization of Rs Vgate
CL1
Rg1
Rg2
M1b
M1a VIN2+
VIN2Rs Cs Cf M6a
Cf M6b
VCM CMFB Amplifier
Fig. 2.
Schematic of the VGA stage 1.
gate-drain capacitances (Cgd1a and Cgd1b ) of the VGA1. This reduces the input capacitance of the VGA. Since the VGA1 stage and the low-pass filter (LPF) are dc coupled to each other, a common-mode feedback amplifier is used in the stage to stabilize the output dc voltage against process, voltage and temperature (PVT) variations. The voltage gain of VGA1 is [2]:
The filters are synthesized using a lossy prototype and realized as a continuous-time gm-C leapfrog filter, similar as in [3]. The load resistance is removed from the RLC prototype to minimize the loss of the last filter stage. All the poles are realized using Signal Flow Graph (SFG) method, where the structure is as shown in Fig. 3. The 50MHz filter is designed by scaling the gm and C from the 160MHz filter. In order to decrease the power consumption, the gm of 50MHz filter is halved from the value for 160MHz filter. A simple trasconductor structure with no internal poles, suitable for wideband filter as depicted in Fig. 4, is used in the filters. A common-mode feedforward (CMFF) circuit is included to obtain input common-mode rejection, and a common-mode feedback (CMFB) circuit to fix the output common-mode voltage of the transconductor. The approach of the lossy prototype is to accept low DC gain. Hence, the tranconductor is designed to have 26dB of gain. VDD
OUTN
OUTP
INP
INN
INP INP
INN
OUTN
INN
OUTP INP
INN
V_ERROR VSS CMFF
gm1a RD1a Av (s) ≈ − . (1 + gm1a R2s )( wsp2 + 1)( wsp3 + 1)
CMFB
INP INN
(1)
CMFF OUTP OUTN
gm gm
The voltage gain can be varied by changing the value of Rs . Fig. 2 shows that Rs can be implemented as a cascade connection of transistors. Therefore, the gate voltage Vgate of these transistors can be used to change the voltage gain. The next stage, VGA2 is a fixed gain and resistively loaded differential pairs. This VGA2 is connected at the output of the LPF. Here again NMCs (Cc2a and Cc2b ) are used to reduce the input capacitance of this stage. The result of the use of NMCs is that the bandwidth of the VGA is 1GHz over the entire gain tuning range. B. Low-Pass Filter
Fig. 4.
Transcconductor circuit.
Since the transconductor’s gain varies as a result of PVT variations, a negative resistance circuit is designed to control the varied gain [3]. The negative resistance circuit, which is connected at the output of each transconductor, is able to control the DC gain of the transconductors to achieve the desired 26dB in all PVT corners by means of a control voltage. The low-pass filters have embedded gain of 8dB in order to satisfy the overall gain requirement. To achieve this, the first feedforward transconductor is scaled by 4. C. Output Buffer VCM CONTROL CIRCUIT
VDD R1
R2
R2
M4 +
OUTN
M4
R1 OUTP
−
Both the low-pass filters with cutoff frequency of 50MHz and 160MHz are 5th-order Chebyshev prototype with a 0.3dB ripple. The LPF can be selected one at a time through switches controlled by a digital control bit. These LPFs act as antialiasing filters before the analog-to-digital conversion. The passband-edge of both the filters are programmable with 5bit binary weighted switched-capacitor matrices.
VCM R3 INP
M1
M1
R3
IREF
M2 INN
M2
M3
VSS Vout+
Vin+ Vin- k1gm
gm
gm
Fig. 3.
gm
gm
gm
gm
gm
5th-order gm-C low pass filter.
gm
gm
Vout-
Fig. 5.
Output buffer.
The output buffer is designed and connected after the VGA2 to drive the ADC. The OBUF has programmable resistive loads controlled by digital control bits, as shown in Fig. 5, in order to achieve maximum I and Q gain balance. Because the following ADC operates with a 600mV common-mode
208
bias voltage, the OBUF also includes a VCM control circuit at its output. IV. A NALOG
TO
D IGITAL C ONVERTER
pins. Fig. 8 depicts the measured magnitude response of the baseband at different gain setting. The gain tuning range is 5 dB with maximum gain achieved of 27dB.
The block diagram of the 5-8-bit pipelined ADC is presented in Fig. 6. The ADC consists of a flip-around sample and hold (S/H) front-end stage, six 1.5-bit double-sampling pipeline stages and a 2-bit flash back-end stage, similar as in [4]. The pipeline stages are based on conventional 1.5-bit Multiplying Digital-to-Analogue Converters (MDACs). Doublesampling is utilized in the S/H and the MDACs to achieve the sampling rate of 440-MS/s with 220-MHz clock. The ADC employs two-stage (telescopic+common source rail-torail stage) Miller-compensated opamps to have adequate openloop DC-gain and large output linear range. The capacitors and currents of the back-end opamps are scaled down. According to the mode selection (5-8bits) control word, the front-end opamps are shut down to decrease the power consumption. The input switches of the S/H and the first MDAC utilize bootstrapping. Differential pair dynamic comparators are used in the pipeline and the flash stages to achieve low power consumption and fast settling. The clocks are derived from a small-amplitude 440-MHz sinusoidal signal. Square wave is generated with a two-stage clock amplifier and cross-coupled inverters. Comparators and digital parts use the 440-MHz clock whereas the 220-MHz clock for the S/H and the MDACs is created by employing a customized flip-flop-based frequency divider. The output clock and data are taken out of the chip by utilizing low-voltage differential signaling (LVDS) drivers. Necessary reference voltages are generated from an external voltage VAGN D with an on-chip buffer. Div 2
+
VREF+
S/H VIN-
PL PL PL PL PL PL stage stage stage stage stage stage 1.5b 1.5b 1.5b 1.5b 1.5b 1.5b
Magnitude [dB]
26 25
10
Fig. 8.
24 23 40
100
160 200
40 100 Frequency [MHz]
160 200
300
Measured magnitude response with different gain setting.
5
0
−5
Flash stage 2b
−10
−15
−20
Bandwidth range of 160MHz baseband
Bandwidth range of 50MHz baseband
−25
−30
R1
−35
VCM
2 R1 VREF-
2
2
2
2
2
DELAY ALIGNMENT 2 2 2 2
R2
2
2 −40
2
30
50
100
160
200
300
Frequency [MHz]
2
RSD correction 5-8
Fig. 9.
LVDS drivers DOUT7+ DOUT7-
Fig. 6.
15
0
CLKOUT-
VIN+
20
5
LVDS
VAGND -
25
CLKOUT+
Vdd CLKIN-
Micrograph of the baseband and the ADC.
30
Magnitude [dB]
CLKIN+
Fig. 7.
DOUT0+ DOUT0-
Block diagram of the pipelined A/D Converter
V. M EASUREMENT R ESULTS The analog baseband chain with the analog to digital converter was fabricated in a 130nm CMOS process, and bonded directly to a 6-layer PCB. A micrograph of the circuit is shown in Fig. 7. The baseband chain with the ADC occupies 1.6 mm2 of silicon area. The supply voltage is provided separately for the baseband and the ADC such that the power consumption can be measured individually between the two blocks. A test signal is fed in to the test input pins and measured results of the baseband alone are taken from the test output
Measured bandwidth programmability with magnitude scaled at 1.
Fig. 9 shows the programmability of the bandwidth for both of the filters in the baseband. The 160MHz filter has a tuning range of 100MHz while the tuning range for the 50MHz filter is 35MHz in order to compensate PVT variations. The demodulation of the analog signal depends on the gain and phase imbalance between I and Q paths. Using the mixed-mode S-parameters, the I/Q imbalance is obtained. The magnitude imbalance for 160MHz baseband is within ±0.1dB and the phase imbalance is less than 11◦ in the passband, as shown in Fig. 10. The imbalance increases near the corner frequency due to the slight difference in the cutoff frequency between both branches. In order to obtain result for the whole baseband chain and the ADC, the output was measured at the output of the ADC
209
TABLE I T HE M EASURED P ERFORMANCE AND C OMPARISON S UMMARY.
Magnitude [dB]
0.4 0.2 0
Process Supply voltage Voltage gain (dB) BB[*] cutoff frequency IQ mismatch (Gain and Phase) Input-referred noise BB Input compression point ADC sampling rate ADC SNR (8,7,6,5b modes) SFDR[**] Power(mW)[**] 50MHz BB+5 bit ADC 50MHz BB+6 bit ADC 50MHz BB+7 bit ADC 50MHz BB+8 bit ADC 160MHz BB+5 bit ADC 160MHz BB+6 bit ADC 160MHz BB+7 bit ADC 160MHz BB+8 bit ADC Active silicon area [**]
−0.2 −0.4 50
100
160
200
160
200
Frequency [MHz]
Phase [degree]
20 10 0 −10 −20 50
100 Frequency [MHz]
Fig. 10.
I/Q imbalance for 160MHz baseband.
with input fed in to the test input pins. Fig. 11 presents output spectrum measured from the ADC output with a 10-MHz sinusoidal input. Second and third harmonic components are at -48dBc and -45dBc, respectively. Spurious-free dynamic range (SFDR) as a function of frequency is shown in Fig. 12. POWER SPECTRUM 0
RELATIVE POWER [dBc]
−10
This work 130nm 1.2V 22 to 27 50MHz and 160MHz ±0.1dB, 45dBc 214 245 280 314 244 275 310 344 1.6mm2
Ref. [5] 180nm 1.8V 25.3 to 84 (including LNA) 260MHz
Abstract—An analog baseband chain together with an analog to digital converter (ADC) for a Synthetic Aperture Radar (SAR) receiver implemented in 130nm CMOS technology is presented in this paper. The baseband and the ADC are integrated on a single chip, occupying 1.6mm2 (I and Q branch) of active silicon area. The baseband is selectable between 50MHz and 160MHz bandwidth through switches and the voltage gain can be controlled between 22dB and 27dB. The ADC has selectable mode of 5, 6, 7 and 8 bits via control switches. The baseband and the ADC achieve measured spurious-free dynamic range more than 45dBc over the 160MHz band. The circuits, which use a 1.2V supply voltage, dissipates minimum power of 214mW with 50MHz baseband and 5 bit mode ADC, and maximum power of 344mW with 160MHz baseband and 8 bit mode ADC.
C-BAND Balun RF In
Mixer Source follower IDAC Analogue Test Input
Analogue Test Obuf Output
ADC Test Input
50-MHz LPF Obuf
VGA1
160-MHz LPF
ADC
I out
ADC
Q out
VGA2
L-BAND IDAC RF In
X-BAND RF In
This work
Fig. 1.
I. I NTRODUCTION
SAR receiver.
The main advantageous feature of SAR is the insensitivity to weather conditions to process images regardless of day and night. Because of this attractive attribute, SAR is playing a major role in earth observation [1]. The receive antenna consists of multiple parallel sub-apertures to obtain wide swadth, high resolution image. Therefore, it is desirable to realize the receive cells with integrated circuits (ICs) in order to reduce size and power consumption. A high-performance analog baseband chain and an ADC implemented in a 130nm CMOS technology for such a SAR receive cell is described in this paper. The paper is organized as follows. Section II describes the SAR receiver architecture. Section III presents the circuit design of the baseband and section IV explains the ADC circuit design. The measured performances are reported in section V and the conclusions are presented in Section VI.
The quadrature mixer to separate between I/Q baseband is followed by source followers to drive a large parasitic capacitive loads of the following variable gain amplifier 1 (VGA1). DC-offset of the baseband is compensated by a 9bit current-steering digital-to-analog converter (IDAC). Analogue test input and output pins are available to measure the baseband alone, excluding the source follower. In order to measure the ADC as a stand alone structure, the ADC test input is connected after the output buffer (OBUF), just before the ADC. All the blocks in the receiver and the ADC are dc-coupled to each other. The baseband has two available bandwidths, 50MHz and 160MHz, and is connected to the multi-mode (5,6,7 and 8 bits) ADC. The selection of baseband bandwidth and ADC mode are controlled by digital control bits.
II. S YSTEM A RCHITECTURE
III. BASEBAND
The main objective of this work is to integrate a receiver together with an ADC on a single chip. The integrated SAR receiver as shown in Fig. 1 employs a direct conversion architecture. The receiver is able to receive 3 bands, C-band, L-band and X-band which can be selected to be connected to the baseband and ADC one at a time, by using switches controlled by digital control bits. 1 Currently
with Epcos, Finland.
978-1-4577-0704-9/10/$26.00 ©2011 IEEE
A. Variable Gain Amplifier The most important requirement of the VGA is that it should have 1GHz bandwidth over its entire gain tuning range. This ensures that the shape of the filter response is not affected by the VGA. The amplifier was divided into two design blocks: the variable gain stage (VGA1) and a fixed gain stage (VGA2). The first gain stage, shown in Fig. 2, is a variable gain degenerated differential pairs. It uses negative Miller capacitors (NMCs) (Cc1a and Cc1b ) to cancel the parasitic
207
VDD RD1a
RD1b RCM1
RCM2
Cc1a
VCMFB Cc1b
VOUT2 CL1 Realization of Rs Vgate
CL1
Rg1
Rg2
M1b
M1a VIN2+
VIN2Rs Cs Cf M6a
Cf M6b
VCM CMFB Amplifier
Fig. 2.
Schematic of the VGA stage 1.
gate-drain capacitances (Cgd1a and Cgd1b ) of the VGA1. This reduces the input capacitance of the VGA. Since the VGA1 stage and the low-pass filter (LPF) are dc coupled to each other, a common-mode feedback amplifier is used in the stage to stabilize the output dc voltage against process, voltage and temperature (PVT) variations. The voltage gain of VGA1 is [2]:
The filters are synthesized using a lossy prototype and realized as a continuous-time gm-C leapfrog filter, similar as in [3]. The load resistance is removed from the RLC prototype to minimize the loss of the last filter stage. All the poles are realized using Signal Flow Graph (SFG) method, where the structure is as shown in Fig. 3. The 50MHz filter is designed by scaling the gm and C from the 160MHz filter. In order to decrease the power consumption, the gm of 50MHz filter is halved from the value for 160MHz filter. A simple trasconductor structure with no internal poles, suitable for wideband filter as depicted in Fig. 4, is used in the filters. A common-mode feedforward (CMFF) circuit is included to obtain input common-mode rejection, and a common-mode feedback (CMFB) circuit to fix the output common-mode voltage of the transconductor. The approach of the lossy prototype is to accept low DC gain. Hence, the tranconductor is designed to have 26dB of gain. VDD
OUTN
OUTP
INP
INN
INP INP
INN
OUTN
INN
OUTP INP
INN
V_ERROR VSS CMFF
gm1a RD1a Av (s) ≈ − . (1 + gm1a R2s )( wsp2 + 1)( wsp3 + 1)
CMFB
INP INN
(1)
CMFF OUTP OUTN
gm gm
The voltage gain can be varied by changing the value of Rs . Fig. 2 shows that Rs can be implemented as a cascade connection of transistors. Therefore, the gate voltage Vgate of these transistors can be used to change the voltage gain. The next stage, VGA2 is a fixed gain and resistively loaded differential pairs. This VGA2 is connected at the output of the LPF. Here again NMCs (Cc2a and Cc2b ) are used to reduce the input capacitance of this stage. The result of the use of NMCs is that the bandwidth of the VGA is 1GHz over the entire gain tuning range. B. Low-Pass Filter
Fig. 4.
Transcconductor circuit.
Since the transconductor’s gain varies as a result of PVT variations, a negative resistance circuit is designed to control the varied gain [3]. The negative resistance circuit, which is connected at the output of each transconductor, is able to control the DC gain of the transconductors to achieve the desired 26dB in all PVT corners by means of a control voltage. The low-pass filters have embedded gain of 8dB in order to satisfy the overall gain requirement. To achieve this, the first feedforward transconductor is scaled by 4. C. Output Buffer VCM CONTROL CIRCUIT
VDD R1
R2
R2
M4 +
OUTN
M4
R1 OUTP
−
Both the low-pass filters with cutoff frequency of 50MHz and 160MHz are 5th-order Chebyshev prototype with a 0.3dB ripple. The LPF can be selected one at a time through switches controlled by a digital control bit. These LPFs act as antialiasing filters before the analog-to-digital conversion. The passband-edge of both the filters are programmable with 5bit binary weighted switched-capacitor matrices.
VCM R3 INP
M1
M1
R3
IREF
M2 INN
M2
M3
VSS Vout+
Vin+ Vin- k1gm
gm
gm
Fig. 3.
gm
gm
gm
gm
gm
5th-order gm-C low pass filter.
gm
gm
Vout-
Fig. 5.
Output buffer.
The output buffer is designed and connected after the VGA2 to drive the ADC. The OBUF has programmable resistive loads controlled by digital control bits, as shown in Fig. 5, in order to achieve maximum I and Q gain balance. Because the following ADC operates with a 600mV common-mode
208
bias voltage, the OBUF also includes a VCM control circuit at its output. IV. A NALOG
TO
D IGITAL C ONVERTER
pins. Fig. 8 depicts the measured magnitude response of the baseband at different gain setting. The gain tuning range is 5 dB with maximum gain achieved of 27dB.
The block diagram of the 5-8-bit pipelined ADC is presented in Fig. 6. The ADC consists of a flip-around sample and hold (S/H) front-end stage, six 1.5-bit double-sampling pipeline stages and a 2-bit flash back-end stage, similar as in [4]. The pipeline stages are based on conventional 1.5-bit Multiplying Digital-to-Analogue Converters (MDACs). Doublesampling is utilized in the S/H and the MDACs to achieve the sampling rate of 440-MS/s with 220-MHz clock. The ADC employs two-stage (telescopic+common source rail-torail stage) Miller-compensated opamps to have adequate openloop DC-gain and large output linear range. The capacitors and currents of the back-end opamps are scaled down. According to the mode selection (5-8bits) control word, the front-end opamps are shut down to decrease the power consumption. The input switches of the S/H and the first MDAC utilize bootstrapping. Differential pair dynamic comparators are used in the pipeline and the flash stages to achieve low power consumption and fast settling. The clocks are derived from a small-amplitude 440-MHz sinusoidal signal. Square wave is generated with a two-stage clock amplifier and cross-coupled inverters. Comparators and digital parts use the 440-MHz clock whereas the 220-MHz clock for the S/H and the MDACs is created by employing a customized flip-flop-based frequency divider. The output clock and data are taken out of the chip by utilizing low-voltage differential signaling (LVDS) drivers. Necessary reference voltages are generated from an external voltage VAGN D with an on-chip buffer. Div 2
+
VREF+
S/H VIN-
PL PL PL PL PL PL stage stage stage stage stage stage 1.5b 1.5b 1.5b 1.5b 1.5b 1.5b
Magnitude [dB]
26 25
10
Fig. 8.
24 23 40
100
160 200
40 100 Frequency [MHz]
160 200
300
Measured magnitude response with different gain setting.
5
0
−5
Flash stage 2b
−10
−15
−20
Bandwidth range of 160MHz baseband
Bandwidth range of 50MHz baseband
−25
−30
R1
−35
VCM
2 R1 VREF-
2
2
2
2
2
DELAY ALIGNMENT 2 2 2 2
R2
2
2 −40
2
30
50
100
160
200
300
Frequency [MHz]
2
RSD correction 5-8
Fig. 9.
LVDS drivers DOUT7+ DOUT7-
Fig. 6.
15
0
CLKOUT-
VIN+
20
5
LVDS
VAGND -
25
CLKOUT+
Vdd CLKIN-
Micrograph of the baseband and the ADC.
30
Magnitude [dB]
CLKIN+
Fig. 7.
DOUT0+ DOUT0-
Block diagram of the pipelined A/D Converter
V. M EASUREMENT R ESULTS The analog baseband chain with the analog to digital converter was fabricated in a 130nm CMOS process, and bonded directly to a 6-layer PCB. A micrograph of the circuit is shown in Fig. 7. The baseband chain with the ADC occupies 1.6 mm2 of silicon area. The supply voltage is provided separately for the baseband and the ADC such that the power consumption can be measured individually between the two blocks. A test signal is fed in to the test input pins and measured results of the baseband alone are taken from the test output
Measured bandwidth programmability with magnitude scaled at 1.
Fig. 9 shows the programmability of the bandwidth for both of the filters in the baseband. The 160MHz filter has a tuning range of 100MHz while the tuning range for the 50MHz filter is 35MHz in order to compensate PVT variations. The demodulation of the analog signal depends on the gain and phase imbalance between I and Q paths. Using the mixed-mode S-parameters, the I/Q imbalance is obtained. The magnitude imbalance for 160MHz baseband is within ±0.1dB and the phase imbalance is less than 11◦ in the passband, as shown in Fig. 10. The imbalance increases near the corner frequency due to the slight difference in the cutoff frequency between both branches. In order to obtain result for the whole baseband chain and the ADC, the output was measured at the output of the ADC
209
TABLE I T HE M EASURED P ERFORMANCE AND C OMPARISON S UMMARY.
Magnitude [dB]
0.4 0.2 0
Process Supply voltage Voltage gain (dB) BB[*] cutoff frequency IQ mismatch (Gain and Phase) Input-referred noise BB Input compression point ADC sampling rate ADC SNR (8,7,6,5b modes) SFDR[**] Power(mW)[**] 50MHz BB+5 bit ADC 50MHz BB+6 bit ADC 50MHz BB+7 bit ADC 50MHz BB+8 bit ADC 160MHz BB+5 bit ADC 160MHz BB+6 bit ADC 160MHz BB+7 bit ADC 160MHz BB+8 bit ADC Active silicon area [**]
−0.2 −0.4 50
100
160
200
160
200
Frequency [MHz]
Phase [degree]
20 10 0 −10 −20 50
100 Frequency [MHz]
Fig. 10.
I/Q imbalance for 160MHz baseband.
with input fed in to the test input pins. Fig. 11 presents output spectrum measured from the ADC output with a 10-MHz sinusoidal input. Second and third harmonic components are at -48dBc and -45dBc, respectively. Spurious-free dynamic range (SFDR) as a function of frequency is shown in Fig. 12. POWER SPECTRUM 0
RELATIVE POWER [dBc]
−10
This work 130nm 1.2V 22 to 27 50MHz and 160MHz ±0.1dB, 45dBc 214 245 280 314 244 275 310 344 1.6mm2
Ref. [5] 180nm 1.8V 25.3 to 84 (including LNA) 260MHz
