ADPLL Architecture - Semantic Scholar
A Wide Power-Supply Range (0.5V-to-1.3V) Wide Tuning Range (500 MHz-to-8 GHz) AllStatic CMOS ADPLL in 65nm SOI A. V. Rylyakov1, J. A. Tierno1, G. J. English2, D. J. Friedman1, M. Meghelli3 1IBM T.J. Watson Research Center, Yorktown Heights, NY 2IBM Systems and Technology Group, Poughkeepsie, NY 3IBM Systems and Technology Group, Hopewell Junction, NY
ISSCC'2007 Session 9 Paper 1
PLL for Microprocessors and ASICs
Low period jitter needed to increase usable cycle time Lots of programmability needed for ASIC applications ADPLL performance should track other digital circuits over manufacturing corners February 13th 2007
ISSCC'2007 Session 9 Paper 1
1
All Digital PLL (ADPLL) Architecture Divide-by-N Clock Divide-by-M Gate
Clock Divider C1
Ref Clock SCLK Data In Data Out
BB PFD
Early Late
Digital MSB PID Filter LSB
DCO
Vdda
3
DCC Buffer
Σ∆
3
Clock Out
Serial Interface Control and Registers
February 13th 2007
ISSCC'2007 Session 9 Paper 1
2
Self-timed Bang-bang PFD Asynchronous Reset A First A
Ref Clk
Ref Leads (Late) Mutex
Div Leads (Early)
Div Clk B
B First
C C-element February 13th 2007
ISSCC'2007 Session 9 Paper 1
3
Mutual-exclusion Element (Mutex) Metastability filter B First Mutex detects A which of A or B makes a high-tolow transition first. It is reset by A and B B going high
Au Bu
A First AFirst and BFirst are not resolved until Au and Bu differ by at least Vth
These nodes may go metastable
February 13th 2007
ISSCC'2007 Session 9 Paper 1
4
PID Loop Filter Architecture Prop Diff Int
2
+Prop +Prop+Diff -Prop-Diff -Prop
Early/ Late +Int -Int
1 5 0
10
Overflow
OverflowP UnderflowP
5
01
5
00
Underflow 5
February 13th 2007
11
= Proportional constant = Differential constant = Integral constant
5
Fractional Frequency
5
5-bit arithmetic combines with the DCO control to implement 14-bit arithmetic
ISSCC'2007 Session 9 Paper 1
5
3rd Order MASH Σ∆ Cy 1 To Dithered Control
Cy 2 Cy 3 Fractional Frequency From Loop Filter
5
Cy 1 5
5
Cy 2 5
5
Cy 3 5
February 13th 2007
ISSCC'2007 Session 9 Paper 1
6
DCO Inverter Array and Control From Sigma Delta / Loop Filter
01 2 01 2 01 2 01 2 … 01 2 01 2
012 012 012
01 2 01 2 …
012
Inverter Array
February 13th 2007
012
…
From Loop Shift Filter Control
01 2 01 2 …
…
Row Control
Row Override
Dither Control
Phase0 Phase1 Phase2
271 Inverters per phase
Column Control
ISSCC'2007 Session 9 Paper 1
7
DCO Control Loop Filter Underflow/ Overflow
Column Underflow / Overflow
rsel1
csel2
rsel2
…
…
Shift by -1, 0, 1
csel1
Shift by -1, 0, 1
csel0
‘1’ rsel0
‘0’
Row Even/Odd/First/Last Column Control Row Control February 13th 2007
ISSCC'2007 Session 9 Paper 1
8
DCO Array 0
1
2
Some inverters are turned off
Some inverters are turned on
February 13th 2007
0
1
2
0
1
2
0
1
2
0
1
2
Phase 0 Phase 1 Phase 2 Output frequency a function of “filling factor”: fraction of tri-state inverters turned on
ISSCC'2007 Session 9 Paper 1
9
Single Tri-state Inverter with Control rsel j+1
Also performs conversion from VDD to VDDA
rsel j
VDDA
csel i (j even) Not csel i (j odd) Phase (i mod 3) February 13th 2007
Phase ((i+1) mod 3)
ISSCC'2007 Session 9 Paper 1
10
Design for Manufacturing Test
All digital logic is connected to a scan chain, and is LSSD testable (Level Sensitive Scan Design) The only “analog” component, the ring oscillator, can be tested this way as well Checking for locking range can be executed digitally
February 13th 2007
ISSCC'2007 Session 9 Paper 1
11
ADPLL Floorplan, 65 nm SOI 200 µm
Row/Col Control February 13th 2007
DCO
150 µm
Row Control
Σ∆
Clock Divider
Phold PFD
Loop Filter
Column Control ISSCC'2007 Session 9 Paper 1
12
Design Summary Implementation All static standard cell CMOS in 65nm SOI, 2 versions (HVT, RVT FETs). Custom design for tri-state inverter and metastability filter DCO (Digitally Three stage ring oscillator. Tri-state Controlled inverters switched on-off to change gm of Oscillator) the ring stages. 800 frequency steps Loop filter Digital PID filter running at divided frequency. 1 MHz to 20 MHz programmable loop bandwidth Third order MASH Sigma Delta PFD Self-timed, bang-bang PFD Area
200 µm × 150 µm, generously floor-planned layout February 13th 2007
ISSCC'2007 Session 9 Paper 1
13
VHDL Simulations Frequency / Phase acquisition Pink -> reference cycle time White -> output clock cycle time
Zero-crossing data is passed to Matlab for spectral processing
February 13th 2007
ISSCC'2007 Session 9 Paper 1
14
Simulated Phase Noise Plot
February 13th 2007
ISSCC'2007 Session 9 Paper 1
15
Simulated Phase Noise Plot
February 13th 2007
ISSCC'2007 Session 9 Paper 1
16
Closed Loop Phase Noise, 4 GHz, 1.2V, 100ºC 0th Order Σ∆ 1st Order Σ∆ 2nd Order Σ∆
2nd Order Σ∆
February 13th 2007
1st Order Σ∆
ISSCC'2007 Session 9 Paper 1
0th Order Σ∆
17
Period Jitter, 4GHz Output, 0.5 GHz Ref., 1.2V Supply, 100ºC, 2nd Order Σ∆ Mean Tcycle Min Tcycle Max Tcycle Std Dev
250 ps 246 ps 254 ps 0.7 ps
T1
T2
T3
T4
…
Ti
In general, T1≠T2≠… Figure is histogram of measured Ti’s February 13th 2007
ISSCC'2007 Session 9 Paper 1
18
Period Jitter, 1GHz Output, 125 MHz Reference, 0.5V Supply, 100ºC, No Σ∆ Mean Tcycle Min Tcycle Max Tcycle Std Dev
1000 ps 987 ps 1012 ps 3.0 ps
T1
T2
T3
T4
…
Ti
Power dissipation: 1.6 mW February 13th 2007
ISSCC'2007 Session 9 Paper 1
19
Accumulated Jitter (RMS, ps)
N-Cycle Jitter Accumulation, 1.2V, 100ºC, 4GHz, 2nd Order Σ∆ 20 16
Reference Frequency 125MHz 250MHz 500MHz
12 8 4 0
0
1
2
3
4
5
6
7
8
9
10
log2 N February 13th 2007
ISSCC'2007 Session 9 Paper 1
20
Oscillation Frequency (GHz)
DCO Tuning Curves, 100ºC 9 8 7 6 5 4 3 2 1 0
0.3V 100C HVT 0.5V 100C HVT 0.7V 100C HVT 0.9V 100C HVT 1.1V 100C HVT 1.3V 100C HVT 1.3V 25C RVT
0
0.2
0.4
0.6
0.8
1
DCO Fill Factor February 13th 2007
ISSCC'2007 Session 9 Paper 1
21
Test Results Locking range
400 MHz to 8 GHz measured
Power Supply range
0.5 V -> phase lock up to 1 GHz 1.3 V -> phase lock up to 8 GHz (RVT)
Power
1.6 mW / GHz @ 0.5V 8 mW / GHz @ 1.2V
Jitter (RMS)
Period: 0.7 ps Long term: 5 ps Cycle to cycle: 1.1 ps
Phase Noise
-110 dBc/Hz @ 10 MHz, 500 MHz reference, 4 GHz output, 2nd order Σ∆
February 13th 2007
ISSCC'2007 Session 9 Paper 1
22
Conclusion
We designed, simulated and tested an ADPLL in 65 nm SOI The ADPLL is ideally suited for µP and ASIC applications in advanced CMOS technology All static CMOS implementation allows this circuit to work over a wide voltage range (0.5V to 1.3V)
Useful for very low power circuits (1.6 mW @ 1 GHz) Allows for VDD regulation (e.g. from 1.2V down to 0.6V) while still maintaining ASIC level performance
Digital design = Scalable, testable, predictable February 13th 2007
ISSCC'2007 Session 9 Paper 1
23
ISSCC'2007 Session 9 Paper 1
PLL for Microprocessors and ASICs
Low period jitter needed to increase usable cycle time Lots of programmability needed for ASIC applications ADPLL performance should track other digital circuits over manufacturing corners February 13th 2007
ISSCC'2007 Session 9 Paper 1
1
All Digital PLL (ADPLL) Architecture Divide-by-N Clock Divide-by-M Gate
Clock Divider C1
Ref Clock SCLK Data In Data Out
BB PFD
Early Late
Digital MSB PID Filter LSB
DCO
Vdda
3
DCC Buffer
Σ∆
3
Clock Out
Serial Interface Control and Registers
February 13th 2007
ISSCC'2007 Session 9 Paper 1
2
Self-timed Bang-bang PFD Asynchronous Reset A First A
Ref Clk
Ref Leads (Late) Mutex
Div Leads (Early)
Div Clk B
B First
C C-element February 13th 2007
ISSCC'2007 Session 9 Paper 1
3
Mutual-exclusion Element (Mutex) Metastability filter B First Mutex detects A which of A or B makes a high-tolow transition first. It is reset by A and B B going high
Au Bu
A First AFirst and BFirst are not resolved until Au and Bu differ by at least Vth
These nodes may go metastable
February 13th 2007
ISSCC'2007 Session 9 Paper 1
4
PID Loop Filter Architecture Prop Diff Int
2
+Prop +Prop+Diff -Prop-Diff -Prop
Early/ Late +Int -Int
1 5 0
10
Overflow
OverflowP UnderflowP
5
01
5
00
Underflow 5
February 13th 2007
11
= Proportional constant = Differential constant = Integral constant
5
Fractional Frequency
5
5-bit arithmetic combines with the DCO control to implement 14-bit arithmetic
ISSCC'2007 Session 9 Paper 1
5
3rd Order MASH Σ∆ Cy 1 To Dithered Control
Cy 2 Cy 3 Fractional Frequency From Loop Filter
5
Cy 1 5
5
Cy 2 5
5
Cy 3 5
February 13th 2007
ISSCC'2007 Session 9 Paper 1
6
DCO Inverter Array and Control From Sigma Delta / Loop Filter
01 2 01 2 01 2 01 2 … 01 2 01 2
012 012 012
01 2 01 2 …
012
Inverter Array
February 13th 2007
012
…
From Loop Shift Filter Control
01 2 01 2 …
…
Row Control
Row Override
Dither Control
Phase0 Phase1 Phase2
271 Inverters per phase
Column Control
ISSCC'2007 Session 9 Paper 1
7
DCO Control Loop Filter Underflow/ Overflow
Column Underflow / Overflow
rsel1
csel2
rsel2
…
…
Shift by -1, 0, 1
csel1
Shift by -1, 0, 1
csel0
‘1’ rsel0
‘0’
Row Even/Odd/First/Last Column Control Row Control February 13th 2007
ISSCC'2007 Session 9 Paper 1
8
DCO Array 0
1
2
Some inverters are turned off
Some inverters are turned on
February 13th 2007
0
1
2
0
1
2
0
1
2
0
1
2
Phase 0 Phase 1 Phase 2 Output frequency a function of “filling factor”: fraction of tri-state inverters turned on
ISSCC'2007 Session 9 Paper 1
9
Single Tri-state Inverter with Control rsel j+1
Also performs conversion from VDD to VDDA
rsel j
VDDA
csel i (j even) Not csel i (j odd) Phase (i mod 3) February 13th 2007
Phase ((i+1) mod 3)
ISSCC'2007 Session 9 Paper 1
10
Design for Manufacturing Test
All digital logic is connected to a scan chain, and is LSSD testable (Level Sensitive Scan Design) The only “analog” component, the ring oscillator, can be tested this way as well Checking for locking range can be executed digitally
February 13th 2007
ISSCC'2007 Session 9 Paper 1
11
ADPLL Floorplan, 65 nm SOI 200 µm
Row/Col Control February 13th 2007
DCO
150 µm
Row Control
Σ∆
Clock Divider
Phold PFD
Loop Filter
Column Control ISSCC'2007 Session 9 Paper 1
12
Design Summary Implementation All static standard cell CMOS in 65nm SOI, 2 versions (HVT, RVT FETs). Custom design for tri-state inverter and metastability filter DCO (Digitally Three stage ring oscillator. Tri-state Controlled inverters switched on-off to change gm of Oscillator) the ring stages. 800 frequency steps Loop filter Digital PID filter running at divided frequency. 1 MHz to 20 MHz programmable loop bandwidth Third order MASH Sigma Delta PFD Self-timed, bang-bang PFD Area
200 µm × 150 µm, generously floor-planned layout February 13th 2007
ISSCC'2007 Session 9 Paper 1
13
VHDL Simulations Frequency / Phase acquisition Pink -> reference cycle time White -> output clock cycle time
Zero-crossing data is passed to Matlab for spectral processing
February 13th 2007
ISSCC'2007 Session 9 Paper 1
14
Simulated Phase Noise Plot
February 13th 2007
ISSCC'2007 Session 9 Paper 1
15
Simulated Phase Noise Plot
February 13th 2007
ISSCC'2007 Session 9 Paper 1
16
Closed Loop Phase Noise, 4 GHz, 1.2V, 100ºC 0th Order Σ∆ 1st Order Σ∆ 2nd Order Σ∆
2nd Order Σ∆
February 13th 2007
1st Order Σ∆
ISSCC'2007 Session 9 Paper 1
0th Order Σ∆
17
Period Jitter, 4GHz Output, 0.5 GHz Ref., 1.2V Supply, 100ºC, 2nd Order Σ∆ Mean Tcycle Min Tcycle Max Tcycle Std Dev
250 ps 246 ps 254 ps 0.7 ps
T1
T2
T3
T4
…
Ti
In general, T1≠T2≠… Figure is histogram of measured Ti’s February 13th 2007
ISSCC'2007 Session 9 Paper 1
18
Period Jitter, 1GHz Output, 125 MHz Reference, 0.5V Supply, 100ºC, No Σ∆ Mean Tcycle Min Tcycle Max Tcycle Std Dev
1000 ps 987 ps 1012 ps 3.0 ps
T1
T2
T3
T4
…
Ti
Power dissipation: 1.6 mW February 13th 2007
ISSCC'2007 Session 9 Paper 1
19
Accumulated Jitter (RMS, ps)
N-Cycle Jitter Accumulation, 1.2V, 100ºC, 4GHz, 2nd Order Σ∆ 20 16
Reference Frequency 125MHz 250MHz 500MHz
12 8 4 0
0
1
2
3
4
5
6
7
8
9
10
log2 N February 13th 2007
ISSCC'2007 Session 9 Paper 1
20
Oscillation Frequency (GHz)
DCO Tuning Curves, 100ºC 9 8 7 6 5 4 3 2 1 0
0.3V 100C HVT 0.5V 100C HVT 0.7V 100C HVT 0.9V 100C HVT 1.1V 100C HVT 1.3V 100C HVT 1.3V 25C RVT
0
0.2
0.4
0.6
0.8
1
DCO Fill Factor February 13th 2007
ISSCC'2007 Session 9 Paper 1
21
Test Results Locking range
400 MHz to 8 GHz measured
Power Supply range
0.5 V -> phase lock up to 1 GHz 1.3 V -> phase lock up to 8 GHz (RVT)
Power
1.6 mW / GHz @ 0.5V 8 mW / GHz @ 1.2V
Jitter (RMS)
Period: 0.7 ps Long term: 5 ps Cycle to cycle: 1.1 ps
Phase Noise
-110 dBc/Hz @ 10 MHz, 500 MHz reference, 4 GHz output, 2nd order Σ∆
February 13th 2007
ISSCC'2007 Session 9 Paper 1
22
Conclusion
We designed, simulated and tested an ADPLL in 65 nm SOI The ADPLL is ideally suited for µP and ASIC applications in advanced CMOS technology All static CMOS implementation allows this circuit to work over a wide voltage range (0.5V to 1.3V)
Useful for very low power circuits (1.6 mW @ 1 GHz) Allows for VDD regulation (e.g. from 1.2V down to 0.6V) while still maintaining ASIC level performance
Digital design = Scalable, testable, predictable February 13th 2007
ISSCC'2007 Session 9 Paper 1
23
