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Microelectronics Reliability 54 (2014) 1959–1962
Contents lists available at ScienceDirect
Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel
Advanced methods for mechanical and structural characterization of nanoscale materials for 3D IC integration C. Sander ⇑, Y. Standke, S. Niese, R. Rosenkranz, A. Clausner, M. Gall, E. Zschech Fraunhofer Institute for Ceramic Technologies and Systems, Branch Materials Diagnostics IKTS-MD, Maria-Reiche-Str. 2, 01109 Dresden, Germany
a r t i c l e
i n f o
Article history: Received 30 June 2014 Accepted 16 July 2014 Available online 15 August 2014 Keywords: 3D integration Indentation CTE Ultra low-k dielectrics
a b s t r a c t Managing the emerging internal mechanical stress in chips, particularly if they are 3D stacked, is a key task to maintain performance and reliability of microelectronic products. Hence, a strong need of a physics-based simulation methodology emerges. This physics-based simulation, however, requires material parameters with high accuracy. A full-chip analysis can then be performed, balancing the need for local resolution and computing time. The key for an efficient simulation of a 3D stacked IC is a comprehensive database with material properties for multiple scales of the affected materials. Therefore, effective ‘‘composite-type’’ material data for several regions of interest are needed. Advanced techniques to measure FEA- and design-relevant properties such as adhesion properties and effective CTE values are presented. Ó 2014 Elsevier Ltd. All rights reserved.
1. Introduction The semiconductor industry is driven by the demand for processing power and satisfies it by increasing the number of transistors on the die. This rule is known as ‘‘Moore’s law’’. The latest approach to keep the pace of this law leads to 3D-stacks of several dies, Fig. 1. Due to this fact, the intrinsic stress in the dielectrics increases and crack growth is a main reliability issue of modern low-k dielectrics in the back-end-of-line (BEoL). Also because of physical limitations in the manufacturing process, the need for new materials is ubiquitous. With a mixture of different materials, the thermal stress normally rises due to different coefficients of thermal expansion (CTE). Quantifying the material properties of those materials, such as effective Young’s modulus and adhesion, is an important duty, as the integration of new microprocessor designs is done by simulations that need a highly reliable input. 2. Nanoscale CTE measurements To check the accuracy of future full die FEA simulations, an insitu technique with very high local resolution to determine thermal material properties in a stacked die was developed. In this case, the intent was to examine the composite CTE of a mesh of dielectrics and Cu in the BEoL of a 3D integrated die. The region of interest was excavated with the Focused Ion Beam technique (FIB), leading to two free-standing cantilever beams, Fig. 4. An ⇑ Corresponding author. E-mail address: [email protected] (C. Sander). http://dx.doi.org/10.1016/j.microrel.2014.07.124 0026-2714/Ó 2014 Elsevier Ltd. All rights reserved.
FEA-simulation was done to prove the concept and estimate the scale of expansion, Fig. 3. The measurements were observed and recorded by a Zeiss NVision 40 SEM with high spatial resolution. The thermal load was provided by a custom heating stage inside the vacuum chamber. The temperature range attained was between 50 °C and 200 °C. High quality images that can provide the needed nm-resolution, demand a minimal thermal drift of the sample and the stage. The power supply was closed loop controlled by a custom LabVIEW VI for temperatures with changing rates less than ±0.1 °C per minute, Fig. 2. These temperature shifts were acceptable for the micrographs taken with the SEM. After the experiment, the gathered data from the thermocouple and the SEM were correlated by the time code and the linear CTE is given by aL = 1/L (dL/dT). The gap between the bars was measured with an ImageJ routine as a function of temperature, while the well-known expansion of the 50 lm thick Silicon substrate was added to the gap length, because the fixed ends of the bars were displaced by the movement of the substrate. This effect can be clearly seen in the conducted FEA-simulation, see Fig. 3. The experiment was repeated on different, well-defined locations on the die map. The Cu volume density was obtained from the original CAD design file of the BEoL stack. The CTE values were determined for BEoL stacks with different Cu line structure and density. The CTE value clearly changes with Cu density. To demonstrate the impact of the BEoL-design, a simplified FEM-model of a fragment from the CTE-cantilever was modeled with an over-exaggerated Cu-line alignment. All Cu-lines were randomly distributed and aligned in y-direction only, see Fig. 5.
1960
C. Sander et al. / Microelectronics Reliability 54 (2014) 1959–1962 Table 1 CTE variation corresponding to Cu volume density and direction in different spots. BEoL (x-/y-direction)
1x
2x
3x
4x
4y
5x
6x
CTE (ppm/K) Cu (%)
6.6 17.8
6.1 17.6
5.9 18.4
5.6 18.3
8.0 18.3
7.1 23.8
11 23.8
Fig. 3. FEA-simulation of the CTE experiment. The beams extend during heating towards each other, while the Silicon substrate pulls in the other direction.
Fig. 1. Schematic of the examined 3D stack [1,2].
The simulation parameters were identical to the real experiment and showed very good correlation. Depending on the main line direction, CTE values of 13 ppm/K for the y-direction and 5.5 ppm/K for the x-direction respectively are reasonable and match our measurements in Table 1. 3. Nanoindentation wedge test Adhesion properties of low-k and ultra-low-k (ULK) dielectrics are often used to compare deposition processes, as dielectrics tend to crack with further minimization and lower k-values. The Nanoindentation technique is a fairly new method to derive the energy release rate Gc [3]. While the experiment itself needs no further
Fig. 4. SEM micrograph of two FIB-cut bars in a deprocessed 3D-die-stack for CTE measurements.
preparation, the analysis of the indented crack area is important to calculate Gc. The procedure consists of the wedge indent, depicted in Fig. 7, and the following height mapping by scanning the crack with a Berkovich indenter tip. The height map is processed by an ImageJ routine that computes the cracked area. Fig. 6 shows a FIB cross
Fig. 2. Diagram of the heating stage temperature measured with a K-type thermocouple versus the voltage as the control parameter in the closed loop control. The left graph shows the temperature and voltage during the optimizing process of the PID control parameters. The graph on the right side shows the condition after the optimization. The SEM micrographs were taken with temperature conditions at least as stable as shown here.
C. Sander et al. / Microelectronics Reliability 54 (2014) 1959–1962
1961
Fig. 5. FEA simulation of a simplified 4 4 1.5 lm3 block of the CTE bars (A). (B) and (C) show the resulting deformation in x- and y-direction respectively for a temperature of 200 °C.
Fig. 6. Cross-section SEM image of an indented ULK material showing the crack propagation. The location of the cross section prepared using a FIB is indicated in the top down view on the left SEM micrograph.
Fig. 7. Image processing result with the calculated area.
section of the indented thin film. The topography matches the height increase surrounding the indent. The next step is the development of a new height-profiling method to discard the lengthy indenter mapping. This combination of a fast experiment and measurement leads to a reliable, easy and time-saving technique. Because of the exceptional correlation of this method compared to traditional adhesion measurement techniques and because of smaller errors, this technique has the potential to be the next standard for inline adhesion measurements. The four-point-bending technique (FPB or 4 PB) and the double cantilever beam test (DCB) are well-known procedures for the adhesion measurement of thin films. Both are reliable but have shortcomings in experimental yield and speed of the test and preparation. A significant advantage of the DCB test is the local resolution of the gathered measurements that allow correlating the measured Gc values with the cracked surface. The traditional experiment is based on the compliance method and gives only 10–15 data points per measurement with a high inaccuracy in the crack length measurement [4]. For that reason, an opticalbased in-situ crack length measuring method has been developed
Fig. 8. Comparison of the wedge indentation and four-point-bending method.
that gives thousands of data points with high accuracy [5]. The same experimental setup is used to determine crack length velocities and asymmetric crack propagation. This item is the main issue in the application of FPB testing, and can lead to unusable measurements without proper plateau areas. Therefore, an opticalbased setup was adapted and enhanced. Compared to the standard FPB test, the results of the wedge indentation method show the same trend. Fig. 8 shows results for a series of ULK films with a k value of 2.55 on varying substrates. The 2.55 noA film had no adhesion layer but was deployed on an intermediate film. The 2.55 Si film had an adhesion layer but was deployed on Silicon directly, while the 2.55 film had an adhesion layer as well as an intermediate layer on top of the Silicon substrate.
1962
C. Sander et al. / Microelectronics Reliability 54 (2014) 1959–1962
4. Conclusion
References
This paper reviews various characterization methods for nanoscale materials employed in 3D-integration flows. The specific need of an accurate material database for 3D-stacked dies and full-system simulation methodology is highlighted, and advanced characterization techniques are presented to obtain highly reliable materials data.
[1] Sukharev V, Zschech E. AIP Conf Proc 2011;1378:21. [2] Nakamoto M, Radojcic R, Zhao W, Dasarapu VK, Karmarkar AP, Xu XP. IEEE Custom Integr Circ 2010. [3] Yeap KB. Dissertation, National University of Singapore; 2010. [4] Chumakov D, Lindert F, Lehr MU, Grillberger M, Zschech E. IEEE Trans Semicond Manuf 2009;22(4). [5] Sander C, Hecker M, Grillberger M, Lehr MU. In: 11th Workshop on stressinduced phenom., Dresden; 2010. p. 25.
Acknowledgment The financial support of the Sematech/SRC 3D Enablement Center in Albany, NY, USA is greatly appreciated.
Contents lists available at ScienceDirect
Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel
Advanced methods for mechanical and structural characterization of nanoscale materials for 3D IC integration C. Sander ⇑, Y. Standke, S. Niese, R. Rosenkranz, A. Clausner, M. Gall, E. Zschech Fraunhofer Institute for Ceramic Technologies and Systems, Branch Materials Diagnostics IKTS-MD, Maria-Reiche-Str. 2, 01109 Dresden, Germany
a r t i c l e
i n f o
Article history: Received 30 June 2014 Accepted 16 July 2014 Available online 15 August 2014 Keywords: 3D integration Indentation CTE Ultra low-k dielectrics
a b s t r a c t Managing the emerging internal mechanical stress in chips, particularly if they are 3D stacked, is a key task to maintain performance and reliability of microelectronic products. Hence, a strong need of a physics-based simulation methodology emerges. This physics-based simulation, however, requires material parameters with high accuracy. A full-chip analysis can then be performed, balancing the need for local resolution and computing time. The key for an efficient simulation of a 3D stacked IC is a comprehensive database with material properties for multiple scales of the affected materials. Therefore, effective ‘‘composite-type’’ material data for several regions of interest are needed. Advanced techniques to measure FEA- and design-relevant properties such as adhesion properties and effective CTE values are presented. Ó 2014 Elsevier Ltd. All rights reserved.
1. Introduction The semiconductor industry is driven by the demand for processing power and satisfies it by increasing the number of transistors on the die. This rule is known as ‘‘Moore’s law’’. The latest approach to keep the pace of this law leads to 3D-stacks of several dies, Fig. 1. Due to this fact, the intrinsic stress in the dielectrics increases and crack growth is a main reliability issue of modern low-k dielectrics in the back-end-of-line (BEoL). Also because of physical limitations in the manufacturing process, the need for new materials is ubiquitous. With a mixture of different materials, the thermal stress normally rises due to different coefficients of thermal expansion (CTE). Quantifying the material properties of those materials, such as effective Young’s modulus and adhesion, is an important duty, as the integration of new microprocessor designs is done by simulations that need a highly reliable input. 2. Nanoscale CTE measurements To check the accuracy of future full die FEA simulations, an insitu technique with very high local resolution to determine thermal material properties in a stacked die was developed. In this case, the intent was to examine the composite CTE of a mesh of dielectrics and Cu in the BEoL of a 3D integrated die. The region of interest was excavated with the Focused Ion Beam technique (FIB), leading to two free-standing cantilever beams, Fig. 4. An ⇑ Corresponding author. E-mail address: [email protected] (C. Sander). http://dx.doi.org/10.1016/j.microrel.2014.07.124 0026-2714/Ó 2014 Elsevier Ltd. All rights reserved.
FEA-simulation was done to prove the concept and estimate the scale of expansion, Fig. 3. The measurements were observed and recorded by a Zeiss NVision 40 SEM with high spatial resolution. The thermal load was provided by a custom heating stage inside the vacuum chamber. The temperature range attained was between 50 °C and 200 °C. High quality images that can provide the needed nm-resolution, demand a minimal thermal drift of the sample and the stage. The power supply was closed loop controlled by a custom LabVIEW VI for temperatures with changing rates less than ±0.1 °C per minute, Fig. 2. These temperature shifts were acceptable for the micrographs taken with the SEM. After the experiment, the gathered data from the thermocouple and the SEM were correlated by the time code and the linear CTE is given by aL = 1/L (dL/dT). The gap between the bars was measured with an ImageJ routine as a function of temperature, while the well-known expansion of the 50 lm thick Silicon substrate was added to the gap length, because the fixed ends of the bars were displaced by the movement of the substrate. This effect can be clearly seen in the conducted FEA-simulation, see Fig. 3. The experiment was repeated on different, well-defined locations on the die map. The Cu volume density was obtained from the original CAD design file of the BEoL stack. The CTE values were determined for BEoL stacks with different Cu line structure and density. The CTE value clearly changes with Cu density. To demonstrate the impact of the BEoL-design, a simplified FEM-model of a fragment from the CTE-cantilever was modeled with an over-exaggerated Cu-line alignment. All Cu-lines were randomly distributed and aligned in y-direction only, see Fig. 5.
1960
C. Sander et al. / Microelectronics Reliability 54 (2014) 1959–1962 Table 1 CTE variation corresponding to Cu volume density and direction in different spots. BEoL (x-/y-direction)
1x
2x
3x
4x
4y
5x
6x
CTE (ppm/K) Cu (%)
6.6 17.8
6.1 17.6
5.9 18.4
5.6 18.3
8.0 18.3
7.1 23.8
11 23.8
Fig. 3. FEA-simulation of the CTE experiment. The beams extend during heating towards each other, while the Silicon substrate pulls in the other direction.
Fig. 1. Schematic of the examined 3D stack [1,2].
The simulation parameters were identical to the real experiment and showed very good correlation. Depending on the main line direction, CTE values of 13 ppm/K for the y-direction and 5.5 ppm/K for the x-direction respectively are reasonable and match our measurements in Table 1. 3. Nanoindentation wedge test Adhesion properties of low-k and ultra-low-k (ULK) dielectrics are often used to compare deposition processes, as dielectrics tend to crack with further minimization and lower k-values. The Nanoindentation technique is a fairly new method to derive the energy release rate Gc [3]. While the experiment itself needs no further
Fig. 4. SEM micrograph of two FIB-cut bars in a deprocessed 3D-die-stack for CTE measurements.
preparation, the analysis of the indented crack area is important to calculate Gc. The procedure consists of the wedge indent, depicted in Fig. 7, and the following height mapping by scanning the crack with a Berkovich indenter tip. The height map is processed by an ImageJ routine that computes the cracked area. Fig. 6 shows a FIB cross
Fig. 2. Diagram of the heating stage temperature measured with a K-type thermocouple versus the voltage as the control parameter in the closed loop control. The left graph shows the temperature and voltage during the optimizing process of the PID control parameters. The graph on the right side shows the condition after the optimization. The SEM micrographs were taken with temperature conditions at least as stable as shown here.
C. Sander et al. / Microelectronics Reliability 54 (2014) 1959–1962
1961
Fig. 5. FEA simulation of a simplified 4 4 1.5 lm3 block of the CTE bars (A). (B) and (C) show the resulting deformation in x- and y-direction respectively for a temperature of 200 °C.
Fig. 6. Cross-section SEM image of an indented ULK material showing the crack propagation. The location of the cross section prepared using a FIB is indicated in the top down view on the left SEM micrograph.
Fig. 7. Image processing result with the calculated area.
section of the indented thin film. The topography matches the height increase surrounding the indent. The next step is the development of a new height-profiling method to discard the lengthy indenter mapping. This combination of a fast experiment and measurement leads to a reliable, easy and time-saving technique. Because of the exceptional correlation of this method compared to traditional adhesion measurement techniques and because of smaller errors, this technique has the potential to be the next standard for inline adhesion measurements. The four-point-bending technique (FPB or 4 PB) and the double cantilever beam test (DCB) are well-known procedures for the adhesion measurement of thin films. Both are reliable but have shortcomings in experimental yield and speed of the test and preparation. A significant advantage of the DCB test is the local resolution of the gathered measurements that allow correlating the measured Gc values with the cracked surface. The traditional experiment is based on the compliance method and gives only 10–15 data points per measurement with a high inaccuracy in the crack length measurement [4]. For that reason, an opticalbased in-situ crack length measuring method has been developed
Fig. 8. Comparison of the wedge indentation and four-point-bending method.
that gives thousands of data points with high accuracy [5]. The same experimental setup is used to determine crack length velocities and asymmetric crack propagation. This item is the main issue in the application of FPB testing, and can lead to unusable measurements without proper plateau areas. Therefore, an opticalbased setup was adapted and enhanced. Compared to the standard FPB test, the results of the wedge indentation method show the same trend. Fig. 8 shows results for a series of ULK films with a k value of 2.55 on varying substrates. The 2.55 noA film had no adhesion layer but was deployed on an intermediate film. The 2.55 Si film had an adhesion layer but was deployed on Silicon directly, while the 2.55 film had an adhesion layer as well as an intermediate layer on top of the Silicon substrate.
1962
C. Sander et al. / Microelectronics Reliability 54 (2014) 1959–1962
4. Conclusion
References
This paper reviews various characterization methods for nanoscale materials employed in 3D-integration flows. The specific need of an accurate material database for 3D-stacked dies and full-system simulation methodology is highlighted, and advanced characterization techniques are presented to obtain highly reliable materials data.
[1] Sukharev V, Zschech E. AIP Conf Proc 2011;1378:21. [2] Nakamoto M, Radojcic R, Zhao W, Dasarapu VK, Karmarkar AP, Xu XP. IEEE Custom Integr Circ 2010. [3] Yeap KB. Dissertation, National University of Singapore; 2010. [4] Chumakov D, Lindert F, Lehr MU, Grillberger M, Zschech E. IEEE Trans Semicond Manuf 2009;22(4). [5] Sander C, Hecker M, Grillberger M, Lehr MU. In: 11th Workshop on stressinduced phenom., Dresden; 2010. p. 25.
Acknowledgment The financial support of the Sematech/SRC 3D Enablement Center in Albany, NY, USA is greatly appreciated.
