AEIOU(VM) Any Vowel Will Do
AEIOU(VM) ANY VOWEL WILL DO
OVMWORLD Presentation David Murray CTO Duolog Technologies 4-Jul-10
1
SoC Design Trends Exploding Cost & Complexity • >3bn transistors • Development: $50m - $100m • Re-spin: $5-10m + 6 months • Advanced verification flows • Increasing SW content
IP-based Design • Higher levels of abstraction • Extensive IP use & reuse
Early Software development
Source : SNUG2009
SoC Integration
Reusable Hardware Components
Hardware Development Cycle HW Integration Verification
HW/SW Integration
Software Development Cycle
Virtual modelling HW/SW Validation HW Prototyping
Firmware/ Integration OS Integration
Physical Design
Middleware
Fabrication
Application Dev
SOLUTON Earlier + Robust HW/SW integration
Reusable Software Components
HW/SW Interface (HW View)
IP Block
Register Select Signals Registers Processor Bus Interface
State Machine + Address Decoder + Write Data
Register Register
Logic block
Register
Write data Read Data Multiplexer bitfield read data from Logic
Functional Interfaces
HW/SW Interface (HW View) Memory Mapped Register Write Data
To HW
Decode Logic
Clock Enable
Processor Bus Interface
Address Enable Control
Transaction is valid for this block AND Address = Register Offset AND Transaction is a WRITE
Reset
Read Data Multiplex logic
Read Data
If Address = Register offset then Select this read data Else if Address = ... ... ... End if
Other read data
HW/SW Interface (HW View) interrupt_status_register Interrupt From HW SET
CLR Processor Bus Interface
Address Enable Control
Transaction is valid for this block AND Address = Interrupt Status Register AND Transaction is a READ
Read Data
HW/SW Interface (SW View)
Processor Bus Interface
MEMORY_MAP
IP Block
Memory Map
Memory Map Offset
4-Jul-10
7
Register Definition Bitfield Offset
Register name Bitfields
Bitfield Access Type e.g. RO-R2C
RX_FIFO_CTRL 31
30
28
26
25
24
23
22
21
20
19
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
RO
RO
RO
RO
RO
RO
RO RO RO
RO
FIFO_DEPTH
FIFO_ALARM
EN_SYNCH PARITY ERROR_CHK
F_EXTEND
4-Jul-10
16
FIFO_ENABLE
FIFO_CTRL
Bitfield Width
17
FIFO_RESET
RO
18
OE_ERROR
RW
27
Status
RO
29
0
FIFO_RESET
1
FIFIO_CLEAR
2
FIFO_TX_EN
3
FIFO_RX_EN
0
Bitfield Enumerated Values
8
Modelling the system
23
RO
22
21
20
19
18
17
RO
16
RO
15
14
RO
13
RO
12
11
10
9
8
7
6
RO
RO
5
4
3
2
RO
RO
RO
1
0
RO
F_EXTEND
MEMORY_MAP
24
EN_SYNCH PARITY ERROR_CHK
MEMORY_MAP
25
FIFO_ALARM
SPI
26
FIFO_DEPTH
0x5000
UART
27
FIFO_RESET
0xF000000
Graphics Sub-system
0x4000
28
RW
Status
0x8000000
Peripheral Sub-system
0x3000
29
OE_ERROR
Memory Sub-system
USB
30
RO
FIFO_RESET
0x000000
RX_FIFO_CTRL 31
FIFO_CTRL
4-Jul-10
MEMORY_MAP
Sub-Systems Processor(s)
Registers
IP Blocks
9
System Processors
Processor 3
MEMORY_MAP
Processor 2
MEMORY_MAP
Processor 1
MEMORY_MAP
System Instantiated Sub-Systems
00000 1C0000 4FFFF
000000 800000
Leaf IPs
8FFFFF
00000 1C0000 4FFFF
Memory Maps
4-Jul-10
10
Traditional HW/SW Interface Design Specification
IP-LEVEL Hardware D/V
SYSTEM-LEVEL Hardware D/V
SYSTEM-LEVEL Software D/V
Feedback
Feedback
HW Design
interpret
interpret SYSTEM RTL Design
Firmware Libraries
Register interpret Specify
Document interpret
Firmware testcases RTL Test
SYSTEM Test
Feedback
interpret interpret
Silicon testcases interpret
Feedback
Refinement points/Milestones
4-Jul-10
11
Compressed Design Cycle Design Specification
HW Design
IP-LEVEL Hardware D/V
interpret Feedback
RTL Test
interpret Feedback SYSTEM RTL Design
Register interpret Specify
Document
SYSTEMLEVEL Hardware D/V
SYSTEM Test interpret
Feedback Firmware Libraries interpret
interpret
SYSTEM-LEVEL Software D/V Firmware testcases
interpret Silicon testcases Feedback
4-Jul-10
12
HW/SW Interface (Verification) Specification View
SW View
HW View
Verification View
Verification Evolution New Verification thinking User Environment Applications Class Library HVL Simulation Environment
• New verification environment -
OOV Scoreboard/Checkers Constrained random Coverage driven Monitors/Drivers – TLM
• Emergence of HW verification languages -
Specman ‘e’ Vera SystemC/C++ SystemVerilog
High-level Verification Methodology
User Environment Applications Class Library HVL Simulation Environment
A high-level verification methodology consists of an HVL running in a simulation environment which can interact with the RTL. The HVL’s object-oriented infrastructure can be organized and extended to deliver high levels of productivity for specific user applications. The key mechanisms are stimulus generation, monitoring and coverage. Bailey/Martin 2007
High-level Verification Methodology
User Environment Applications Class Library HVL Simulation Environment
Evolution of the Verification methodologies (VM) • A-E-I-O-U(VM) where I = V
Verification IP Reuse Application oriented User Capability
HW/SW VM Applications
eRM VR_AD VMM RAL OVM Register Package UVM Register Package
: Methodologies improve : How to keep aligned … • To new methodologies? • Across different flows?
Standardize-Centralize-Synchronise STANDARDIZE HW Interface : interfaces & ports SW Interface : registers, memories, memory maps
IP
CENTRALIZE Correct Data Coherent specification Central repository
SYNCRONIZE Auto-generated design source HW/SW Design/Verification Specification/Implementation KEEPING TEAMS ALIGNED 4-Jul-10
18
Standardize-Centralize-Synchronise
DEMO (Using Socrates to Auto-generate any OVM/UVM Implementations
4-Jul-10
19
LCD Controller
WB_Master
WB_Slave
LCD Controller
External LCD
System
4-Jul-10
20
IP Verification Environment based on OVM OVM Environment Shadow Registers
Model Coverage
Register Map
Test Test Test Test Case Test Case Case Case Case
Generic Testcases
Scoreboard
Global Monitor
Test Test Test Test Case Test Case Case Case Case
LCD_WRAP WB Library OVC
Global Bus Monitor
Sequence Sequence r Sequencer r Class wb_slave_sequence Class r wb_slave_sequence class r wb_slave_ag class wb_slave_agent
Standard Verification Components
WB_Master OVC
Sequence Sequence r Sequencer r Class wb_slave_sequence Class r wb_slave_sequence class r wb_slave_ag class wb_slave_agent
WB Library OVC
WB_Slave OVC
Master Agent [n] Master Agent [1] Driver MasterAgent [0] Driver class Driver wb_slave_driver class wb_slave_driver
Monitor Monitor class wb_slave_monitor class Monitor wb_slave_monitor
wb_slave_driver class wb_slave_driver
Monitor Monitor class wb_slave_monitor class Monitor wb_slave_monitor
Global Bus Monitor
Sequence Sequence r Sequencer r Class wb_slave_sequence Class r wb_slave_sequence class r wb_slave_ag class wb_slave_agent
Sequence Sequence r Sequencer r Class wb_slave_sequence Class r wb_slave_sequence class r wb_slave_ag class wb_slave_agent
User Verification Component
WB_Master
Slave Agent [n] Slave Agent [1] Driver Slave Agent [0] Driver class Driver
WB_Slave
Master Agent [n] Master Agent [1] Driver MasterAgent [0] Driver class Driver wb_slave_driver class wb_slave_driver
Monitor Monitor class wb_slave_monitor class Monitor wb_slave_monitor
Slave Agent [n] Slave Agent [1] Driver Slave Agent [0] Driver class Driver
LCD Controller
External LCD
wb_slave_driver class wb_slave_driver
Monitor
LCD OVC
Monitor class wb_slave_monitor class Monitor wb_slave_monitor
System System OVC
User Verification Component Ports & Interfaces Registers
DUT
SystemVerilog Wrapper
Auto-generation of IP OVM infrastructure Bitwise
Cadence ncsim/Mentor Questasim Simulator/OVM
Duolog Socrates Package Interfaces + Verification Attributes
LCD
Package Registers + Verification Attributes
OVM Environment Shadow Registers
Import
Test Test Test Test Case Test Case Case Case Case
G
(Verilog)
Generic Testcases
Global Monitor
Test Test Test Test Case Test Case Case Case Case
LCD_WRAP WB Library OVC
Global Bus Monitor
Sequence Sequence r Sequencer r Class wb_slave_sequence Class r wb_slave_sequence class r wb_slave_ag class wb_slave_agent
WB_Master OVC
Sequence Sequence r Sequencer r Class wb_slave_sequence Class r wb_slave_sequence class wb_slave_ag class wb_slave_agent
r
WB Library OVC
WB_Slave OVC
Interface Definitions
Model Coverage
Register Map
Generate OVM
Scoreboard
Capture
Master Agent [n] Master Agent [1] Driver MasterAgent [0] Driver class Driver wb_slave_driver class wb_slave_driver
Monitor Monitor class wb_slave_monitor class Monitor wb_slave_monitor
Slave Agent [n] Slave Agent [1] Driver Slave Agent [0] Driver class Driver
WB_Master
wb_slave_driver class wb_slave_driver
Monitor Monitor class wb_slave_monitor class Monitor wb_slave_monitor
Global Bus Monitor
Sequence Sequence r Sequencer r Class wb_slave_sequence Class r wb_slave_sequence class r wb_slave_ag class wb_slave_agent
Sequence Sequence r Sequencer r Class wb_slave_sequence Class r wb_slave_sequence class r wb_slave_ag class wb_slave_agent
Master Agent [n] Master Agent [1] Driver MasterAgent [0] Driver class Driver
WB_Slave
wb_slave_driver class wb_slave_driver
Monitor Monitor class wb_slave_monitor class Monitor wb_slave_monitor
Slave Agent [n] Slave Agent [1] Driver Slave Agent [0] Driver class Driver
LCD Controller
External LCD
wb_slave_driver class wb_slave_driver
Monitor Monitor class wb_slave_monitor class Monitor wb_slave_monitor
System System OVC
WB Library OVC
Global Bus Monitor class wb_monitor
WB Library OVC
Master Agent [n]Global Bus Monitor [1] Driver MasterAgent [0] Driver
Master Agent class wb_monitor
Sequence Sequence r
class Driver Sequencer r wb_slave_driver class Agent [n] Master class wb_slave_driver Master Agent Global [1] Bus Monitor wb_master_driver Monitor wb_slave_sequence Driver Class Sequence MasterAgent [0] class Monitor wb_monitor r class wb_slave_sequence Driver Sequence r class class class wb_master_sequencer r Driver class Monitor Sequencer rwb_slave_monitor wb_slave_driver wb_slave_ag class wb_slave_monitor class class class wb_slave_driver wb_slave_agent wb_master_monitor class wb_master_agent Class Master Agent [n] wb_master_driver Monitor wb_slave_sequence Class Master Agent [1] Monitor r class wb_slave_sequence Driver Sequence Slave Agent [n] MasterAgent [0] class class wb_master_sequencer wb_slave_monitor r class Monitor Driver Sequence r Agent Slave [1] class class wb_slave_ag class wb_slave_monitor Driver Sequencer Driver Sequence r Agent wb_slave_agent Slave [0] wb_slave_driver wb_master_monitor class wb_master_agent class Driver Sequence r class wb_slave_driver class Class Driver Sequencer r wb_master_driver Monitor wb_slave_driver class Agent [n] wb_slave_sequence Class Slave class Monitor rwb_slave_driver class wb_slave_sequence Class Slave Agent [1] wb_slave_driver class Monitor class wb_master_sequencer wb_slave_monitor r class Monitor wb_slave_sequence Driver Class Sequence Slave Agent [0] class wb_slave_ag class Monitor wb_slave_monitor r class wb_slave_sequence Driver Sequence r wb_slave_agent Monitor wb_master_monitor class class Sequencer wb_master_agent class wb_slave_sequencer r class class Driver rwb_slave_monitor wb_slave_driver wb_slave_ag class wb_slave_monitor class class class wb_slave_driver wb_slave_agent wb_slave_monitor class wb_slave_agent Class Slave Agent [n] wb_slave_driver Monitor wb_slave_sequence Class Slave Agent [1] Monitor r wb_slave_sequence Driver Sequence class Slave Agent [0] class class wb_slave_sequencer wb_slave_monitor r class Monitor Driver Sequence r wb_slave_ag class wb_slave_monitor class class Driver Sequencer r wb_slave_agent wb_slave_monitor class wb_slave_agent wb_slave_driver class class wb_slave_driver Class wb_slave_driver Monitor wb_slave_sequence Class Monitor r class wb_slave_sequence class class wb_slave_sequencer wb_slave_monitor r class Monitor wb_slave_ag class wb_slave_monitor class wb_slave_agent wb_slave_monitor class wb_slave_agent
WB Library OVC Class
LCD Specification
OVC Libraries
OVM SystemVerilog code & scripts
LCD OVC
Auto-generation of IP OVM infrastructure Standard sequence
User sequence
Register Sequencer
• •
RDB updater & checker
OVC
Analysis port
Sequencer
Register Verification Environment
•
WB-S LCD Controller
100 % autogeration with the possibility of user extensions
Sending 32 bit vector sequences to the driver
Register sequencer: •
Monitor
Modular and reusable Bus protocol changes (WB -> APB) doesn’t require any changes in the register verification part
OVC Master sequencer: •
Register Map and DB Driver
Register verification is separated from the standard slave OVC:
Executing sequences from sequence library (register data) TLM connection to the OVC master sequencer using adaptor sequences
Monitor sending the read/write data to the analysis port RDB checker & updater : •
Link between bus activity and RDB
VM attributes
COMPONENT
REGISTERS
REGISTER & BITFIELDS
REGISTER ATTRIBUTES
Conclusion
HW/SW interface requires critical verification attention HW/SW interface modelling is key to synchronizing teams HW/SW interface modelling is key to allowing smoother VM transition Demoed Auto-generation of OVM/UVM from a single source Looking forward to the next transition 4-Jul-10
25
OVMWORLD Presentation David Murray CTO Duolog Technologies 4-Jul-10
1
SoC Design Trends Exploding Cost & Complexity • >3bn transistors • Development: $50m - $100m • Re-spin: $5-10m + 6 months • Advanced verification flows • Increasing SW content
IP-based Design • Higher levels of abstraction • Extensive IP use & reuse
Early Software development
Source : SNUG2009
SoC Integration
Reusable Hardware Components
Hardware Development Cycle HW Integration Verification
HW/SW Integration
Software Development Cycle
Virtual modelling HW/SW Validation HW Prototyping
Firmware/ Integration OS Integration
Physical Design
Middleware
Fabrication
Application Dev
SOLUTON Earlier + Robust HW/SW integration
Reusable Software Components
HW/SW Interface (HW View)
IP Block
Register Select Signals Registers Processor Bus Interface
State Machine + Address Decoder + Write Data
Register Register
Logic block
Register
Write data Read Data Multiplexer bitfield read data from Logic
Functional Interfaces
HW/SW Interface (HW View) Memory Mapped Register Write Data
To HW
Decode Logic
Clock Enable
Processor Bus Interface
Address Enable Control
Transaction is valid for this block AND Address = Register Offset AND Transaction is a WRITE
Reset
Read Data Multiplex logic
Read Data
If Address = Register offset then Select this read data Else if Address = ... ... ... End if
Other read data
HW/SW Interface (HW View) interrupt_status_register Interrupt From HW SET
CLR Processor Bus Interface
Address Enable Control
Transaction is valid for this block AND Address = Interrupt Status Register AND Transaction is a READ
Read Data
HW/SW Interface (SW View)
Processor Bus Interface
MEMORY_MAP
IP Block
Memory Map
Memory Map Offset
4-Jul-10
7
Register Definition Bitfield Offset
Register name Bitfields
Bitfield Access Type e.g. RO-R2C
RX_FIFO_CTRL 31
30
28
26
25
24
23
22
21
20
19
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
RO
RO
RO
RO
RO
RO
RO RO RO
RO
FIFO_DEPTH
FIFO_ALARM
EN_SYNCH PARITY ERROR_CHK
F_EXTEND
4-Jul-10
16
FIFO_ENABLE
FIFO_CTRL
Bitfield Width
17
FIFO_RESET
RO
18
OE_ERROR
RW
27
Status
RO
29
0
FIFO_RESET
1
FIFIO_CLEAR
2
FIFO_TX_EN
3
FIFO_RX_EN
0
Bitfield Enumerated Values
8
Modelling the system
23
RO
22
21
20
19
18
17
RO
16
RO
15
14
RO
13
RO
12
11
10
9
8
7
6
RO
RO
5
4
3
2
RO
RO
RO
1
0
RO
F_EXTEND
MEMORY_MAP
24
EN_SYNCH PARITY ERROR_CHK
MEMORY_MAP
25
FIFO_ALARM
SPI
26
FIFO_DEPTH
0x5000
UART
27
FIFO_RESET
0xF000000
Graphics Sub-system
0x4000
28
RW
Status
0x8000000
Peripheral Sub-system
0x3000
29
OE_ERROR
Memory Sub-system
USB
30
RO
FIFO_RESET
0x000000
RX_FIFO_CTRL 31
FIFO_CTRL
4-Jul-10
MEMORY_MAP
Sub-Systems Processor(s)
Registers
IP Blocks
9
System Processors
Processor 3
MEMORY_MAP
Processor 2
MEMORY_MAP
Processor 1
MEMORY_MAP
System Instantiated Sub-Systems
00000 1C0000 4FFFF
000000 800000
Leaf IPs
8FFFFF
00000 1C0000 4FFFF
Memory Maps
4-Jul-10
10
Traditional HW/SW Interface Design Specification
IP-LEVEL Hardware D/V
SYSTEM-LEVEL Hardware D/V
SYSTEM-LEVEL Software D/V
Feedback
Feedback
HW Design
interpret
interpret SYSTEM RTL Design
Firmware Libraries
Register interpret Specify
Document interpret
Firmware testcases RTL Test
SYSTEM Test
Feedback
interpret interpret
Silicon testcases interpret
Feedback
Refinement points/Milestones
4-Jul-10
11
Compressed Design Cycle Design Specification
HW Design
IP-LEVEL Hardware D/V
interpret Feedback
RTL Test
interpret Feedback SYSTEM RTL Design
Register interpret Specify
Document
SYSTEMLEVEL Hardware D/V
SYSTEM Test interpret
Feedback Firmware Libraries interpret
interpret
SYSTEM-LEVEL Software D/V Firmware testcases
interpret Silicon testcases Feedback
4-Jul-10
12
HW/SW Interface (Verification) Specification View
SW View
HW View
Verification View
Verification Evolution New Verification thinking User Environment Applications Class Library HVL Simulation Environment
• New verification environment -
OOV Scoreboard/Checkers Constrained random Coverage driven Monitors/Drivers – TLM
• Emergence of HW verification languages -
Specman ‘e’ Vera SystemC/C++ SystemVerilog
High-level Verification Methodology
User Environment Applications Class Library HVL Simulation Environment
A high-level verification methodology consists of an HVL running in a simulation environment which can interact with the RTL. The HVL’s object-oriented infrastructure can be organized and extended to deliver high levels of productivity for specific user applications. The key mechanisms are stimulus generation, monitoring and coverage. Bailey/Martin 2007
High-level Verification Methodology
User Environment Applications Class Library HVL Simulation Environment
Evolution of the Verification methodologies (VM) • A-E-I-O-U(VM) where I = V
Verification IP Reuse Application oriented User Capability
HW/SW VM Applications
eRM VR_AD VMM RAL OVM Register Package UVM Register Package
: Methodologies improve : How to keep aligned … • To new methodologies? • Across different flows?
Standardize-Centralize-Synchronise STANDARDIZE HW Interface : interfaces & ports SW Interface : registers, memories, memory maps
IP
CENTRALIZE Correct Data Coherent specification Central repository
SYNCRONIZE Auto-generated design source HW/SW Design/Verification Specification/Implementation KEEPING TEAMS ALIGNED 4-Jul-10
18
Standardize-Centralize-Synchronise
DEMO (Using Socrates to Auto-generate any OVM/UVM Implementations
4-Jul-10
19
LCD Controller
WB_Master
WB_Slave
LCD Controller
External LCD
System
4-Jul-10
20
IP Verification Environment based on OVM OVM Environment Shadow Registers
Model Coverage
Register Map
Test Test Test Test Case Test Case Case Case Case
Generic Testcases
Scoreboard
Global Monitor
Test Test Test Test Case Test Case Case Case Case
LCD_WRAP WB Library OVC
Global Bus Monitor
Sequence Sequence r Sequencer r Class wb_slave_sequence Class r wb_slave_sequence class r wb_slave_ag class wb_slave_agent
Standard Verification Components
WB_Master OVC
Sequence Sequence r Sequencer r Class wb_slave_sequence Class r wb_slave_sequence class r wb_slave_ag class wb_slave_agent
WB Library OVC
WB_Slave OVC
Master Agent [n] Master Agent [1] Driver MasterAgent [0] Driver class Driver wb_slave_driver class wb_slave_driver
Monitor Monitor class wb_slave_monitor class Monitor wb_slave_monitor
wb_slave_driver class wb_slave_driver
Monitor Monitor class wb_slave_monitor class Monitor wb_slave_monitor
Global Bus Monitor
Sequence Sequence r Sequencer r Class wb_slave_sequence Class r wb_slave_sequence class r wb_slave_ag class wb_slave_agent
Sequence Sequence r Sequencer r Class wb_slave_sequence Class r wb_slave_sequence class r wb_slave_ag class wb_slave_agent
User Verification Component
WB_Master
Slave Agent [n] Slave Agent [1] Driver Slave Agent [0] Driver class Driver
WB_Slave
Master Agent [n] Master Agent [1] Driver MasterAgent [0] Driver class Driver wb_slave_driver class wb_slave_driver
Monitor Monitor class wb_slave_monitor class Monitor wb_slave_monitor
Slave Agent [n] Slave Agent [1] Driver Slave Agent [0] Driver class Driver
LCD Controller
External LCD
wb_slave_driver class wb_slave_driver
Monitor
LCD OVC
Monitor class wb_slave_monitor class Monitor wb_slave_monitor
System System OVC
User Verification Component Ports & Interfaces Registers
DUT
SystemVerilog Wrapper
Auto-generation of IP OVM infrastructure Bitwise
Cadence ncsim/Mentor Questasim Simulator/OVM
Duolog Socrates Package Interfaces + Verification Attributes
LCD
Package Registers + Verification Attributes
OVM Environment Shadow Registers
Import
Test Test Test Test Case Test Case Case Case Case
G
(Verilog)
Generic Testcases
Global Monitor
Test Test Test Test Case Test Case Case Case Case
LCD_WRAP WB Library OVC
Global Bus Monitor
Sequence Sequence r Sequencer r Class wb_slave_sequence Class r wb_slave_sequence class r wb_slave_ag class wb_slave_agent
WB_Master OVC
Sequence Sequence r Sequencer r Class wb_slave_sequence Class r wb_slave_sequence class wb_slave_ag class wb_slave_agent
r
WB Library OVC
WB_Slave OVC
Interface Definitions
Model Coverage
Register Map
Generate OVM
Scoreboard
Capture
Master Agent [n] Master Agent [1] Driver MasterAgent [0] Driver class Driver wb_slave_driver class wb_slave_driver
Monitor Monitor class wb_slave_monitor class Monitor wb_slave_monitor
Slave Agent [n] Slave Agent [1] Driver Slave Agent [0] Driver class Driver
WB_Master
wb_slave_driver class wb_slave_driver
Monitor Monitor class wb_slave_monitor class Monitor wb_slave_monitor
Global Bus Monitor
Sequence Sequence r Sequencer r Class wb_slave_sequence Class r wb_slave_sequence class r wb_slave_ag class wb_slave_agent
Sequence Sequence r Sequencer r Class wb_slave_sequence Class r wb_slave_sequence class r wb_slave_ag class wb_slave_agent
Master Agent [n] Master Agent [1] Driver MasterAgent [0] Driver class Driver
WB_Slave
wb_slave_driver class wb_slave_driver
Monitor Monitor class wb_slave_monitor class Monitor wb_slave_monitor
Slave Agent [n] Slave Agent [1] Driver Slave Agent [0] Driver class Driver
LCD Controller
External LCD
wb_slave_driver class wb_slave_driver
Monitor Monitor class wb_slave_monitor class Monitor wb_slave_monitor
System System OVC
WB Library OVC
Global Bus Monitor class wb_monitor
WB Library OVC
Master Agent [n]Global Bus Monitor [1] Driver MasterAgent [0] Driver
Master Agent class wb_monitor
Sequence Sequence r
class Driver Sequencer r wb_slave_driver class Agent [n] Master class wb_slave_driver Master Agent Global [1] Bus Monitor wb_master_driver Monitor wb_slave_sequence Driver Class Sequence MasterAgent [0] class Monitor wb_monitor r class wb_slave_sequence Driver Sequence r class class class wb_master_sequencer r Driver class Monitor Sequencer rwb_slave_monitor wb_slave_driver wb_slave_ag class wb_slave_monitor class class class wb_slave_driver wb_slave_agent wb_master_monitor class wb_master_agent Class Master Agent [n] wb_master_driver Monitor wb_slave_sequence Class Master Agent [1] Monitor r class wb_slave_sequence Driver Sequence Slave Agent [n] MasterAgent [0] class class wb_master_sequencer wb_slave_monitor r class Monitor Driver Sequence r Agent Slave [1] class class wb_slave_ag class wb_slave_monitor Driver Sequencer Driver Sequence r Agent wb_slave_agent Slave [0] wb_slave_driver wb_master_monitor class wb_master_agent class Driver Sequence r class wb_slave_driver class Class Driver Sequencer r wb_master_driver Monitor wb_slave_driver class Agent [n] wb_slave_sequence Class Slave class Monitor rwb_slave_driver class wb_slave_sequence Class Slave Agent [1] wb_slave_driver class Monitor class wb_master_sequencer wb_slave_monitor r class Monitor wb_slave_sequence Driver Class Sequence Slave Agent [0] class wb_slave_ag class Monitor wb_slave_monitor r class wb_slave_sequence Driver Sequence r wb_slave_agent Monitor wb_master_monitor class class Sequencer wb_master_agent class wb_slave_sequencer r class class Driver rwb_slave_monitor wb_slave_driver wb_slave_ag class wb_slave_monitor class class class wb_slave_driver wb_slave_agent wb_slave_monitor class wb_slave_agent Class Slave Agent [n] wb_slave_driver Monitor wb_slave_sequence Class Slave Agent [1] Monitor r wb_slave_sequence Driver Sequence class Slave Agent [0] class class wb_slave_sequencer wb_slave_monitor r class Monitor Driver Sequence r wb_slave_ag class wb_slave_monitor class class Driver Sequencer r wb_slave_agent wb_slave_monitor class wb_slave_agent wb_slave_driver class class wb_slave_driver Class wb_slave_driver Monitor wb_slave_sequence Class Monitor r class wb_slave_sequence class class wb_slave_sequencer wb_slave_monitor r class Monitor wb_slave_ag class wb_slave_monitor class wb_slave_agent wb_slave_monitor class wb_slave_agent
WB Library OVC Class
LCD Specification
OVC Libraries
OVM SystemVerilog code & scripts
LCD OVC
Auto-generation of IP OVM infrastructure Standard sequence
User sequence
Register Sequencer
• •
RDB updater & checker
OVC
Analysis port
Sequencer
Register Verification Environment
•
WB-S LCD Controller
100 % autogeration with the possibility of user extensions
Sending 32 bit vector sequences to the driver
Register sequencer: •
Monitor
Modular and reusable Bus protocol changes (WB -> APB) doesn’t require any changes in the register verification part
OVC Master sequencer: •
Register Map and DB Driver
Register verification is separated from the standard slave OVC:
Executing sequences from sequence library (register data) TLM connection to the OVC master sequencer using adaptor sequences
Monitor sending the read/write data to the analysis port RDB checker & updater : •
Link between bus activity and RDB
VM attributes
COMPONENT
REGISTERS
REGISTER & BITFIELDS
REGISTER ATTRIBUTES
Conclusion
HW/SW interface requires critical verification attention HW/SW interface modelling is key to synchronizing teams HW/SW interface modelling is key to allowing smoother VM transition Demoed Auto-generation of OVM/UVM from a single source Looking forward to the next transition 4-Jul-10
25
