An Apparatus for Pseudo-Detenmimistic Testing - VLSI ... - IEEE Xplore
An Apparatus for Pseudo-Deterministic Testing Shridhar K. Mukund*, Edward J. McCluskey, and T. R. N.Rao** Center for Reliable Computing Stanford University, Stanford, CA 94305
Abstract In this paper we propose a new apparatus for embedding deterministic patterns in pseudo-random sequences, with application to at-speed BIST We employ an arbitrary length Shift Register driven by a LFSR (LFSWSR)with the size of the LFSR dependant only on the number of care bits in any test vectol: We provide an efJicient method to compute positions of bit-patterns at arbitrarily chosen tap configurations in the LFSWSR sequence. Hence, one can make an optimal choice of test segments (seeds) while taking inherent advantage of don’t care bits in test vectors, say corresponding to random pattern resistantfaults. The length of the LFSWSR can be arbitrarily increased to feed several interconnected logic blocks such that all the care bits of any deterministic test vector can be predictably generated without compromising computational ej@Aency.
cuit may however have some random pattern resistant (RPR) faults. As a result, it is often required to supplement random-patterns with few deterministically generated patterns. This situation may sometimes be alleviated by using weighted random patterns [ 5 ] .Test point insertion technique [14, 15, 181 is effective, but could impact performance. Methods to synthesize LFSR for embedding deterministic patterns have been suggested in [4, 161. However, these methods do not take advantage of don’t care bits, resulting in complex LFSRs. Efficient schemes for scan based BIST have been proposed in [7,6]. Scan based BIST requires loading of a large scan chain for every applicaf.ion of test vector. As a result, it does not offer at-speed, concurrency, and test volume benefits of conventional BIST. Our intent is to address the problem of embedding deterministic patterns in at-speed BIST, where a test pattern is applied every clock cycle.
1 Introduction
1.1 On Pseudo-DeterministicTesting
With growing complexity of integrated circuits anld systems, the cost of testing has become ever more significant. BIST (Built-In Self Test) is increasingly being applied as an effective means to reduce the cost of testing. The test complexity is cut down through a systematic structured approach and the test time is reduced through concurrency. BIST also gives us the ability for testing parts at-speed, incircuit, and possibly on-line [lo].
An optimal chloice of pseudo-random subsequences can be made, if positions of deterministic test vectors, say corresponding to RPR faults, is known a priori. Through appropriate choice of seeds, the hardware apparatus for pseudorandom testing can be made to additionally cover deterministic patterns. We call this method of test pattern application, pseudo-deterministic testing. Pseudo-deterministic testing is ]particularly well suited for BIST, where the test patterns have to be generated internally.
For built-in self testing, one must be able to generate and apply test patterns internally. Due to simplicity and compactness, LFSR (Linear Feedback Shift Register) is popularly used as the apparatus for generating pseudo-random test patterns. Pseudo-random test patterns are effective when the circuit is random-pattern testable. A typical cir-
When the LFSR has fewer stages, say less than 16, one can use brute-force to determine positions of deterministic patterns. However, as the number of stages become larger, it becomes prohibitive to do so. The theory of discrete logarithms is employed to address this problem. A related problem of interest is that of identifying RPR faults. Random-pattern resistance is a function of pseudo-random test length. The exponential dependency between pseudo-random test length and fault coverage, suggests that there is a point beyond which increasing the test length does not
* This author is with R&D, Cirrus Logic Inc., pursuing graduate study in Electrical Engineering through the Honors Cooperative Program at Stanford University. **. This author is with Center of Advanced Computer Studies, University of Southwestern Louisiana, Lafayette, LA 70504. 125 0-8186-7000-2/95 $04.00 0 1995 IEEE
improve fault coverage significantly [9]. For a given pseudo-random test length, an efficient method for identifying RPR faults has been suggested in [ 171, In order to find an optimal set of seeds, one must consider a reasonable size subset, if not all, of the test vectors for every RPR fault class. We then try to maximize RPR fault coverage by making intelligent choice of seed or multiple seeds for a given test length. This method Cali also be thought of as an inexpensive first step prior to applying random pattern testability enhancement techniques such as test point insertion and logic modification.
1.2 Modular Form LFSR - GF(2n)Generator The theory of discrete logarithm has been applied to determine positions of bit patterns in the sequence generated by a modular form or internal-XOR LFSR [ 11, 81. Consider the modular realization of a n-stage LFSR in Fig. 1, with the feedback polynomial
CO
Cn-i
The problem of computing the discrete logarithm, m = l o g a p , has received wide attention in the area of Cryptography [13,2, 121. If the value of n is so chosen that 2n-1 is a large prime or at least one of its prime factors is large, then it is very hard to extract logarithms in the field GF(2"). On the other hand, it is much easier to exponentiate. It is this disparity that led Diffe and Hellman [3] to propose a cryptographic scheme based on exponentiation in finite field. However, for the pseudo-deterministic test application, the value n can be chosen such that 2n-1 is smooth (expressible as a product of relatively small primes). Fortunately, many values of n in the range of interest, say 16 < n < 100, are such that 2n-1 is smooth. A method for computing discrete logarithm, that is particularly suited for this application has been proposed in [ 111. By making careful choices of n, discrete logarithms can be computed very efficiently.
2 Motivation and the BIST Scheme
I
-...-
REG3
REG1 \
Figure I . Modular Form LFSR or SDC We call this, the Shift Division Circuit (SDC) Let p ( x ) be primitive and a be one of its roots in GF(2"). Then we can identify the state: U
P
= [bo b , ... b n - J
Figure 2. A BIST Situation pseudo-random testing, REGl,2 &3 can be configured as independent PRPGs (Pseudo-Random Pattern Generator) and REG4&5 as MISRs (Multiple Input Signature Register). The care bits for RPR faults in CLB1&2 can potentially span REG1,2&3. As a result, prior techniques for embedding deterministic patterns require REGl,2&3 to be configured into one large LFSR. The number of possible deterministic test patterns, for every RPR fault class,
of the SDC with the field element:
p
= b o + b , a + ... + b n - , a n - '
Notice that every step of work performed by the device corresponds to multiplying the field element P by the field element a. This means, starting from any non-zero state Po, the SDC generates all the other non-zero elements of
grows exponentially with the number of LFSR stages. The
GF(2n)successively as:
computation required to identify positions of deterministic patterns is soon rendered impractical. In reality, the interplay between the inputs of CLBs could be even more complex.
Po, P"a, Poa2, '..
In particular, in order to determine how many steps it will take for the SDC, starting from the state Po, to arrive at the state p, we need only compute l o g a p - log,po.
In order to satisfy the constraint due to this interplay, without compromising computational efficiency, we adopt LFSWSR, a device proposed for pseudo-exhaustive test-
126
ing [ 11. LFSWSR is composed of a standard form LFSR driving an arbitrary length shift register (scan-chain). We partition the logic into RPR Fault Partitions (RFP). A RFP is a set of RPR faults with corresponding set of primary inputs such they can be tested independently. Any primary input is associated with one and only one RFP. In a given test phase, the inputs of a RFP are configured into a LFSW SR and the outputs into MISRs, as shown in Fig. El. Note
LFSWSR. The shift register in Fig. 4 could potentially be the scan chain for the whole chip. In which case, we have an alternative method for reseeding the scan based BIST discussed in [7,6]. Needless to say, a mix of several strategies can be employed in a trade-off between test coverage and cost. In order to determine optimal test sequences or seeds, we need a computationally efficient method to determine positions of bit-patterns, at arbitrary tap configurations, in the sequence generated by the LFSWSR.
LFSR/SR
3 Standard Form LFSR - The Dual In preparation, we first develop a linear transformation that will help us identify positions of bit-patterns in a standard form LFSR sequence.
Figure 3. The BIST Scheme
We call the autonomous time-sequential circuit of Fig. 5,
that a CLB can potentially be fragmented into several RFPs. In a subsequent test phase, the LFSWSR may be configured into MISRs and vice versa. PRPGs and MISRs are optionally scan chained to move signatures1see:dsand to facilitate reconfiguration.
Figure 5. Standard Form LFSR
As in conventional BIST, it is desirable to avoid or minimize circular dependencies which result in the need for simultaneous PRPG and MISR configuration of some registers. An alternative is to configure these registers into a Shift Register (SR) as shown in Fig. 4. Any LFSR active
with the transition matrix:
1
0 0 ... 0
1 0 ... 0 T = I o 1 .. . 0
CO C1
c2
.............. 0 0 ... 1
Cn-!
RFP the standard form LFSR.
Figure 4. LFSWSWMISR
We also know that the transition matrix of an accompanying SDC with the same feedback polynomial is the transpose:
during the same test phase can be used for pattern generation and similarly a MISR for output compaction. However, for every application of test pattern the shift register needs to be shifted into. Nevertheless, prior knowledge of positions of test patterns can still be used to make optimal choice of seeds. Single seeding is desirable from a cost perspective, although multiple seeding may be performed through the scan chain. Alternatively, reseeding logic can be built around the LFSR. The cost of reseeding is justified when several RFPs are combined, resulting in a large
-
T
T =
127
0 1 0 ... 0 0 0 1 ... 0 ............... 0 0 0 ... 1
(N-n)-stage shift register
1
bk+ l I
bk+i,
~
i
n-stage standard form LFSR
bk+ it-,
Figure 6. A I tap, N-stage LFSFUSR with n-stage driving LFSR If the feedback polynomial is primitive and we start from any non-zero state, then both the circuits traverse through all the 2n - 1 distinct non-zero states. The position of a bitpattern in the standard form LFSR sequence can be determined by the following theorem.
We see from this theorem that in order to determine the distance between the test vectors Po and in the standard form LFSR, we need only compute l o g p (P) - log,o (Po)
Theorem 1: There exists a one-to-one correspondence between the state sets of a standard form LFSR and a SDC
4 LFSWSR - The Apparatus
'
with the same feedback polynomial, which is linear and respects the succession of states in both the devices.
The apparatus particularly suited for pseudo-deterministic BIST is the LFSWSR illustrated in Fig. 6. The shift register could potentially be inserted in a post-logic design step with the head of the shift register re-configured into a standard form LFSR.
Proof: Considering the invertible matrix: c1 c2 c3 ... c2 c3 c4 ... A =
cn-,
1
1
0
... ... ... ... ... ... c n - l 1 0 ... 0 0
1
0 0 ...
0
As discussed in [ 11, one can generate test patterns of the form:
(Equation 1)
r
0
7
by the help of an arbitrarily chosen tapping configuration:
it is easy to verify that:
z = [io i, i , ... i l - J , o < i j < ~ - 1
TA = AT= on a N-stage LFSWSR, where the driving n-stage standard form LFSR has a primitive feedback polynomial. A problem of interest is to make the choice of a primitive feedback polynomial such that all I-patterns can be generated at a setsf s a,rQitrarilyc,hosen tapping configura' 0 ' I S.,? * . To this end, a theorem is tions7 , T ,..., z obtained in [l].Here we give a proof in a different perspective that illustrates how the position of a test pattern ?$ at the tapping configuration z can be determined in the LFSWSR sequence.
Thus, if we define the linear mapping rs by sending the state P of the standard form LFSR to the corresponding state:
o(P) = PA
(Equation 2)
of the accompanying SDC, then it is evidently invertible and we see from: o ( ~ T =) P T A =
PAT^ = G ( P ) T ~ ,
that the transition of states in both the devices is preserved. Q. E. D.
*. For clarity only one of the s tapping configurations is illustrated in Fig. 6. 128
Theorem 2: For any integer $, we divide xl’ by p(x) to
where:
obtain the remainder T i (x) I
+ c4,1x+ ... + C i , n - l X n -
=
1
’
I
If the feedback polynomial p(x) is primitive, then the tapping configuration z generates all 1-patterns if and only if, the vectors:
Y (ij)
=
[til,
ell,
ciI,, ...
-
i], 0 I j 5 1 - 1(Equation 3)
are linearly independent.
Thus we see, if the columns of C are linearly dependent, then fixed non-trivial linear relations can be found between the components of 6k. This means not all 1-patterns can be obtained from the tap configuration z. If, on the contrary, the columns of C are linearly independent, then since p k can be any non-zero n-vector, every given 1pattern can be obtained by selecting a suitable k. Q. E. D.
In particular, if we wish the tapping configuration to generate all the 1-patterns then 1 cannot exceed n.
Proof Suppose the LFSR starts working with the nonzero state:
On the other hand, if 1 < n and the matrix C has rank I, then for any given 1-vector 6,, the linear system:
pc
= 6,
(Equation 5)
and we write: =
Pk
POr”
has Zfn solutions for p, say V (6,) . Thus, if the driving LFSR starts with an initial state Po, then for every step:
’
Then, since p(T) = 0, we see from: pk+il
=
PoT
k+i
’=
P
k
=~ P k r i l ( T )
>
that the signal 6, , being the zeroth component of the vector pk , can lie computed as:
(Equation 6)
+
+
bk+ll
=
PkYT(i,)
which means we have:
of work, the configuration z will output the pattern 6, 3
5 An Illustration 6, =
PkC3
In this section, we provide an example to illustrate the application of LFSWSR in pseudo-deterministic testing.
i 42)
1+6
1+0
1
=---a
1+7
Figure 7. An Application of the Pseudo-Deterministic Test Apparatus
129
Consider the scenario shown in Fig. 7. The design has a set of registers, some of which are connected to the inputs of CLB 1 and CLB2. The goal is to apply the deterministic pattern 62(1)= [I 1 11 to CLBl and 6, (2) = [0 1 01 to CLB2. The registers are configured into a shift register. The order in which the registers are connected is arbitrary. As a result, we have tap configurations dl)and d2)connected to CLB 1 and CLB2 respectively. We can pick a primitive feedback polynomial for the driving LFSR using the method suggested in [I], such that the columns of C matrices corresponding to dl)and d2)are linearly independent. Instead, let us arbitrarily pick a 4-stage LFSR with the 3 4 primitive feedback polynomial: 1 + x + x , and test for the linear independence of the columns of C matrices. From Eqn. 4, we have:
and B solving for ('I and p(2) in b(') C ( ' ) = ?j2(') C ( 2 ) =, 6, '),respectively. we have:
b)'
Let the LFSR start at an arbitrary state, say = [o 0 0 11 . Applying Eqn. 6, we have the positions of bit-patterns as:
so
(1)
U,
-
- 12,u2(,) = 8,
= 7 and u2(2) = 5.
(1)
The bit pattern 62 = [I 1 11 at the tapping configuration dl)is generated at the step 8 and 12. The bit pattern 0] at d2)is generated at the step 5 and 7. 6, = [0 The sequence generated by this LFSWSR is shown in Fig. 9. If we seed the driving LFSWSR with the pattern at step RO R 1
R 2 R3 R 4 R 5 R 6 R 7 (1)
TO
By inspection, the columns of C(l) and C(2)are linearly independent. We can compute discrete logarithms using the method suggested in [ l l ] . Since n is small, all the elements of GF(24)can be generated using the SDC shown in Fig. 8.
(2)
(2)
20
21
log
logCl [OOIO] = 2
a [1001]= 4 log,[llOl]=
5
0
0
1
0 0 0 0 0 1 1 1 1 1 1 1 1 0
4 5
fi
6 7
loga[lllO]= 7 loga[Ollll= 8 log
loga [OOOI J = 3 log
a [1111]= 6
l o g a [10101= 9
\
a [OlOlJ= 10 log a [ l o l l ] = 11 logCl[110O]= 12
i O E a [ a i i a ] = 13 i o 6 a [ 0 0 ~ 1 ~ = 14 io,
cl.
(2)
72
STEP
Working this SDC through all the states from the root, a = [Ol 001, we can readily obtain the discrete logarithm lookup table: l o g a [OlOO] = 1
(1)
72
=I
2 3
Figure 8. SDC with p(x) = 1 + $+
R8 R9
(1)
[1aaal= is.
0
0
101 0 101
0 0 0 1
0 0 0 1 1
0 0 0 1 1 1
0
0
1
0 1 1 1 111 0
1
1
1 1 0
111
I 1 1 101 1 101
1 0
1
8 0 1 9 1 1 1 0 1 1 1 1 1 1
11~11
111111 0
1
0
11~11
1 1 0
1 0 1
0 1 0
1 0 1
0 1 1
1 1 0
I
1 O
0 0
0 1
12 1 0 1 3 0 1 1 4 1 0 1 5 0 1
lllll
0 1 1 0
IIIII
1 0 0 1
0 0 0 1 1 0 0 0
11111 0 0 0
0 0 0 1
0 1 1
1 0 0
Figure 9. The LFSWSR Sequence From Eqn. 1, we have,
7, a sequence of length 2 covers the bit patterns of interest. If only the driving LFSR is seeded, than we need to allow sufficient number of steps to initialize the shift register.
130
6 Summary and Conclusions
References Barzilai, Z., D.Coppersmith, and A. L. Rosenberg, “Exhaustive Generation of Bit Patterns with Applications to VLSI Self-Testing,”IEEE Trans. Comput., Feb 1983.
In this paper a new apparatus for generating pseudo-deterministic patterns for at-speed BIST has been presented. By taking inherent advantage of don’t care bits, a computationally efficient method for predicting bit-patterns in the LFSWSR sequence has been proposed. A prior knowledge of the positions of test vectors, say corresponding to RPR faults, can be used to make an optimal choice of test sequences (seeds). In practical situations, there is significant interplay between the inputs of combinational logic blocks. Further, for pseudo-deterministic testing, it is, required that all the care bits of the test vector for an RPR fault be generated by the same pattern source. The LFSW SR can be extended to feed an entire span of interconnected combinational logic blocks, without compromising computational efficiency.
Coppersmith, D., “Fast Evaluation of Logarithms in Fields of Characteristic Two,” IEEE Trans. Info. Theory, July 1984. Diffe, W. and M. E. Hellman, “New Directions in Cryptography,” IEEE Trans. Info. Theory, 1976. Dufaza, C. and G. Cambon, “LFSR based Deterministic and Pseudo-Random Test Pattern Generator structures,” Proc. European Test Conference, 1991. Eichelberger, E. B., E. Lindbloom, J. A. Waicukauski and T. W. Williams, “Structured Logic Testing,” Prentice Hall, Englewood Cliffs, New Jersey 1991. Hellebrand, S., S. Tarnick and J. Rajski, “Generation of Vector Patterns Through Reseeding of Multiple-Polynomial Linear Feedback Shift Registers,” Proc. ITC, 1992.
A linear transformation [Eqn. 21 to relate the sequence generated by a standard form (external-XOR) LFSR with that of an accompanying modular form (internal-XOR) LFSR has been presented. The positions of bit-patterns are identified by computing discrete logarithms in the field generated by the accompanying modular form LFSR. A further transformation [Eqn. 51 to relate the sequence generated by a standard form LFSR with the sequence generated at arbitrarily chosen tap positions in a LFSWSR has also been presented. A formula [Eqn. 61 for identifying positions of bit-patterns in the sequence generated at these tap positions has been provided.
[7] Konemann, B., “LFSR-Coded Test Patterns for Scan Designs,” Proc. of European Test Con$, 1991. [8] Lempel, M., S . K. Gupta, and M. A. Breuer, “Test Embedding with Discrete Logarithms,” IEEE VLSI Test Symposium, 1994.
[9] McCluskey, E. J., S. Makar, S. Mourad, and K. D. Wagner, “Probability Models for Pseudorandom Test Sequences,” IEEE Trans. Computer-Aided Design, Jan. 1988. [ 101 McCluskey, E. J., “Built-In Self-Test Techniques,” IEEE Design & Test, April, 1985.
[l I] Mukund, S. K., T.R.N. Rao, and K. Zeng, “On Reducing Test Length in LFSR based Testing,” VLSI Design Symposium, Jan. 1991. [ 121 Odlyzko, A. M., “Discrete Logarithms in Finite Fields and
The proposed technique for pseudo-deterministic pattern generation can be used to enhance pseudo-random B E T by maximizing the coverage of RPR faults. The technique can be used in a variety of BIST schemes varying from concurrent at-speed BIST to simpler scan-based BIST, in order to meet a desired test coverage versus cost trade-off. It can also be used in conjunction with techniques for improving random pattern testability, such as test point insertion and logic modification.
their Cryptographic Significance,” Adv. in Cryptology (Proc. of Eurocrypt ‘84), Lecture Notes in Computer Science, Vol. 209, Springer-Verlag,New York, 1984. [13] Pohlig, S C., and M. E. Hellman, “An Improved Algorithm for Computing Logarithms over GF(p)and Its Cryptographic Significance,” IEEE Trans. Info. Theory, Jan. 1978. [14] Savaria, T., M. Youssef, B. Kamishka, and M. Koudil, “Automatic Test Point Insertion for Pseudo-Random Testing,” Proc. of Intl. Symp. on Circuits and Systems, 1991. [15] Seiss, B.H., P.M. Trouborst, and M.H. Schulz, “Test Point Insertion for Scan-Based BIST,” Proc. of European Test ConJ, 1991.
Acknowledgments
[16] Vasudevan, B., D.E. Ross, M. Gala and K.L. Watson, “LFSR Based Deterministic Hardware for At-Speed BIST,” Proc. VLSI Test Symp., 1993.
The authors gratefully acknowledge Kencheng Zeng and Pran Kurup for helpful comments and suggestions. This work was supported in part by the Innovative Science and Technology Office of the Strategic Defense Initiative Organization and administered through the Office of Naval Research under Contract No. NOOO14-92-5-1782, by the National Science Foundation under Grant No. MIP9107760, and by Cirrus Logic Inc.
[ 171 Waicukauski, J. A., E. B. Eichelberger, D. 0. Forlenza, E.
Lindbloom, and T. McCarthy, “Fault Simulation for Structured VLSI,” VLSISystems Design, Dec. 1985. [18] Youssef, M., Y.Savaria, and B. Kaminska, “Methodology for Efficiently Inserting and Condensing Test Points,” IEE Proceedings-E, Vol. 140, No. 3., May 1993.
131
Abstract In this paper we propose a new apparatus for embedding deterministic patterns in pseudo-random sequences, with application to at-speed BIST We employ an arbitrary length Shift Register driven by a LFSR (LFSWSR)with the size of the LFSR dependant only on the number of care bits in any test vectol: We provide an efJicient method to compute positions of bit-patterns at arbitrarily chosen tap configurations in the LFSWSR sequence. Hence, one can make an optimal choice of test segments (seeds) while taking inherent advantage of don’t care bits in test vectors, say corresponding to random pattern resistantfaults. The length of the LFSWSR can be arbitrarily increased to feed several interconnected logic blocks such that all the care bits of any deterministic test vector can be predictably generated without compromising computational ej@Aency.
cuit may however have some random pattern resistant (RPR) faults. As a result, it is often required to supplement random-patterns with few deterministically generated patterns. This situation may sometimes be alleviated by using weighted random patterns [ 5 ] .Test point insertion technique [14, 15, 181 is effective, but could impact performance. Methods to synthesize LFSR for embedding deterministic patterns have been suggested in [4, 161. However, these methods do not take advantage of don’t care bits, resulting in complex LFSRs. Efficient schemes for scan based BIST have been proposed in [7,6]. Scan based BIST requires loading of a large scan chain for every applicaf.ion of test vector. As a result, it does not offer at-speed, concurrency, and test volume benefits of conventional BIST. Our intent is to address the problem of embedding deterministic patterns in at-speed BIST, where a test pattern is applied every clock cycle.
1 Introduction
1.1 On Pseudo-DeterministicTesting
With growing complexity of integrated circuits anld systems, the cost of testing has become ever more significant. BIST (Built-In Self Test) is increasingly being applied as an effective means to reduce the cost of testing. The test complexity is cut down through a systematic structured approach and the test time is reduced through concurrency. BIST also gives us the ability for testing parts at-speed, incircuit, and possibly on-line [lo].
An optimal chloice of pseudo-random subsequences can be made, if positions of deterministic test vectors, say corresponding to RPR faults, is known a priori. Through appropriate choice of seeds, the hardware apparatus for pseudorandom testing can be made to additionally cover deterministic patterns. We call this method of test pattern application, pseudo-deterministic testing. Pseudo-deterministic testing is ]particularly well suited for BIST, where the test patterns have to be generated internally.
For built-in self testing, one must be able to generate and apply test patterns internally. Due to simplicity and compactness, LFSR (Linear Feedback Shift Register) is popularly used as the apparatus for generating pseudo-random test patterns. Pseudo-random test patterns are effective when the circuit is random-pattern testable. A typical cir-
When the LFSR has fewer stages, say less than 16, one can use brute-force to determine positions of deterministic patterns. However, as the number of stages become larger, it becomes prohibitive to do so. The theory of discrete logarithms is employed to address this problem. A related problem of interest is that of identifying RPR faults. Random-pattern resistance is a function of pseudo-random test length. The exponential dependency between pseudo-random test length and fault coverage, suggests that there is a point beyond which increasing the test length does not
* This author is with R&D, Cirrus Logic Inc., pursuing graduate study in Electrical Engineering through the Honors Cooperative Program at Stanford University. **. This author is with Center of Advanced Computer Studies, University of Southwestern Louisiana, Lafayette, LA 70504. 125 0-8186-7000-2/95 $04.00 0 1995 IEEE
improve fault coverage significantly [9]. For a given pseudo-random test length, an efficient method for identifying RPR faults has been suggested in [ 171, In order to find an optimal set of seeds, one must consider a reasonable size subset, if not all, of the test vectors for every RPR fault class. We then try to maximize RPR fault coverage by making intelligent choice of seed or multiple seeds for a given test length. This method Cali also be thought of as an inexpensive first step prior to applying random pattern testability enhancement techniques such as test point insertion and logic modification.
1.2 Modular Form LFSR - GF(2n)Generator The theory of discrete logarithm has been applied to determine positions of bit patterns in the sequence generated by a modular form or internal-XOR LFSR [ 11, 81. Consider the modular realization of a n-stage LFSR in Fig. 1, with the feedback polynomial
CO
Cn-i
The problem of computing the discrete logarithm, m = l o g a p , has received wide attention in the area of Cryptography [13,2, 121. If the value of n is so chosen that 2n-1 is a large prime or at least one of its prime factors is large, then it is very hard to extract logarithms in the field GF(2"). On the other hand, it is much easier to exponentiate. It is this disparity that led Diffe and Hellman [3] to propose a cryptographic scheme based on exponentiation in finite field. However, for the pseudo-deterministic test application, the value n can be chosen such that 2n-1 is smooth (expressible as a product of relatively small primes). Fortunately, many values of n in the range of interest, say 16 < n < 100, are such that 2n-1 is smooth. A method for computing discrete logarithm, that is particularly suited for this application has been proposed in [ 111. By making careful choices of n, discrete logarithms can be computed very efficiently.
2 Motivation and the BIST Scheme
I
-...-
REG3
REG1 \
Figure I . Modular Form LFSR or SDC We call this, the Shift Division Circuit (SDC) Let p ( x ) be primitive and a be one of its roots in GF(2"). Then we can identify the state: U
P
= [bo b , ... b n - J
Figure 2. A BIST Situation pseudo-random testing, REGl,2 &3 can be configured as independent PRPGs (Pseudo-Random Pattern Generator) and REG4&5 as MISRs (Multiple Input Signature Register). The care bits for RPR faults in CLB1&2 can potentially span REG1,2&3. As a result, prior techniques for embedding deterministic patterns require REGl,2&3 to be configured into one large LFSR. The number of possible deterministic test patterns, for every RPR fault class,
of the SDC with the field element:
p
= b o + b , a + ... + b n - , a n - '
Notice that every step of work performed by the device corresponds to multiplying the field element P by the field element a. This means, starting from any non-zero state Po, the SDC generates all the other non-zero elements of
grows exponentially with the number of LFSR stages. The
GF(2n)successively as:
computation required to identify positions of deterministic patterns is soon rendered impractical. In reality, the interplay between the inputs of CLBs could be even more complex.
Po, P"a, Poa2, '..
In particular, in order to determine how many steps it will take for the SDC, starting from the state Po, to arrive at the state p, we need only compute l o g a p - log,po.
In order to satisfy the constraint due to this interplay, without compromising computational efficiency, we adopt LFSWSR, a device proposed for pseudo-exhaustive test-
126
ing [ 11. LFSWSR is composed of a standard form LFSR driving an arbitrary length shift register (scan-chain). We partition the logic into RPR Fault Partitions (RFP). A RFP is a set of RPR faults with corresponding set of primary inputs such they can be tested independently. Any primary input is associated with one and only one RFP. In a given test phase, the inputs of a RFP are configured into a LFSW SR and the outputs into MISRs, as shown in Fig. El. Note
LFSWSR. The shift register in Fig. 4 could potentially be the scan chain for the whole chip. In which case, we have an alternative method for reseeding the scan based BIST discussed in [7,6]. Needless to say, a mix of several strategies can be employed in a trade-off between test coverage and cost. In order to determine optimal test sequences or seeds, we need a computationally efficient method to determine positions of bit-patterns, at arbitrary tap configurations, in the sequence generated by the LFSWSR.
LFSR/SR
3 Standard Form LFSR - The Dual In preparation, we first develop a linear transformation that will help us identify positions of bit-patterns in a standard form LFSR sequence.
Figure 3. The BIST Scheme
We call the autonomous time-sequential circuit of Fig. 5,
that a CLB can potentially be fragmented into several RFPs. In a subsequent test phase, the LFSWSR may be configured into MISRs and vice versa. PRPGs and MISRs are optionally scan chained to move signatures1see:dsand to facilitate reconfiguration.
Figure 5. Standard Form LFSR
As in conventional BIST, it is desirable to avoid or minimize circular dependencies which result in the need for simultaneous PRPG and MISR configuration of some registers. An alternative is to configure these registers into a Shift Register (SR) as shown in Fig. 4. Any LFSR active
with the transition matrix:
1
0 0 ... 0
1 0 ... 0 T = I o 1 .. . 0
CO C1
c2
.............. 0 0 ... 1
Cn-!
RFP the standard form LFSR.
Figure 4. LFSWSWMISR
We also know that the transition matrix of an accompanying SDC with the same feedback polynomial is the transpose:
during the same test phase can be used for pattern generation and similarly a MISR for output compaction. However, for every application of test pattern the shift register needs to be shifted into. Nevertheless, prior knowledge of positions of test patterns can still be used to make optimal choice of seeds. Single seeding is desirable from a cost perspective, although multiple seeding may be performed through the scan chain. Alternatively, reseeding logic can be built around the LFSR. The cost of reseeding is justified when several RFPs are combined, resulting in a large
-
T
T =
127
0 1 0 ... 0 0 0 1 ... 0 ............... 0 0 0 ... 1
(N-n)-stage shift register
1
bk+ l I
bk+i,
~
i
n-stage standard form LFSR
bk+ it-,
Figure 6. A I tap, N-stage LFSFUSR with n-stage driving LFSR If the feedback polynomial is primitive and we start from any non-zero state, then both the circuits traverse through all the 2n - 1 distinct non-zero states. The position of a bitpattern in the standard form LFSR sequence can be determined by the following theorem.
We see from this theorem that in order to determine the distance between the test vectors Po and in the standard form LFSR, we need only compute l o g p (P) - log,o (Po)
Theorem 1: There exists a one-to-one correspondence between the state sets of a standard form LFSR and a SDC
4 LFSWSR - The Apparatus
'
with the same feedback polynomial, which is linear and respects the succession of states in both the devices.
The apparatus particularly suited for pseudo-deterministic BIST is the LFSWSR illustrated in Fig. 6. The shift register could potentially be inserted in a post-logic design step with the head of the shift register re-configured into a standard form LFSR.
Proof: Considering the invertible matrix: c1 c2 c3 ... c2 c3 c4 ... A =
cn-,
1
1
0
... ... ... ... ... ... c n - l 1 0 ... 0 0
1
0 0 ...
0
As discussed in [ 11, one can generate test patterns of the form:
(Equation 1)
r
0
7
by the help of an arbitrarily chosen tapping configuration:
it is easy to verify that:
z = [io i, i , ... i l - J , o < i j < ~ - 1
TA = AT= on a N-stage LFSWSR, where the driving n-stage standard form LFSR has a primitive feedback polynomial. A problem of interest is to make the choice of a primitive feedback polynomial such that all I-patterns can be generated at a setsf s a,rQitrarilyc,hosen tapping configura' 0 ' I S.,? * . To this end, a theorem is tions7 , T ,..., z obtained in [l].Here we give a proof in a different perspective that illustrates how the position of a test pattern ?$ at the tapping configuration z can be determined in the LFSWSR sequence.
Thus, if we define the linear mapping rs by sending the state P of the standard form LFSR to the corresponding state:
o(P) = PA
(Equation 2)
of the accompanying SDC, then it is evidently invertible and we see from: o ( ~ T =) P T A =
PAT^ = G ( P ) T ~ ,
that the transition of states in both the devices is preserved. Q. E. D.
*. For clarity only one of the s tapping configurations is illustrated in Fig. 6. 128
Theorem 2: For any integer $, we divide xl’ by p(x) to
where:
obtain the remainder T i (x) I
+ c4,1x+ ... + C i , n - l X n -
=
1
’
I
If the feedback polynomial p(x) is primitive, then the tapping configuration z generates all 1-patterns if and only if, the vectors:
Y (ij)
=
[til,
ell,
ciI,, ...
-
i], 0 I j 5 1 - 1(Equation 3)
are linearly independent.
Thus we see, if the columns of C are linearly dependent, then fixed non-trivial linear relations can be found between the components of 6k. This means not all 1-patterns can be obtained from the tap configuration z. If, on the contrary, the columns of C are linearly independent, then since p k can be any non-zero n-vector, every given 1pattern can be obtained by selecting a suitable k. Q. E. D.
In particular, if we wish the tapping configuration to generate all the 1-patterns then 1 cannot exceed n.
Proof Suppose the LFSR starts working with the nonzero state:
On the other hand, if 1 < n and the matrix C has rank I, then for any given 1-vector 6,, the linear system:
pc
= 6,
(Equation 5)
and we write: =
Pk
POr”
has Zfn solutions for p, say V (6,) . Thus, if the driving LFSR starts with an initial state Po, then for every step:
’
Then, since p(T) = 0, we see from: pk+il
=
PoT
k+i
’=
P
k
=~ P k r i l ( T )
>
that the signal 6, , being the zeroth component of the vector pk , can lie computed as:
(Equation 6)
+
+
bk+ll
=
PkYT(i,)
which means we have:
of work, the configuration z will output the pattern 6, 3
5 An Illustration 6, =
PkC3
In this section, we provide an example to illustrate the application of LFSWSR in pseudo-deterministic testing.
i 42)
1+6
1+0
1
=---a
1+7
Figure 7. An Application of the Pseudo-Deterministic Test Apparatus
129
Consider the scenario shown in Fig. 7. The design has a set of registers, some of which are connected to the inputs of CLB 1 and CLB2. The goal is to apply the deterministic pattern 62(1)= [I 1 11 to CLBl and 6, (2) = [0 1 01 to CLB2. The registers are configured into a shift register. The order in which the registers are connected is arbitrary. As a result, we have tap configurations dl)and d2)connected to CLB 1 and CLB2 respectively. We can pick a primitive feedback polynomial for the driving LFSR using the method suggested in [I], such that the columns of C matrices corresponding to dl)and d2)are linearly independent. Instead, let us arbitrarily pick a 4-stage LFSR with the 3 4 primitive feedback polynomial: 1 + x + x , and test for the linear independence of the columns of C matrices. From Eqn. 4, we have:
and B solving for ('I and p(2) in b(') C ( ' ) = ?j2(') C ( 2 ) =, 6, '),respectively. we have:
b)'
Let the LFSR start at an arbitrary state, say = [o 0 0 11 . Applying Eqn. 6, we have the positions of bit-patterns as:
so
(1)
U,
-
- 12,u2(,) = 8,
= 7 and u2(2) = 5.
(1)
The bit pattern 62 = [I 1 11 at the tapping configuration dl)is generated at the step 8 and 12. The bit pattern 0] at d2)is generated at the step 5 and 7. 6, = [0 The sequence generated by this LFSWSR is shown in Fig. 9. If we seed the driving LFSWSR with the pattern at step RO R 1
R 2 R3 R 4 R 5 R 6 R 7 (1)
TO
By inspection, the columns of C(l) and C(2)are linearly independent. We can compute discrete logarithms using the method suggested in [ l l ] . Since n is small, all the elements of GF(24)can be generated using the SDC shown in Fig. 8.
(2)
(2)
20
21
log
logCl [OOIO] = 2
a [1001]= 4 log,[llOl]=
5
0
0
1
0 0 0 0 0 1 1 1 1 1 1 1 1 0
4 5
fi
6 7
loga[lllO]= 7 loga[Ollll= 8 log
loga [OOOI J = 3 log
a [1111]= 6
l o g a [10101= 9
\
a [OlOlJ= 10 log a [ l o l l ] = 11 logCl[110O]= 12
i O E a [ a i i a ] = 13 i o 6 a [ 0 0 ~ 1 ~ = 14 io,
cl.
(2)
72
STEP
Working this SDC through all the states from the root, a = [Ol 001, we can readily obtain the discrete logarithm lookup table: l o g a [OlOO] = 1
(1)
72
=I
2 3
Figure 8. SDC with p(x) = 1 + $+
R8 R9
(1)
[1aaal= is.
0
0
101 0 101
0 0 0 1
0 0 0 1 1
0 0 0 1 1 1
0
0
1
0 1 1 1 111 0
1
1
1 1 0
111
I 1 1 101 1 101
1 0
1
8 0 1 9 1 1 1 0 1 1 1 1 1 1
11~11
111111 0
1
0
11~11
1 1 0
1 0 1
0 1 0
1 0 1
0 1 1
1 1 0
I
1 O
0 0
0 1
12 1 0 1 3 0 1 1 4 1 0 1 5 0 1
lllll
0 1 1 0
IIIII
1 0 0 1
0 0 0 1 1 0 0 0
11111 0 0 0
0 0 0 1
0 1 1
1 0 0
Figure 9. The LFSWSR Sequence From Eqn. 1, we have,
7, a sequence of length 2 covers the bit patterns of interest. If only the driving LFSR is seeded, than we need to allow sufficient number of steps to initialize the shift register.
130
6 Summary and Conclusions
References Barzilai, Z., D.Coppersmith, and A. L. Rosenberg, “Exhaustive Generation of Bit Patterns with Applications to VLSI Self-Testing,”IEEE Trans. Comput., Feb 1983.
In this paper a new apparatus for generating pseudo-deterministic patterns for at-speed BIST has been presented. By taking inherent advantage of don’t care bits, a computationally efficient method for predicting bit-patterns in the LFSWSR sequence has been proposed. A prior knowledge of the positions of test vectors, say corresponding to RPR faults, can be used to make an optimal choice of test sequences (seeds). In practical situations, there is significant interplay between the inputs of combinational logic blocks. Further, for pseudo-deterministic testing, it is, required that all the care bits of the test vector for an RPR fault be generated by the same pattern source. The LFSW SR can be extended to feed an entire span of interconnected combinational logic blocks, without compromising computational efficiency.
Coppersmith, D., “Fast Evaluation of Logarithms in Fields of Characteristic Two,” IEEE Trans. Info. Theory, July 1984. Diffe, W. and M. E. Hellman, “New Directions in Cryptography,” IEEE Trans. Info. Theory, 1976. Dufaza, C. and G. Cambon, “LFSR based Deterministic and Pseudo-Random Test Pattern Generator structures,” Proc. European Test Conference, 1991. Eichelberger, E. B., E. Lindbloom, J. A. Waicukauski and T. W. Williams, “Structured Logic Testing,” Prentice Hall, Englewood Cliffs, New Jersey 1991. Hellebrand, S., S. Tarnick and J. Rajski, “Generation of Vector Patterns Through Reseeding of Multiple-Polynomial Linear Feedback Shift Registers,” Proc. ITC, 1992.
A linear transformation [Eqn. 21 to relate the sequence generated by a standard form (external-XOR) LFSR with that of an accompanying modular form (internal-XOR) LFSR has been presented. The positions of bit-patterns are identified by computing discrete logarithms in the field generated by the accompanying modular form LFSR. A further transformation [Eqn. 51 to relate the sequence generated by a standard form LFSR with the sequence generated at arbitrarily chosen tap positions in a LFSWSR has also been presented. A formula [Eqn. 61 for identifying positions of bit-patterns in the sequence generated at these tap positions has been provided.
[7] Konemann, B., “LFSR-Coded Test Patterns for Scan Designs,” Proc. of European Test Con$, 1991. [8] Lempel, M., S . K. Gupta, and M. A. Breuer, “Test Embedding with Discrete Logarithms,” IEEE VLSI Test Symposium, 1994.
[9] McCluskey, E. J., S. Makar, S. Mourad, and K. D. Wagner, “Probability Models for Pseudorandom Test Sequences,” IEEE Trans. Computer-Aided Design, Jan. 1988. [ 101 McCluskey, E. J., “Built-In Self-Test Techniques,” IEEE Design & Test, April, 1985.
[l I] Mukund, S. K., T.R.N. Rao, and K. Zeng, “On Reducing Test Length in LFSR based Testing,” VLSI Design Symposium, Jan. 1991. [ 121 Odlyzko, A. M., “Discrete Logarithms in Finite Fields and
The proposed technique for pseudo-deterministic pattern generation can be used to enhance pseudo-random B E T by maximizing the coverage of RPR faults. The technique can be used in a variety of BIST schemes varying from concurrent at-speed BIST to simpler scan-based BIST, in order to meet a desired test coverage versus cost trade-off. It can also be used in conjunction with techniques for improving random pattern testability, such as test point insertion and logic modification.
their Cryptographic Significance,” Adv. in Cryptology (Proc. of Eurocrypt ‘84), Lecture Notes in Computer Science, Vol. 209, Springer-Verlag,New York, 1984. [13] Pohlig, S C., and M. E. Hellman, “An Improved Algorithm for Computing Logarithms over GF(p)and Its Cryptographic Significance,” IEEE Trans. Info. Theory, Jan. 1978. [14] Savaria, T., M. Youssef, B. Kamishka, and M. Koudil, “Automatic Test Point Insertion for Pseudo-Random Testing,” Proc. of Intl. Symp. on Circuits and Systems, 1991. [15] Seiss, B.H., P.M. Trouborst, and M.H. Schulz, “Test Point Insertion for Scan-Based BIST,” Proc. of European Test ConJ, 1991.
Acknowledgments
[16] Vasudevan, B., D.E. Ross, M. Gala and K.L. Watson, “LFSR Based Deterministic Hardware for At-Speed BIST,” Proc. VLSI Test Symp., 1993.
The authors gratefully acknowledge Kencheng Zeng and Pran Kurup for helpful comments and suggestions. This work was supported in part by the Innovative Science and Technology Office of the Strategic Defense Initiative Organization and administered through the Office of Naval Research under Contract No. NOOO14-92-5-1782, by the National Science Foundation under Grant No. MIP9107760, and by Cirrus Logic Inc.
[ 171 Waicukauski, J. A., E. B. Eichelberger, D. 0. Forlenza, E.
Lindbloom, and T. McCarthy, “Fault Simulation for Structured VLSI,” VLSISystems Design, Dec. 1985. [18] Youssef, M., Y.Savaria, and B. Kaminska, “Methodology for Efficiently Inserting and Condensing Test Points,” IEE Proceedings-E, Vol. 140, No. 3., May 1993.
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