An Asynchronous Finite State Machine Controller ... - Semantic Scholar
An Asynchronous Finite State Machine Controller for Integrated Buck-Boost Power Converters in Wideband Signal-Tracking Applications Daniel Fernández, Jordi Madrenas and Eduard Alarcón Electronic Engineering Department Universitat Politècnica de Catalunya Jordi Girona 1-3, 08034 Barcelona, Spain Email: [email protected]
Abstract—In this paper, a simple, fully digital, asynchronous finite state machine controller for buck-boost power converters is introduced and simulated. With the addition of only two analog voltage comparators and six power MOS switches, the circuit can generate an output voltage that is able to track a dynamic reference with a 1 MHz bandwidth with good efficiency using a 0.35 μ m CMOS process. The controller also provides adiabatic charging and discharging of capacitive loads.
I. I NTRODUCTION In telecommunications and computing systems, the continuous trend in miniaturizing power processing subsystems, which are in charge of guaranteeing high efficiency in the use of supply energy, stands from the global system-level impact of those subsystems in terms of volume and weight, and thus on portability. This statement is particularly true for current and future generation systems-onchip (SOC), a trend which provides a line of convergence for the implementation of systems for portable, mobile and autonomous applications, in which power management is one of the key performance limiting factors as regards to ergonomics and operability time. The ultimate step consequently consists in the fully monolithic integration of the power converter together with the same circuits which constitute its load [1–4]. On-chip efficient power management circuits usually focus on integrating a regulator, a circuit which pursues a stable output regardless of perturbations in both the output load and input power source. There are indeed a few challenging applications in which the output of the converter is forced to track a wideband time-varying signal. Among the different applications for such wideband amplifiers, we could point out three cases with stringent specifications, namely A) MEMS-based capacitive actuators, where the positive-feedback pull-in effect can be overcome applying time-variable supply, B) System-level optimization of power consumption in digital circuits, via Adaptive Voltage Scaling scheme (AVS) [5, 6], C) Envelope Elimination and Restoration (EER) or Kahn technique [7, 8], which theoretically allows implementation of linear highly efficient RF Power Amplifiers (as required by RF power amplification in modern digital modulations such as in EDGE and UMTS as well as in WiLAN and 4G applications that exhibit significant envelope modulation by adaptively supplying the RF PA with the wideband baseband envelope signal via a switching power converter, of the type usually applied to efficient DC-DC conversion. One of the key remaining challenges for a successful realization of such systems is the practical implementation of the efficient, wide-bandwidth tracking power converter. Independently of whether the power converter operates in a regulator or amplifier application, one additional challenge is that of designing the control scheme and modulation law to drive the converter [9]. Recently, feasibility of practical high-frequency,
978-1-4244-1684-4/08/$25.00 ©2008 IEEE
high-performance digital controllers for DC-DC applications has been demonstrated [10]. Based on custom VLSI realizations of the key building blocks, including high-resolution high-frequency digital pulse-width modulators (DPWM), simplified discrete-time compensator schemes, and A/D converters, such controllers can offer the advantages of lower sensitivity to parameter variations, programmability, and reduction or elimination of external passive components, without compromising dynamic performance, simplicity or cost [11–13]. Application of digital controllers in the field of power converters frequently rise problems regarding efficiency due to their power consumption. One of the causes is the requirement of a very low latency synchronous digital circuit, which implies high-frequency clock signals routed system-wide (thus highly capacitively loaded) that are continuosly dissipating power. On the contrary, since asynchronous digital controllers are clockless, they have a very low power consumption as opposed to synchronous controllers [14] and an extremely low latency (they don’t need to wait one clock period to change their internal state). Clock elimination avoids the need of buffers to reduce clock skew as well as electromagnetic interference [15]. Despite all those advantages, asynchronous design is more complex and there are still few design tools to ease the task. Asynchronous digital circuits are usually described with a Finite State Machine model or FSM [16]. Asynchronous finite state machines are referred as AFSM. This description provides a graphical and simple representation of the behavior of small and medium size digital sequential systems. This paper focuses on the on-chip integration of a switching power converter targeting wideband tracking application using asynchronous digital control. In Section II the power converter architecture is presented. In Section III the AFSM controller architecture and implementation is explained in detail and in Section IV the simulation results are shown. II. S YSTEM ARCHITECTURE The the non-inverting buck-boost power converter schematic is shown in figure 1 [17–20]. The input voltage is connected to VIN and the output voltage is available in VOU T . CL and RL model the load and the inductor acts as an energy transfer element. M1 , M2 , M3 , M4N , M4P and M5 are power MOS transistors and all the others are small MOS switches. The gate voltage VGx of the MOS transistors are logically driven directly by the AFSM controller. The switch M4 was implemented as a pass gate instead of a single PMOS transistor in case of VOU T is required to go below the PMOS threshold voltage.
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VG5
VG4N M5
VIN
M4N
L
M1
VOU T M4P
VG1
M2
M3
VG2
VG4P
CL
RL
VG3
VLIM M2b
M3b
M6
M7
VG6
+
VG7
− U1
VG1
AFSM VREF
+
VOU T
−
VG2 VG3 VG4P
Figure 2. Finite state machine controller diagram. The conditions are represented as physical variables instead of the comparator outputs for clarity purposes.
VG4N U2
VG5 VG6 VG7
Figure 1. Power converter circuit schematic. M1 , M2 , M3 , M4N , M4P and M5 are power MOS switches and M2b , M3b , M5 and M6 are small MOS switches, all driven by the AFSM controller. U1 and U2 are voltage comparators.
•
The running sequence generated by the AFSM controller depends on a comparator that detects whether VOU T is below or above a reference or desired voltage VREF . The AFSM controller also requires to know the inductor current sign and if the inductor current reaches a certain limit ILIM . This current can be measured indirectly by monitoring the voltage drop of either VDS2 if M2 is on or VDS3 if M3 is on. The voltage is compared either with zero if the sequence requires to detect when the inductor is discharged or with a constant positive voltage VLIM if the sequence requires to detect when its current reaches a certain limit. VLIM is related to the inductor current limit ILIM by means of VLIM = ILIM RON
•
•
•
(1)
where RON is the on resistance of M2 or M3 switches. Since the controller only requires to know either the current sign or current limit at each state, a simple multiplexing circuit is used, implemented by M2b , M3b , M5 and M6 . This way, allowing a single comparator to perform all current detection of the inductor reduces the power consumption and thereby increases efficiency. Despite two additional control signals are needed, namely VG6 and VG7 , they can be easily generated by the AFSM controller. III. T HE FINITE STATE MACHINE CONTROLLER
transistors are M1 , M3 , M3b and M6 . LtoC transfers energy from the charged inductor to the output load. If the output voltage reaches the reference, it jumps to LtoV to return the remaining energy of the inductor to the source. If the inductor discharges completely without the output voltage reaching the reference, the state jumps to ChgL to begin another charging cycle. Active transistors are M2 , M2b , M4x and M7 . LtoV returns the remaining inductor energy (if any) to the source. When it is done, it jumps back to ChgL if the output voltage is below the refence of to CtoL if is above. Active transistors are M2 , M2b , M5 and M7 . CtoL transfers energy from the capacitor to the inductor, thus decreasing the output voltage, until it reaches the reference or the inductor current reaches a limit. Then it jumps to DisL. Active transistors are M2 , M2b , M4 and M6 . DisL returns energy to the source. When it is done it jumps to CtoL if the output voltage is still above the reference or to ChgL if not. Active transistors are M1 , M3 , M3b and M7 .
Each state is divided in two or three substates to implement a deadtime in the outputs to avoid current shoot across the MOS switches. The duration of the deadtime is taken from the constant time response of a chain of starving inverters. This solution provides a wide tuning range while keeping a very low power consumption. Another chain of starving inverters implement a stabilization time delay that the AFSM must wait just after entering in a new state before it can change of state again. This is necessary to avoid anomalous behaviors due to the nonzero response time of the comparators.
A. Architecture
B. Implementation
The AFSM controller diagram is shown in figure 2, where the circles represent major states. The state names and their function are summarized in the following list: • ChgL charges the inductor until its current reaches the specified limit ILIM . When this happens, the state jumps to LtoC. Active
The AFSM was coded in Verilog directly at gate level to avoid hazards or glitches caused by the logical simplifications done by the commercial available synthesizers, while allowing the possibility of automatic layout drawing. Glitches or hazards are acceptable on synchronous design as long as they disappear before the next clock
2211
TABLE I G ENERALIZED C- ELEMENT S TATE T RANSITION TABLE S
R
Q+
0
0
Q
0
1
0
1
0
1
1
1
Q
S R
Q
Figure 4. Transient response of the power converter. The plots show the output voltage VOU T for various constant values of reference voltage VREF . VIN was set to 3.3 V , L = 1 μH, CL = 10 nF and RL = 133 Ω.
event, however, they increase the power consumption and can cause unwanted switching of the output transistors of the power converter, thereby decreasing efficiency. Also, they are a major cause of errors in asynchronous design, as glitches cannot be easily distinguished from real transitions in most of the asynchronous implementations. In order to ease the design task and reduce the risk of glitches in the outputs, each state is implemented by using gate-level descriptions of generalized C-elements (gC) [21] and some simple additional logic. gC-elements are a type of latch with decoupled set and reset inputs. The state transition table of the gC-element is shown in table I and a gate level implementation, similar to those published in [22], in figure 3. Each of the five states has, at least, a set and a reset signal. Their set signal is generated by performing a logical AN D operation between the output of the substate from the controller can jump from and the jump condition itself, while their reset signal is generated by performing a logical OR operation of the outputs of the substates to the controller can jump to. The circuit has also an external global reset signal.
however, due to the nonzero time response of the comparators and the controller, which cause a delayed controller state change. Figure 5 shows the behavior of the power converter for a dynamic input reference, consisting in a 1 M Hz triangular wave. The value of the gate voltages of the power transistors and current drained from the input VIN are also shown in order to assess the behavior of the controller. Although it might seem that the tracking error is high, an improved topology based on the linear-assisted scheme can be applied in this case, thus increasing the overall efficiency of the system. The effect of the delay of the comparators and the controller is an output voltage going slightly above the reference at the end of the LtoC state during the rising edge of the triangle input waveform and going slightly below the reference at the end of the CtoL state during the falling edge. Those effects are expected to be much smaller with faster deep submicron technologies. Also, if at least one more bit of information about the difference between output voltage VOU T and the reference VREF is made available to the controller, the inductor could be charged with less energy during the ChgL state if this difference is small, making the charging of the output capacitor during LtoC state much slower and reducing the effect of a slow circuitry at the output voltage. This will also increase efficiency since it will reduce the amount of remaining energy that has to so be returned to the source during the LtoV state. Moreover, if the load is mainly capacitive, the controller could be stopped if the difference is small enough.
IV. R ESULTS
V. C ONCLUSION
The circuit was simulated at transistor-level with Spectre in the AMIS C035U 0.35 μm CMOS process and it will be manufactured in the near future. The width of the power MOS transistors has been set in order to have a RON resistance of 0.5 Ω. The inductor parasitic resistance was set to 0.2 Ω based on a commerciallyavailable inductor datasheet. The AFSM controller netlist has been implemented using standard cells of the digital library provided with the design kit to allow automatic layout routing. In figure 4 the output voltage for some values of the reference voltage is shown. The efficiency reaches 75% for VREF = 3.3 V and the circuit parameters of the figure. Peak efficiency was found to be beyond 80%. The ripple that can be observed for high output voltages is due to the discharge of the output capacitor by the resistive load, and can be easily reduced increasing the size of the output capacitor. The output ripple that can be observed for low output voltages is,
In this paper we have shown the suitability of asynchronous digital controllers for power converters. We also have presented a simple AFSM controller for buck-boost power converters with the capability of adiabatic charging and discharging of capacitive loads and found its main limitations, which are related to the circuit latency. Simulated response indicates 75% efficiency with a 8.5 M Hz switching frequency in a 0.35 μm CMOS process technology. Both bandwidth and efficiency is expected to increase with advanced submicron technologies, while output ripple is expected to decrease. The AFSM netlist description in Verilog and a minimal analog circuitry allows for easy portability of the design amongst different manufacturing processes, for automatic layout generation and routing of the controller from a library of standard digital cells and also for reducing the design cycle or time to market of products which require power converters.
Figure 3. Generalized C-element gate-level implementation. S is the set signal, R is the reset signal and Q is the output.
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[5]
[6]
[7] [8]
[9] [10]
[11] [12]
[13] Figure 5. Behavior of the power converter for a dynamic input reference. The plots show the output voltage VOU T , the current drained by the converter IIN and the gate voltages of the power transistors for a positive triangle waveform of 1 μs period, also shown. VIN was set to 3.3 V , L = 1 μH, CL = 5 nF and RL = 220 Ω.
The presented circuit can be used in environments where a high frequency output is required, such as Adaptive Voltage Scaling (AVS) and Envelope Elimination and Restoration (EER) or in applications where the load has a significant capacitive component, such as in MEMS capacitive actuator driving or also as a simple and fast replacement of classic inductor-based power converters.
[14]
[15] [16] [17] [18] [19]
ACKNOWLEDGMENT This work was supported in part by the Spanish Ministry of Education and Science under Projects TEC2004-03940, TEC200767144/MIC and TEC2004-05608-C02-01 from the Spanish MCYT and EU FEDER. Daniel Fernández holds a research fellowship supported by the Catalan Department of Universities, Research and Information Society (DURSI) and the European Social Fund (ESF).
[20] [21] [22]
R EFERENCES [1] E. Alarcón and D. Maksimovic, “Powering ICs: trends in on-chip power regulators,” in Indian Institute of Technology, Kharagpur, India, December, 23 2005, invited Paper. [2] Y.-H. Lam, W.-H. Ki, C.-F. Tsui, and P. Mok, “Single-inductor dualinput dual-output switching converter for integrated battery charging and power regulation,” in Circuits and Systems, 2003. ISCAS ’03. Proceedings of the 2003 International Symposium on, vol. 3, 2003, pp. III–447–III–450 vol.3. [3] M. Paparo, “Power management systems on silicon for portable equipment,” in Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on, vol. 1, 2001, pp. 13–18 vol.1. [4] S. Sakiyama, J. Kajiwara, M. Kinoshita, K. Satomi, K. Ohtani, and A. Matsuzawa, “An on-chip high-efficiency and low-noise DC/DC converter using divided switches with current control technique,” in
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Solid-State Circuits Conference, 1999. Digest of Technical Papers. ISSCC. 1999 IEEE International, 1999, pp. 156–157. A. Dancy, R. Amirtharajah, and A. Chandrakasan, “High-efficiency multiple-output DC-DC conversion for low-voltage systems,” Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 8, no. 3, pp. 252–263, 2000. W. Namgoong, M. Yu, and T. Meng, “A high-efficiency variable-voltage CMOS dynamic dc-dc switching regulator,” in Solid-State Circuits Conference, 1997. Digest of Technical Papers. 44th ISSCC., 1997 IEEE International, 1997, pp. 380–381, 489. V. Yousefzadeh, E. Alarcon, and D. Maksimovic, “Three-level buck converter for envelope tracking applications,” Power Electronics, IEEE Transactions on, vol. 21, no. 2, pp. 549–552, 2006. ——, “Efficiency optimization in linear-assisted switching power converters for envelope tracking in RF power amplifiers,” in Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on, 2005, pp. 1302–1305 Vol. 2. W. Lau and S. Sanders, “An integrated controller for a high frequency buck converter,” in Power Electronics Specialists Conference, 1997. PESC ’97 Record., 28th Annual IEEE, vol. 1, 1997, pp. 246–254 vol.1. D. Maksimovic, R. Zane, and R. Erickson, “Impact of digital control in power electronics,” in Power Semiconductor Devices and ICs, 2004. Proceedings. ISPSD ’04. The 16th International Symposium on, 2004, pp. 13–22. B. Patella, A. Prodic, A. Zirger, and D. Maksimovic, “High-frequency digital PWM controller IC for DC-DC converters,” Power Electronics, IEEE Transactions on, vol. 18, no. 1, pp. 438–446, 2003. A. Syed, E. Ahmed, D. Maksimovic, and E. Alarcon, “Digital pulse width modulator architectures,” in Power Electronics Specialists Conference, 2004. PESC 04. 2004 IEEE 35th Annual, vol. 6, 2004, pp. 4689–4695 Vol.6. J. Xiao, A. Peterchev, and S. Sanders, “Architecture and IC implementation of a digital VRM controller,” in Power Electronics Specialists Conference, 2001. PESC. 2001 IEEE 32nd Annual, vol. 1, 2001, pp. 38–47 vol. 1. L. Nielsen, C. Niessen, J. Sparso, and K. van Berkel, “Low-power operation using self-timed circuits and adaptive scaling of the supply voltage,” Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 2, no. 4, pp. 391–397, 1994. C. J. Myers, Asynchronous Circuit Design. Wiley-Interscience, 2001. T. L. Booth, Sequential Machines and Automata Theory. John Wiley and Sons, Inc., 1967. P. Midya, K. Haddad, and M. Miller, “Buck or boost tracking power converter,” Power Electronics Letters, IEEE, vol. 2, no. 4, pp. 131–134, 2004. B. Sahu and G. Rincon-Mora, “A high-efficiency, dual-mode, dynamic, buck-boost power supply IC for portable applications,” in VLSI Design, 2005. 18th International Conference on, 2005, pp. 858–861. ——, “A high-efficiency linear RF power amplifier with a powertracking dynamically adaptive buck-boost supply,” Microwave Theory and Techniques, IEEE Transactions on, vol. 52, no. 1, pp. 112–120, 2004. W. Zhou and T. Phillips, Industry’s First 4-Switch Buck-Boost Controller Achieves Highest Efficiency Using a Single Inductor, Linear Technology, 2005, design Note 369. D. Muller and W. Bartky, “A theory of asynchronous circuits,” in Proceedings of International Symposium on the Theory of Switching, H. U. Press, Ed., vol. 29, April 1959, pp. 204–243. T.-Y. Wuu and S. Vrudhula, “A design of a fast and area efficient multi-input Muller C-element,” Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 1, no. 2, pp. 215–219, 1993. S. Barnes and P. Lefley, “Finite state machine brings high frequency, adaptive control to power electronics applications,” in Applied Power Electronics Conference and Exposition, 1999. APEC ’99. Fourteenth Annual, vol. 2, 1999, pp. 974–979 vol.2. Y.-H. Lam, W.-H. Ki, C.-Y. Tsui, and D. Ma, “Integrated 0.9 V charge-control switching converter with self-biased current sensor,” in Circuits and Systems, 2004. MWSCAS ’04. The 2004 47th Midwest Symposium on, vol. 2, 2004, pp. II–305–II–308 vol.2. B. Sahu and G. Rincon-Mora, “A low voltage, dynamic, noninverting, synchronous buck-boost converter for portable applications,” Power Electronics, IEEE Transactions on, vol. 19, no. 2, pp. 443–452, 2004.
Abstract—In this paper, a simple, fully digital, asynchronous finite state machine controller for buck-boost power converters is introduced and simulated. With the addition of only two analog voltage comparators and six power MOS switches, the circuit can generate an output voltage that is able to track a dynamic reference with a 1 MHz bandwidth with good efficiency using a 0.35 μ m CMOS process. The controller also provides adiabatic charging and discharging of capacitive loads.
I. I NTRODUCTION In telecommunications and computing systems, the continuous trend in miniaturizing power processing subsystems, which are in charge of guaranteeing high efficiency in the use of supply energy, stands from the global system-level impact of those subsystems in terms of volume and weight, and thus on portability. This statement is particularly true for current and future generation systems-onchip (SOC), a trend which provides a line of convergence for the implementation of systems for portable, mobile and autonomous applications, in which power management is one of the key performance limiting factors as regards to ergonomics and operability time. The ultimate step consequently consists in the fully monolithic integration of the power converter together with the same circuits which constitute its load [1–4]. On-chip efficient power management circuits usually focus on integrating a regulator, a circuit which pursues a stable output regardless of perturbations in both the output load and input power source. There are indeed a few challenging applications in which the output of the converter is forced to track a wideband time-varying signal. Among the different applications for such wideband amplifiers, we could point out three cases with stringent specifications, namely A) MEMS-based capacitive actuators, where the positive-feedback pull-in effect can be overcome applying time-variable supply, B) System-level optimization of power consumption in digital circuits, via Adaptive Voltage Scaling scheme (AVS) [5, 6], C) Envelope Elimination and Restoration (EER) or Kahn technique [7, 8], which theoretically allows implementation of linear highly efficient RF Power Amplifiers (as required by RF power amplification in modern digital modulations such as in EDGE and UMTS as well as in WiLAN and 4G applications that exhibit significant envelope modulation by adaptively supplying the RF PA with the wideband baseband envelope signal via a switching power converter, of the type usually applied to efficient DC-DC conversion. One of the key remaining challenges for a successful realization of such systems is the practical implementation of the efficient, wide-bandwidth tracking power converter. Independently of whether the power converter operates in a regulator or amplifier application, one additional challenge is that of designing the control scheme and modulation law to drive the converter [9]. Recently, feasibility of practical high-frequency,
978-1-4244-1684-4/08/$25.00 ©2008 IEEE
high-performance digital controllers for DC-DC applications has been demonstrated [10]. Based on custom VLSI realizations of the key building blocks, including high-resolution high-frequency digital pulse-width modulators (DPWM), simplified discrete-time compensator schemes, and A/D converters, such controllers can offer the advantages of lower sensitivity to parameter variations, programmability, and reduction or elimination of external passive components, without compromising dynamic performance, simplicity or cost [11–13]. Application of digital controllers in the field of power converters frequently rise problems regarding efficiency due to their power consumption. One of the causes is the requirement of a very low latency synchronous digital circuit, which implies high-frequency clock signals routed system-wide (thus highly capacitively loaded) that are continuosly dissipating power. On the contrary, since asynchronous digital controllers are clockless, they have a very low power consumption as opposed to synchronous controllers [14] and an extremely low latency (they don’t need to wait one clock period to change their internal state). Clock elimination avoids the need of buffers to reduce clock skew as well as electromagnetic interference [15]. Despite all those advantages, asynchronous design is more complex and there are still few design tools to ease the task. Asynchronous digital circuits are usually described with a Finite State Machine model or FSM [16]. Asynchronous finite state machines are referred as AFSM. This description provides a graphical and simple representation of the behavior of small and medium size digital sequential systems. This paper focuses on the on-chip integration of a switching power converter targeting wideband tracking application using asynchronous digital control. In Section II the power converter architecture is presented. In Section III the AFSM controller architecture and implementation is explained in detail and in Section IV the simulation results are shown. II. S YSTEM ARCHITECTURE The the non-inverting buck-boost power converter schematic is shown in figure 1 [17–20]. The input voltage is connected to VIN and the output voltage is available in VOU T . CL and RL model the load and the inductor acts as an energy transfer element. M1 , M2 , M3 , M4N , M4P and M5 are power MOS transistors and all the others are small MOS switches. The gate voltage VGx of the MOS transistors are logically driven directly by the AFSM controller. The switch M4 was implemented as a pass gate instead of a single PMOS transistor in case of VOU T is required to go below the PMOS threshold voltage.
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VG5
VG4N M5
VIN
M4N
L
M1
VOU T M4P
VG1
M2
M3
VG2
VG4P
CL
RL
VG3
VLIM M2b
M3b
M6
M7
VG6
+
VG7
− U1
VG1
AFSM VREF
+
VOU T
−
VG2 VG3 VG4P
Figure 2. Finite state machine controller diagram. The conditions are represented as physical variables instead of the comparator outputs for clarity purposes.
VG4N U2
VG5 VG6 VG7
Figure 1. Power converter circuit schematic. M1 , M2 , M3 , M4N , M4P and M5 are power MOS switches and M2b , M3b , M5 and M6 are small MOS switches, all driven by the AFSM controller. U1 and U2 are voltage comparators.
•
The running sequence generated by the AFSM controller depends on a comparator that detects whether VOU T is below or above a reference or desired voltage VREF . The AFSM controller also requires to know the inductor current sign and if the inductor current reaches a certain limit ILIM . This current can be measured indirectly by monitoring the voltage drop of either VDS2 if M2 is on or VDS3 if M3 is on. The voltage is compared either with zero if the sequence requires to detect when the inductor is discharged or with a constant positive voltage VLIM if the sequence requires to detect when its current reaches a certain limit. VLIM is related to the inductor current limit ILIM by means of VLIM = ILIM RON
•
•
•
(1)
where RON is the on resistance of M2 or M3 switches. Since the controller only requires to know either the current sign or current limit at each state, a simple multiplexing circuit is used, implemented by M2b , M3b , M5 and M6 . This way, allowing a single comparator to perform all current detection of the inductor reduces the power consumption and thereby increases efficiency. Despite two additional control signals are needed, namely VG6 and VG7 , they can be easily generated by the AFSM controller. III. T HE FINITE STATE MACHINE CONTROLLER
transistors are M1 , M3 , M3b and M6 . LtoC transfers energy from the charged inductor to the output load. If the output voltage reaches the reference, it jumps to LtoV to return the remaining energy of the inductor to the source. If the inductor discharges completely without the output voltage reaching the reference, the state jumps to ChgL to begin another charging cycle. Active transistors are M2 , M2b , M4x and M7 . LtoV returns the remaining inductor energy (if any) to the source. When it is done, it jumps back to ChgL if the output voltage is below the refence of to CtoL if is above. Active transistors are M2 , M2b , M5 and M7 . CtoL transfers energy from the capacitor to the inductor, thus decreasing the output voltage, until it reaches the reference or the inductor current reaches a limit. Then it jumps to DisL. Active transistors are M2 , M2b , M4 and M6 . DisL returns energy to the source. When it is done it jumps to CtoL if the output voltage is still above the reference or to ChgL if not. Active transistors are M1 , M3 , M3b and M7 .
Each state is divided in two or three substates to implement a deadtime in the outputs to avoid current shoot across the MOS switches. The duration of the deadtime is taken from the constant time response of a chain of starving inverters. This solution provides a wide tuning range while keeping a very low power consumption. Another chain of starving inverters implement a stabilization time delay that the AFSM must wait just after entering in a new state before it can change of state again. This is necessary to avoid anomalous behaviors due to the nonzero response time of the comparators.
A. Architecture
B. Implementation
The AFSM controller diagram is shown in figure 2, where the circles represent major states. The state names and their function are summarized in the following list: • ChgL charges the inductor until its current reaches the specified limit ILIM . When this happens, the state jumps to LtoC. Active
The AFSM was coded in Verilog directly at gate level to avoid hazards or glitches caused by the logical simplifications done by the commercial available synthesizers, while allowing the possibility of automatic layout drawing. Glitches or hazards are acceptable on synchronous design as long as they disappear before the next clock
2211
TABLE I G ENERALIZED C- ELEMENT S TATE T RANSITION TABLE S
R
Q+
0
0
Q
0
1
0
1
0
1
1
1
Q
S R
Q
Figure 4. Transient response of the power converter. The plots show the output voltage VOU T for various constant values of reference voltage VREF . VIN was set to 3.3 V , L = 1 μH, CL = 10 nF and RL = 133 Ω.
event, however, they increase the power consumption and can cause unwanted switching of the output transistors of the power converter, thereby decreasing efficiency. Also, they are a major cause of errors in asynchronous design, as glitches cannot be easily distinguished from real transitions in most of the asynchronous implementations. In order to ease the design task and reduce the risk of glitches in the outputs, each state is implemented by using gate-level descriptions of generalized C-elements (gC) [21] and some simple additional logic. gC-elements are a type of latch with decoupled set and reset inputs. The state transition table of the gC-element is shown in table I and a gate level implementation, similar to those published in [22], in figure 3. Each of the five states has, at least, a set and a reset signal. Their set signal is generated by performing a logical AN D operation between the output of the substate from the controller can jump from and the jump condition itself, while their reset signal is generated by performing a logical OR operation of the outputs of the substates to the controller can jump to. The circuit has also an external global reset signal.
however, due to the nonzero time response of the comparators and the controller, which cause a delayed controller state change. Figure 5 shows the behavior of the power converter for a dynamic input reference, consisting in a 1 M Hz triangular wave. The value of the gate voltages of the power transistors and current drained from the input VIN are also shown in order to assess the behavior of the controller. Although it might seem that the tracking error is high, an improved topology based on the linear-assisted scheme can be applied in this case, thus increasing the overall efficiency of the system. The effect of the delay of the comparators and the controller is an output voltage going slightly above the reference at the end of the LtoC state during the rising edge of the triangle input waveform and going slightly below the reference at the end of the CtoL state during the falling edge. Those effects are expected to be much smaller with faster deep submicron technologies. Also, if at least one more bit of information about the difference between output voltage VOU T and the reference VREF is made available to the controller, the inductor could be charged with less energy during the ChgL state if this difference is small, making the charging of the output capacitor during LtoC state much slower and reducing the effect of a slow circuitry at the output voltage. This will also increase efficiency since it will reduce the amount of remaining energy that has to so be returned to the source during the LtoV state. Moreover, if the load is mainly capacitive, the controller could be stopped if the difference is small enough.
IV. R ESULTS
V. C ONCLUSION
The circuit was simulated at transistor-level with Spectre in the AMIS C035U 0.35 μm CMOS process and it will be manufactured in the near future. The width of the power MOS transistors has been set in order to have a RON resistance of 0.5 Ω. The inductor parasitic resistance was set to 0.2 Ω based on a commerciallyavailable inductor datasheet. The AFSM controller netlist has been implemented using standard cells of the digital library provided with the design kit to allow automatic layout routing. In figure 4 the output voltage for some values of the reference voltage is shown. The efficiency reaches 75% for VREF = 3.3 V and the circuit parameters of the figure. Peak efficiency was found to be beyond 80%. The ripple that can be observed for high output voltages is due to the discharge of the output capacitor by the resistive load, and can be easily reduced increasing the size of the output capacitor. The output ripple that can be observed for low output voltages is,
In this paper we have shown the suitability of asynchronous digital controllers for power converters. We also have presented a simple AFSM controller for buck-boost power converters with the capability of adiabatic charging and discharging of capacitive loads and found its main limitations, which are related to the circuit latency. Simulated response indicates 75% efficiency with a 8.5 M Hz switching frequency in a 0.35 μm CMOS process technology. Both bandwidth and efficiency is expected to increase with advanced submicron technologies, while output ripple is expected to decrease. The AFSM netlist description in Verilog and a minimal analog circuitry allows for easy portability of the design amongst different manufacturing processes, for automatic layout generation and routing of the controller from a library of standard digital cells and also for reducing the design cycle or time to market of products which require power converters.
Figure 3. Generalized C-element gate-level implementation. S is the set signal, R is the reset signal and Q is the output.
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[13] Figure 5. Behavior of the power converter for a dynamic input reference. The plots show the output voltage VOU T , the current drained by the converter IIN and the gate voltages of the power transistors for a positive triangle waveform of 1 μs period, also shown. VIN was set to 3.3 V , L = 1 μH, CL = 5 nF and RL = 220 Ω.
The presented circuit can be used in environments where a high frequency output is required, such as Adaptive Voltage Scaling (AVS) and Envelope Elimination and Restoration (EER) or in applications where the load has a significant capacitive component, such as in MEMS capacitive actuator driving or also as a simple and fast replacement of classic inductor-based power converters.
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ACKNOWLEDGMENT This work was supported in part by the Spanish Ministry of Education and Science under Projects TEC2004-03940, TEC200767144/MIC and TEC2004-05608-C02-01 from the Spanish MCYT and EU FEDER. Daniel Fernández holds a research fellowship supported by the Catalan Department of Universities, Research and Information Society (DURSI) and the European Social Fund (ESF).
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