An improved frequency compensation techinique for low ... - IEEE Xplore
AN IMPROVED FREQUENCY COMPENSATION TECHINIQUE FOR LOW POWER,LOW VOLTAGE CMOS AMPLIFIERS Preetam Tadeparthy Boradband SiliconTechnology center , Texas Instruments India Ltd Bandgalore, India. [email protected] the portable devices requirement, where the power consumption needs to be minimized. All these requirements imply that the Op Amps need to have highspeed high-gain very good linearity and consume very little power.
ABSTRACT This paper presents an improved frequency compensation technique for low power and low voltage CMOS operational amplifier. The Op Amp designed for a high speed high resolution pipeline ADC is a two-stage with folded-cascode as the first stage and uses this improved compensation technique to achieve closed loop bandwidth of 350MHz while driving a 2K resistor load and a 3.5pF capacitive load consuming much lower power when compared to the conventional miller compensation technique or cascode compensation technique. The Op Amp was designed in a 0.15-µm CMOS technology and achieves a THD of 70dB for a 30MHz signal and consumes a total power of 4mW of a 1.35V supply.
II BRIEF ON EXISTING TECHNIQUE AND ISSUES The most commonly used op amp configuration in CMOS has two gain stages, the first one being the differential input stage and the second one is typically a class A or AB depending on the loading requirements. Each stage is typically designed to give a gain in the range of 100. Figure 1 and figure 2 show the conventional amplifier described in literature.
I. INTRODUCTION Mixed-signal systems where analog signals are quantized into digital data for processing in the digital domain have gain overwhelming popularity over years. The performance of such system relies on the performance of the data converter used. The demand for the highresolution and high-speed data converters has continually increased in telecommunication and digital signal processing applications. Meanwhile, the operating voltage of integrated circuits becomes lower every year, following the advances in CMOS technology, thus reducing signal swings and increasing power consumption in contract to
Briefly, in figure 1 transistors M1 to M10 from the input differential stage and M11 and M14 from the output inverting gain stage. The series RC network across the second gain stage provides the frequency compensation for the Op Amp. This circuit, previously analyzed by many authors [1] , displays a dominant pole, two complex poles ,one real pole and a zero which can be moved from the right half to left half plane by increasing the value of the resistance value.
Figure 1 : Conventional Miller Compensation
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,
,6&$6
This technique when used for high bandwidth and lowpower application poses the following problems 1) The op amp stability is severely degraded when the load capacitance becomes larger. 2) The ground PSRR incase of an NMOS second stage also degrades severely at high frequencies. 3) Because the non-dominant pole actually sits at the unity gain frequency of the second stage, with increase in parasitic at the output of the second stage the scheme’s efficiency drops rapidly and extra power needs to be burnt to get back the same phase margin. To solve some of the above-referred issues new frequency compensation techniques was introduced [2] where the compensation capacitor is connected at the cacode node i.e. between the source of MP9/MP10 and the output. The capacitor Cc network connected between the source nodes of the cascode transistors M9, M10 and, the output of the op amp provides the frequency compensation for the op amp. This technique provides better phase margin for the same power because of higher loop gain the compensation capacitor sees once it is closed i.e. in case of miller compensation technique if the non-dominant pole, which was coming approximately at the UGB of the second stage, was degraded because of β factor seen by the compensation capacitor with the parasitic capacitor at the gate of the transistor, cascode compensation reduces the parasitic capacitor seen, secondly the loop gain also involves the cascode gain and hence the pole now moves to higher frequency giving better phase margin.
the output stage (Gain Stage B) were in cascade and the overall feedback is because the Compensation capacitor. Because of large parasitic at the output of the Gain stage A, (which was the reason cascode compensation was chosen), and the high output impedance because of cascoded gain stage there is a low frequency pole associated at the output of gain stage A. similarly because of high load capacitance and high impedance in the output stage there is another low frequency pole at the output of the gain stage B. When the overall loop because of the compensation capacitor is closed inevitably the two poles can end up becoming complex poles and move to approximately the unity gain frequency the compensation loop. These complex poles do not cause any phase/gain margin degradation if the bandwidth requirement is not high. But in the case of amplifier for very high-speed ADC or filters, these complex poles manifest both in phase margin, if they are within or close to UGB of the overall amplifiers and gain margin (Small kink in gain plot after UGB which can cause gain greater than 1 ) if they are causing the damping factor become too small . To get rid of these poles the only way is to reduce the parasitic capacitance at the output of the stage 1 or burn more power to push these complex poles to very high frequency. We present a new compensation technique where we use the advantage of the fact that cascode compensation gives much better loop gain to compensate and introduce another compensation loop to take care of the complex pole problem.
The only catch is if the poles do not merge and become complex on closing the compensation loop. To visualize it better, in case of cascode compensation, the scheme can be split as if the cascode transistors (Gain stage A) and
Figure 2: Proposed new frequency compensation technique
,
The two complex poles are approximately the roots of
III IMPROVED FREQUENCY COMPENSATION TECHNIQUE
S2[(Cc1 +C2)(Cc2 +CL)C1 +(Cc2 +C1)C2Cc1 +(Cc1 +C2)CLCc2]
+S[Gm2C2(CL +Cc2 +Cc1) +Gm2Cc1CL +Gm5Cc1(Cc2 +C1)]
The idea is based on the simple technique that two poles under close loop can cause complex poles only if the separation between them in open loop is not good enough. Another metric to tell that is , the phase margin of the internal loop is better than 66ο , so that when the over all loop is closed they still remain real. To achieve 66ο phase margin is to tell that the overall really does not need too much compensation because the two dominant poles are really far apart. To solve this oxymoron we introduce a small compensation loop using a small capacitor across the output gain stage.
+[Gm2Gm3(Cc1 +Cc2]
It can be easily shown that for typical values of C1, C2, CL, and trasconductance, the effect of Cc1 is to split the complex poles further. Figure 4 shows the root locus plot of the two complex plots with Cc1 varied from 0 to 300ff. The advantage of this scheme comes from the fact that the additional capacitance does not cause us any additional area penalty and does not cause any UGB loss as conceived by conventional (multi-loop) capacitance compensation. The reasoning for the above conjecture can be given as follows. Typical way to compensate such 2/multi stage amplifiers is to keep increasing the value of Cc till such a time that all the non-dominant poles are outside UGB. This not only causes area penalty but also reduction in UGB (same argument can be extended to multi stage too). Here instead of over compensating by increasing the value, we are distributing the total capacitance between the two loops in such a way that the over all UGB improves and the phase margin is also better. This is obvious because we need a very small capacitance (Cc1) to do just enough pole splitting such that the cascode loop does not end up having complex poles and degrade the over all response.
Figure 3: Small signal for figure 3 (Neglecting Rz)
The circuit shown in figure 2 has an additional capacitor Cc1 which is connected between the first stage output and the second stage output acting like an miller capacitor giving the required pole splitting such that when the overall cascode loop is closed the poles do not end up giving complex poles. The small signal model for the network is shown in figure 3. From such an arrangement the complete transfer function is not presented because it does not add too much value. Instead the non-dominant poles and Zeros are given below. The open loop transfer function has one real pole at very low frequency, two poles(which can become complex if Cc1 is not properly chosen) and two zeros. The unity gain frequency is approximately given by ωu ∼ Gm1/Cc2 (1) The two zeros are given by: Z1, 2
Gm1 * C c1 +
−
Gm 2 * C c1 + 4 G m 2 G m1C c 2 (C c1 + C1 ) 2
2
C c 2 (C c1 + C 2 )
Figure 4 Plot of the two complex poles with change in Cc1 (Cc1 increase causes the poles to split ) (X axis being Real Axis and Y - Im)
,
IV. IMPLEMENTATION AND SIMULATION RESULTS A prototype of this amplifier was build using a 0.15µ CMOS process. Although the above-described scheme can be applied to any MOS amplifier design, it lends a relatively simple implementation in CMOS technology. An amplifier to drive a switch capacitor load in a 10 Bit 80 MHz pipeline ADC was designed. The total load was 3.5pF.The Frequency response of the prototype is shown in figure 5. It is very apparent that with and without Cc1 the gain and phase margin do show a significant improvement. In the design compensation capacitors were connected from both Pside cascode node and N side cascode node. This is to improve the stability during amplifier slew from either side. Putting it from either side gives only a marginal degradation (only choice being the N side cascode node has lesser parasitic capacitance when compared to p Side).
V.CONCLUSIONS An improved frequency compensation technique has been described with a brief review of the existing techniques. A CMOS implementation of the technique proposed has also been presented with simulation results, which show considerable high-frequency gain, and phase margin improvements over existing techniques consuming lower power and performing (>70dB) up to 30 MHz input single tone waveform driving a switched capacitor ADC input stage. A quick comparison reveals other 2-stage implementations (Simple miller and cascode compensation) needed at least ~1.5X capacitance value and ~1.4X power consumption to achieve the same GBW and Distortion performance. Further more this techniques is generic and can be extended to any number of stage design. It is appropriate to tell here that, because of an additional loop, without degrading the UGB, in the signal path the over distortion performance also improved by 3dB[3]. Table 1 . Summary of Op Amp Specifications
P H A S E
D B
Specifications DC Gain (dB) Unity Gain BW (MHz) Phase margin (Degree) CL (pF) Cc1, Cc2 (fF) Settling Time (ns) Noise (nV/rt.Hz) Supply (V) Swing (V) Power Consumption (mW)
Figure 5: Frequency Plot with and Without Cc1 of 150f
Design results 75 350(Min) 55(Min) 3.5 150,250 5.2 151@1KHz 6.9@10MHz 1.35 1.1 4
The FFT of the output waveform with a switch capacitor load of the ADC sampled at 80 MHz is shown in figure 6
Reference Fundamental
3.5MHz Supply Tone
[1] B.Ahuja, “ An improved frequency compensation technique for CMOS Operational Amplifier ”,IEEE JSSC,Vol.18,No.6,pp.629-633,Dec,1983 [2] D.B.Ribner and M.A.Copeland, ”Design techniques for cascaded CMOS Op Amps with Improved PSRR and Common-Mode Input Range ”, IEEE JSSC,Vol.SC19,No.6,pp.1122-1132,Dec 1985
HD3
[3] G. Palumbo, S.Pennisi, “ High-Frequency Harmonic Distortion in Feedback Amplifiers: Analysis and Applications ”, IEEE TCAS-I, Vol.50, No.3, pp.328-340, March 2003.
Figure 6 : FFT of a 29.7MHz 1 V pp Input Signal sampled on a S/W Capacitor ADC at 80 MHz(Plot Folds at 40 MHz)
,
ABSTRACT This paper presents an improved frequency compensation technique for low power and low voltage CMOS operational amplifier. The Op Amp designed for a high speed high resolution pipeline ADC is a two-stage with folded-cascode as the first stage and uses this improved compensation technique to achieve closed loop bandwidth of 350MHz while driving a 2K resistor load and a 3.5pF capacitive load consuming much lower power when compared to the conventional miller compensation technique or cascode compensation technique. The Op Amp was designed in a 0.15-µm CMOS technology and achieves a THD of 70dB for a 30MHz signal and consumes a total power of 4mW of a 1.35V supply.
II BRIEF ON EXISTING TECHNIQUE AND ISSUES The most commonly used op amp configuration in CMOS has two gain stages, the first one being the differential input stage and the second one is typically a class A or AB depending on the loading requirements. Each stage is typically designed to give a gain in the range of 100. Figure 1 and figure 2 show the conventional amplifier described in literature.
I. INTRODUCTION Mixed-signal systems where analog signals are quantized into digital data for processing in the digital domain have gain overwhelming popularity over years. The performance of such system relies on the performance of the data converter used. The demand for the highresolution and high-speed data converters has continually increased in telecommunication and digital signal processing applications. Meanwhile, the operating voltage of integrated circuits becomes lower every year, following the advances in CMOS technology, thus reducing signal swings and increasing power consumption in contract to
Briefly, in figure 1 transistors M1 to M10 from the input differential stage and M11 and M14 from the output inverting gain stage. The series RC network across the second gain stage provides the frequency compensation for the Op Amp. This circuit, previously analyzed by many authors [1] , displays a dominant pole, two complex poles ,one real pole and a zero which can be moved from the right half to left half plane by increasing the value of the resistance value.
Figure 1 : Conventional Miller Compensation
;,(((
,
,6&$6
This technique when used for high bandwidth and lowpower application poses the following problems 1) The op amp stability is severely degraded when the load capacitance becomes larger. 2) The ground PSRR incase of an NMOS second stage also degrades severely at high frequencies. 3) Because the non-dominant pole actually sits at the unity gain frequency of the second stage, with increase in parasitic at the output of the second stage the scheme’s efficiency drops rapidly and extra power needs to be burnt to get back the same phase margin. To solve some of the above-referred issues new frequency compensation techniques was introduced [2] where the compensation capacitor is connected at the cacode node i.e. between the source of MP9/MP10 and the output. The capacitor Cc network connected between the source nodes of the cascode transistors M9, M10 and, the output of the op amp provides the frequency compensation for the op amp. This technique provides better phase margin for the same power because of higher loop gain the compensation capacitor sees once it is closed i.e. in case of miller compensation technique if the non-dominant pole, which was coming approximately at the UGB of the second stage, was degraded because of β factor seen by the compensation capacitor with the parasitic capacitor at the gate of the transistor, cascode compensation reduces the parasitic capacitor seen, secondly the loop gain also involves the cascode gain and hence the pole now moves to higher frequency giving better phase margin.
the output stage (Gain Stage B) were in cascade and the overall feedback is because the Compensation capacitor. Because of large parasitic at the output of the Gain stage A, (which was the reason cascode compensation was chosen), and the high output impedance because of cascoded gain stage there is a low frequency pole associated at the output of gain stage A. similarly because of high load capacitance and high impedance in the output stage there is another low frequency pole at the output of the gain stage B. When the overall loop because of the compensation capacitor is closed inevitably the two poles can end up becoming complex poles and move to approximately the unity gain frequency the compensation loop. These complex poles do not cause any phase/gain margin degradation if the bandwidth requirement is not high. But in the case of amplifier for very high-speed ADC or filters, these complex poles manifest both in phase margin, if they are within or close to UGB of the overall amplifiers and gain margin (Small kink in gain plot after UGB which can cause gain greater than 1 ) if they are causing the damping factor become too small . To get rid of these poles the only way is to reduce the parasitic capacitance at the output of the stage 1 or burn more power to push these complex poles to very high frequency. We present a new compensation technique where we use the advantage of the fact that cascode compensation gives much better loop gain to compensate and introduce another compensation loop to take care of the complex pole problem.
The only catch is if the poles do not merge and become complex on closing the compensation loop. To visualize it better, in case of cascode compensation, the scheme can be split as if the cascode transistors (Gain stage A) and
Figure 2: Proposed new frequency compensation technique
,
The two complex poles are approximately the roots of
III IMPROVED FREQUENCY COMPENSATION TECHNIQUE
S2[(Cc1 +C2)(Cc2 +CL)C1 +(Cc2 +C1)C2Cc1 +(Cc1 +C2)CLCc2]
+S[Gm2C2(CL +Cc2 +Cc1) +Gm2Cc1CL +Gm5Cc1(Cc2 +C1)]
The idea is based on the simple technique that two poles under close loop can cause complex poles only if the separation between them in open loop is not good enough. Another metric to tell that is , the phase margin of the internal loop is better than 66ο , so that when the over all loop is closed they still remain real. To achieve 66ο phase margin is to tell that the overall really does not need too much compensation because the two dominant poles are really far apart. To solve this oxymoron we introduce a small compensation loop using a small capacitor across the output gain stage.
+[Gm2Gm3(Cc1 +Cc2]
It can be easily shown that for typical values of C1, C2, CL, and trasconductance, the effect of Cc1 is to split the complex poles further. Figure 4 shows the root locus plot of the two complex plots with Cc1 varied from 0 to 300ff. The advantage of this scheme comes from the fact that the additional capacitance does not cause us any additional area penalty and does not cause any UGB loss as conceived by conventional (multi-loop) capacitance compensation. The reasoning for the above conjecture can be given as follows. Typical way to compensate such 2/multi stage amplifiers is to keep increasing the value of Cc till such a time that all the non-dominant poles are outside UGB. This not only causes area penalty but also reduction in UGB (same argument can be extended to multi stage too). Here instead of over compensating by increasing the value, we are distributing the total capacitance between the two loops in such a way that the over all UGB improves and the phase margin is also better. This is obvious because we need a very small capacitance (Cc1) to do just enough pole splitting such that the cascode loop does not end up having complex poles and degrade the over all response.
Figure 3: Small signal for figure 3 (Neglecting Rz)
The circuit shown in figure 2 has an additional capacitor Cc1 which is connected between the first stage output and the second stage output acting like an miller capacitor giving the required pole splitting such that when the overall cascode loop is closed the poles do not end up giving complex poles. The small signal model for the network is shown in figure 3. From such an arrangement the complete transfer function is not presented because it does not add too much value. Instead the non-dominant poles and Zeros are given below. The open loop transfer function has one real pole at very low frequency, two poles(which can become complex if Cc1 is not properly chosen) and two zeros. The unity gain frequency is approximately given by ωu ∼ Gm1/Cc2 (1) The two zeros are given by: Z1, 2
Gm1 * C c1 +
−
Gm 2 * C c1 + 4 G m 2 G m1C c 2 (C c1 + C1 ) 2
2
C c 2 (C c1 + C 2 )
Figure 4 Plot of the two complex poles with change in Cc1 (Cc1 increase causes the poles to split ) (X axis being Real Axis and Y - Im)
,
IV. IMPLEMENTATION AND SIMULATION RESULTS A prototype of this amplifier was build using a 0.15µ CMOS process. Although the above-described scheme can be applied to any MOS amplifier design, it lends a relatively simple implementation in CMOS technology. An amplifier to drive a switch capacitor load in a 10 Bit 80 MHz pipeline ADC was designed. The total load was 3.5pF.The Frequency response of the prototype is shown in figure 5. It is very apparent that with and without Cc1 the gain and phase margin do show a significant improvement. In the design compensation capacitors were connected from both Pside cascode node and N side cascode node. This is to improve the stability during amplifier slew from either side. Putting it from either side gives only a marginal degradation (only choice being the N side cascode node has lesser parasitic capacitance when compared to p Side).
V.CONCLUSIONS An improved frequency compensation technique has been described with a brief review of the existing techniques. A CMOS implementation of the technique proposed has also been presented with simulation results, which show considerable high-frequency gain, and phase margin improvements over existing techniques consuming lower power and performing (>70dB) up to 30 MHz input single tone waveform driving a switched capacitor ADC input stage. A quick comparison reveals other 2-stage implementations (Simple miller and cascode compensation) needed at least ~1.5X capacitance value and ~1.4X power consumption to achieve the same GBW and Distortion performance. Further more this techniques is generic and can be extended to any number of stage design. It is appropriate to tell here that, because of an additional loop, without degrading the UGB, in the signal path the over distortion performance also improved by 3dB[3]. Table 1 . Summary of Op Amp Specifications
P H A S E
D B
Specifications DC Gain (dB) Unity Gain BW (MHz) Phase margin (Degree) CL (pF) Cc1, Cc2 (fF) Settling Time (ns) Noise (nV/rt.Hz) Supply (V) Swing (V) Power Consumption (mW)
Figure 5: Frequency Plot with and Without Cc1 of 150f
Design results 75 350(Min) 55(Min) 3.5 150,250 5.2 151@1KHz 6.9@10MHz 1.35 1.1 4
The FFT of the output waveform with a switch capacitor load of the ADC sampled at 80 MHz is shown in figure 6
Reference Fundamental
3.5MHz Supply Tone
[1] B.Ahuja, “ An improved frequency compensation technique for CMOS Operational Amplifier ”,IEEE JSSC,Vol.18,No.6,pp.629-633,Dec,1983 [2] D.B.Ribner and M.A.Copeland, ”Design techniques for cascaded CMOS Op Amps with Improved PSRR and Common-Mode Input Range ”, IEEE JSSC,Vol.SC19,No.6,pp.1122-1132,Dec 1985
HD3
[3] G. Palumbo, S.Pennisi, “ High-Frequency Harmonic Distortion in Feedback Amplifiers: Analysis and Applications ”, IEEE TCAS-I, Vol.50, No.3, pp.328-340, March 2003.
Figure 6 : FFT of a 29.7MHz 1 V pp Input Signal sampled on a S/W Capacitor ADC at 80 MHz(Plot Folds at 40 MHz)
,
