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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 57, NO. 10, OCTOBER 2010
813
An Integrated Step-Up/Step-Down DC–DC Converter Implemented With Switched-Capacitor Circuits Chia-Ling Wei, Member, IEEE, Chun-Hsien Wu, Lu-Yao Wu, and Ming-Hsien Shih
Abstract—An integrated step-up/step-down dc–dc converter for battery-powered bioelectronics is presented. Both its power stage and feedback compensator were implemented by using switchedcapacitor circuits. The proposed converter has a wide input range and achieves excellent load regulation. Index Terms—DC–DC power conversion, step-up/step-down, switched capacitor (SC).
I. I NTRODUCTION
M
ORE and more portable bioelectronic products have been introduced to the market recently, and most of them are supplied by batteries, such as cardiac pacemaker and capsule endoscopy. In other words, the service life of these products is determined by their battery life. Moreover, since the battery voltage would decrease with time, a dc–dc converter is typically required to provide a steady output voltage. Hence, a versatile step-up/step-down dc–dc converter is a good choice to extend the battery life and the service life of biomedical electronics. The versatile step-up/step-down dc–dc converters can be implemented by either switching regulator architecture or switched-capacitor (SC) circuits. The switching regulators can provide a high load current with excellent efficiency, but bulky transformers or inductors are required for energy transfer. On the other hand, the SC converters only use capacitors, rather than inductors, but their supplied power is typically less than that of the switching regulators. In fact, portable bio-electronics are typically low-power designs to prolong their service life, but they are very strict with their sizes. Therefore, the SC-based converter is a good choice for these products [1]–[17]. When SC converters were introduced a few decades ago, they had two main drawbacks. First, their voltage conversion ratio is predetermined by the circuit structure. If the input voltage varies, the output voltage changes as well. In other words, their line regulation is very poor. The second problem is the lack of feedback mechanism; thus, their load regulation is also poor. In the past few decades, different control schemes have been Manuscript received May 7, 2010; accepted June 21, 2010. Date of publication August 26, 2010; date of current version October 15, 2010. This work was supported by the National Science Council, Taiwan, under Grant NSC-98-2220-E-006-012. This paper was recommended by Associate Editor H. S.-H. Chung. The authors are with the Department of Electrical Engineering, National Cheng Kung University, Tainan 70101, Taiwan (e-mail: [email protected]. edu.tw). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TCSII.2010.2058594
Fig. 1. Step-up/step-down SC-based dc–dc converter.
proposed to solve these issues [2]–[7], and one of the best solutions is to use a current control scheme [3], [5]–[8]. Fig. 1 shows the adopted SC converter architecture of this work [8]. Moreover, the frequencies of most bio-related signals are very low, and fast transient responses rarely occur. Therefore, to reduce switching loss and also to avoid high-frequency noise, it is preferred to have a low switching frequency for the SC converters used in portable bio-electronics. It means that the bandwidth of the SC converter would be lower, and the poles/zeros of its feedback compensator would also be located at lower frequencies. Furthermore, a built-in compensator would be preferred, because it reduces both device size and cost. However, due to the limited chip area, it is actually difficult to design such a compensator. In this brief, it is proposed to implement the built-in compensator with SC technique. A kilohertz-order pole/zero can be easily realized by SC circuits with a low switching frequency. In addition, it is a trend to integrate microelectromechanical system (MEMS) biosensors with CMOS integrated circuits into a single chip by using CMOS/MEMS processes. Therefore, a MEMS-compatible 0.35-μm CMOS mixed-signal 2P4M polycide 3.3/5 V process is adopted in our design. In fact, it is more possible to achieve a lab-on-a-chip (LOC) by using a 0.35-μm CMOS process, as compared with old technologies. An integrated step-up/step-down SC-based dc–dc converter for bio-electronics is presented. Except for the two energytransferring capacitors, the other parts of the presented
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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 57, NO. 10, OCTOBER 2010
Fig. 2. Block diagram of the integrated SC-based dc–dc converter.
converter, such as its power stage and compensator, were implemented and integrated into a single chip. The load regulation of the presented converter is excellent. Section II describes its block diagram, frequency response, and main circuits, whereas Section III shows the measured results. A short discussion and the conclusion are given in Section IV. II. B LOCK D IAGRAM AND M AIN C IRCUITS Fig. 2 shows the block diagram of the presented converter. The desired input voltage range is 2.5–5.0 V, and its output voltage is set to 3.6 V.
Fig. 3. Timing diagrams of the power switches in the (a) step-up and (b) stepdown modes.
A. SC-Based Power Stage The SC-based power stage is shown in Fig. 1, and it consists of one flying capacitor CM , one load capacitor CL , four power switches (S1 , S1a , S2 , and S2a ), and a voltage-controlled current source (VCCS), which is realized by a PMOS. The timing diagrams of the four switches for the step-up mode (VIN ≤ VOUT ) is shown in Fig. 3(a), whereas those for the step-down mode (VIN > VOUT ) is shown in Fig. 3(b). All clock signals are nonoverlapping, and their frequency is set to 100 kHz in our design [17]. To improve efficiency, switches S1 and S2a were implemented by using transmission gates to reduce their ON -resistance. The other two switches were realized by either NMOS or PMOS only, since they are always conducting to either ground or a high voltage. In the charging phase of the step-up mode, both S1 and S1a are turned on, and the capacitor CM is charged by the VCCS. At this time, the intermediate node voltage VX (see Fig. 1) is slightly lower than the input voltage VIN . In the discharging phase, both S2 and S2a are turned on almost simultaneously, and CM is flipped to be connected in series with VIN to serve the load and CL . During this phase, VX is slightly higher than the output voltage VOUT . Notably, when switching from the discharging phase back to the charging phase again, VX may be temporarily higher than VIN , which would reverse the charging current. To solve this issue, S1a is designed to be turned on slightly earlier than S1 , and S2a is turned on slightly earlier than S2 . In the step-down mode, switch S1a is always turned on, whereas switch S2a is always turned off. During the charging phase, switch S1 is turned on, and CM is charged by the VCCS. During the discharging phase, switch S2 is turned on, and the load and CL are served by CM .
Fig. 4. Equivalent circuits of the SC-based power stage in the (a) step-up and (b) step-down modes.
B. Feedback Circuit To design the feedback circuits, the control-to-output transfer function of the converter is required. The equivalent circuit of the SC-based power stage can be obtained by using the average current method [8], [17], [18]. Fig. 4(a) and (b) shows the equivalent circuit in the step-up and step-down modes, respectively, where r1(AVG) and r2(AVG) is the average resistance
WEI et al.: INTEGRATED STEP-UP/STEP-DOWN DC–DC CONVERTER IMPLEMENTED WITH SC CIRCUITS
Fig. 5.
815
Fig. 6. Soft-start circuit.
PI compensator circuit.
where of switches S1 and S2 over a complete cycle, respectively. Moreover, since the duty ratio of switches S1a and S2a is almost the same as that of S1 and S2 , respectively, their average resistances are assumed to be the same as those of S1 and S2 . Their values can be calculated by r1(AVG) = r1a(AVG) −1 1 ron = 0 · (1 − D) + D = ron D r2(AVG) = r2a(AVG) −1 1 ron = 0 · (D) + (1 − D) = ron 1−D
(1a)
(1b)
(2a)
where Vc is the control voltage of the VCCS, and gm is the transconductance of the VCCS. Similarly, the control-to-output transfer function of the step-down mode is 1 VOUT 2 (1 + sron CL )RL gm . (2b) = 2 Vc 4ron RL CL s2 + (4ron CL + 2RL CL )s + 1
Notably, since S1a is always turned on in the step-down mode, the average resistance of S1a is ron , which is different from r1(AVG) . From (2a) and (2b), both of them have two poles and one zero, and their Bode plots are also similar. Typically, the first pole is located at a very low frequency, and the zero and the second pole are located at relatively high frequencies. Hence, a proportional–integral (PI) compensator is used in this work. Fig. 5 shows the circuit of the PI compensator. In our design, C1 is 50 fF, C2 is 10 pF, Req1 is 2.5 MΩ, and Req2 is 25 MΩ. To save chip area of the built-in compensator, the resistors are actually implemented by using SC circuits. The transfer function of the PI compensator can be derived as HPI (s) =
(1 + s/ω1 ) s/ω2 (1 + s/ω3 )
(3)
1
=
fR CR2 C2
Req2 C2 fR CR1 1 = ω2 = Req1 (C1 + C2 ) (C1 + C2 ) ω3 =
where ron is the ON-resistance of the switches, and D is the duty ratio of S1 [8], [17]. By letting D = 0.5 and CM = CL , the control-to-output transfer function of the converter working in the step-up mode can be derived as 1 VOUT 2 (1 + sron CL )RL gm = 2 Vc 3ron RL CL s2 + (3ron CL + 2RL CL )s + 1
ω1 =
C1 + C2 fR CR2 (C1 + C2 ) = Req2 C1 C2 C1 C2
and fR is the switching frequency of the PI compensator. In our design, fR is set to 400 kHz, four times faster than the switching frequency of the SC-based power stage. The PI compensator contributes one dc pole, one zero, and one high-frequency pole. The dc pole increases the dc loop gain to reduce the steady-state error. The zero is used to cancel the effect of the first pole in the control-to-output transfer function to achieve an adequate phase margin. In addition, the high-frequency pole is used to attenuate the switching noise. In fact, there is one more important advantage by using the SC-implemented resistances. The pole/zero locations of the PI compensator are determined by the RC products. If true resistors are used, it is difficult to precisely control the pole/zero locations due to the large variation in the chip resistance values. On the other hand, when the resistors are implemented by the SC circuits, the pole/zero locations are actually determined by the ratios of capacitors, which is much easier to be well controlled in chip fabrication. Moreover, by alternating the clock sequences of Req1 , it becomes a negative resistance. Therefore, the dc gain of the PI compensator is positive, although the inverting operational amplifier (op amp) configuration is used. A two-stage op amp is adopted as the error amplifier in the PI compensator, because it has a wide output voltage range, which determines the available charging current range of the VCCS. The unity-gain bandwidth of the op amp is designed to be at least ten times higher than its switching frequency fR . C. Soft Start Because the output voltage increases from zero at start-up, a large inrush current will flow through the VCCS if there is not any protection step taken. To prevent this inrush current from damaging the VCCS, it is necessary to implement a soft-start scheme. Fig. 6 shows the soft-start circuit, where the shown op amp is the error amplifier of the PI compensator. A constant current source is used to charge the capacitor Cs at start-up; thus, the capacitor voltage Vcap will increase with time. Before
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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 57, NO. 10, OCTOBER 2010
Fig. 8. Steady-state output waveform in the step-up mode with Iload = 7.5 mA. Fig. 7. Vhigh -selection circuit.
Vcap passes the threshold voltage of the followed inverter, the gradually increasing Vcap is passed to be the reference voltage of the error amplifier. Since the output voltage also starts from zero, the output of the error amplifier would not immediately saturate, and the inrush current is limited. After Vcap gets larger than the threshold voltage of the inverter, the bandgap voltage Vbg is chosen instead, and the converter comes to work normally. The soft-start operational time could be controlled by adjusting the value of the off-chip capacitor Cs. D. Clock Selector There are two tasks for the clock selector. First, it determines the operational mode of the converter, either the step-up or the step-down mode, by comparing the divided voltage of VIN to the bandgap voltage Vbg . The corresponding timing sequences of the power switches are then generated, according to the output of the comparator. To work for a wide input voltage range, the comparator adopts the rail-to-rail input architecture. Moreover, since VIN may be higher or lower than VOUT in this chip, it is important to make sure that n-wells are connected to the highest voltage of the chip. Therefore, the second function of the clock selector is to choose the higher voltage Vhigh from VIN and VOUT , and Vhigh is also used to power up the drivers of the power switches. Fig. 7 shows the circuit to choose Vhigh . Notably, to completely turn off either M1 or M2 , level shifting circuits are required to boost the gate-driving signals of M1 and M2 . III. M EASURED R ESULTS The presented converter is meant for powering up lower power bio-electronics; thus, it was designed to provide at least a 7.5-mA load current in all conditions. In addition, both the flying and load capacitances are chosen to 1 μF in this work. Fig. 8 shows the steady-state output waveform with a 7.5-mA load current in the step-up mode. The output ripple is around 40 mV. Fig. 9 shows the transient response of the output voltage in the step-down mode, whereas the load current Iload changes from 7.5 to 0.4 mA. The settling time is around 6.3 ms with an overshoot of 170 mV. Fig. 10 plots the measured output voltage versus the load current. When the input voltage is 5 V, the maximal load current
Fig. 9. Transient response of the output voltage in the step-down mode with Iload = 7.5 mA → 0.4 mA.
Fig. 10.
Measured output voltage at different load currents.
is 16.8 mA. When the input voltage becomes 2.5 V, the maximal load current goes to 8.3 mA. Notably, its load regulation is excellent for the SC-type dc–dc converters. Fig. 11 plots the power efficiency versus the input voltage VIN , where the dotted line is the ideal efficiency of this architecture [3], [6], [8], and the solid line is the measured efficiency. The measured efficiency values are very close to its theoretical values. It means that the built-in compensator and control circuits consume very little power. Fig. 12 shows the photograph of the whole chip, and Table I summarizes the measured performances of the presented converter.
WEI et al.: INTEGRATED STEP-UP/STEP-DOWN DC–DC CONVERTER IMPLEMENTED WITH SC CIRCUITS
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signal 2P4M polycide 3.3/5 V process. The presented converter has a wide input range, i.e., 2.4–5 V, which is important for battery-powered devices. Take lithium ion cells, whose output voltage range is 2.5–4.2 V, as an example. Its battery life is estimated to extend approximately 15%–20% by using our proposed converter, as compared with that of using a step-down only converter. ACKNOWLEDGMENT The chip fabrication was supported by National Chip Implementation Center (CIC), National Applied Research Laboratories, Taiwan. Fig. 11. Plot of efficiency versus input voltage.
R EFERENCES
Fig. 12. Chip photograph. TABLE I SUMMARY OF MEASURED PERFORMANCES
IV. D ISCUSSION AND C ONCLUSION From Fig. 11, the measured efficiency was only around 40% at VIN = 4.2 V, just before switching from the step-up mode to the step-down mode. This minimal efficiency actually can be improved if the mode-switching voltage gets lower, which can be achieved by increasing the power switch size to reduce their ON -resistance. In fact, it is a tradeoff between efficiency and area and is a topic for future improvement. An integrated step-up/step-down dc–dc converter for batterypowered bio-electronics is proposed. Both the power stage and the PI compensator were implemented by using the SC technique. The chip was implemented by a 0.35-μm CMOS mixed-
[1] A. Ioinovici, “Switched-capacitor power electronics circuits,” IEEE Circuits Syst. Mag., vol. 1, no. 3, pp. 37–42, Jul. 2001. [2] S. V. Cheong, S. H. Chung, and A. Ioinovici, “Inductorless DC-to-DC converter with high power density,” IEEE Trans. Ind. Electron., vol. 41, no. 2, pp. 208–215, Apr. 1994. [3] S. H. Chung, S. Y. Hui, and S. C. Tang, “Development of a multistage current-controlled switched-capacitor step-down DC/DC converter with continuous input current,” IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 47, no. 7, pp. 1017–1025, Jul. 2000. [4] O. C. Mak, Y. C. Wong, and A. Ioinovici, “Step-up DC power supply based on a switched-capacitor circuit,” IEEE Trans. Ind. Electron., vol. 42, no. 1, pp. 90–97, Feb. 1995. [5] H. Chung, B. O, and A. Ioinovici, “Switched-capacitor-based DC-to-DC converter with improved input current waveform,” in Proc. IEEE Int. Symp. Circuits Syst., 1996, pp. 541–544. [6] S. H. Chung, “Design and analysis of a switched-capacitor-based step-up DC/DC converter with continuous input current,” IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 46, no. 6, pp. 722–730, Jun. 1999. [7] B. Robert Gregoire, “A compact switched-capacitor regulated charge pump power supply,” IEEE J. Solid-State Circuits, vol. 41, no. 8, pp. 1944–1953, Aug. 2006. [8] C. L. Wei, L. Y. Wu, H. H. Yang, C. H. Tsai, B. D. Liu, and S. J. Chang, “A versatile step-up/step-down switched-capacitor-based DC–DC converter,” IEICE Trans. Electron., vol. E91-C, no. 5, pp. 809–812, 2008. [9] F. Zhang, L. Du, F. Z. Peng, and Z. Qian, “A new design method for high-power high-efficiency switched-capacitor DC–DC converters,” IEEE Trans. Power Electron., vol. 23, no. 2, pp. 832–840, Mar. 2008. [10] M. S. Makowski, “Voltage regulation in switched-capacitor converters— A problem revisited,” in Proc. 5th Eur. Space Power Conf., 1998, pp. 357–360. [11] S. C. Tan, M. Nur, S. Kiratipongvoo, S. Bronstein, Y. M. Lai, C. K. Tse, and A. Ioinovici, “Switched-capacitor converter configuration with low EMI emission obtained by interleaving and its large-signal modeling,” in Proc. ISCAS, 2009, pp. 1081–1084. [12] S. C. Tan, S. Bronstein, M. Nur, Y. M. Lai, A. Ioinovici, and C. K. Tse, “Variable structure modeling and design of switched-capacitor converters,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 56, no. 9, pp. 2132– 2142, Sep. 2009. [13] B. Axelrod, Y. Berkovich, and A. Ioinovici, “Switched-capacitor/ switched-inductor structures for getting transformerless hybrid DC–DC PWM converters,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 55, no. 2, pp. 687–696, Mar. 2008. [14] J. Chen and A. Ioinovici, “Switching-mode DC–DC converter with switched-capacitor-based resonant circuit,” IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 43, no. 11, pp. 933–938, Nov. 1996. [15] G. Y. Zhu and A. Ioinovici, “Steady-state characteristics of switchedcapacitor electronic converters,” J. Circuits Syst. Comput., vol. 7, no. 2, pp. 69–91, Jul. 1997. [16] B. Axelrod, Y. Berkovich, and A. Ioinovici, “Transformerless DC–DC converters with a very high DC line-to-load voltage ratio,” in Proc. ISCAS, 2003, pp. III-435–III-438. [17] C. L. Wei and H. H. Yang, “Analysis and design of a step-down switchedcapacitor-based converter for low-power application,” in Proc. ISCAS, 2010, pp. 3184–3187. [18] Y. W. Lu, G. Feng, and Y. F. Liu, “A large signal dynamic model for DC-to-DC converters with average current control,” in Proc. IEEE APEC, 2004, vol. 2, pp. 797–803.
813
An Integrated Step-Up/Step-Down DC–DC Converter Implemented With Switched-Capacitor Circuits Chia-Ling Wei, Member, IEEE, Chun-Hsien Wu, Lu-Yao Wu, and Ming-Hsien Shih
Abstract—An integrated step-up/step-down dc–dc converter for battery-powered bioelectronics is presented. Both its power stage and feedback compensator were implemented by using switchedcapacitor circuits. The proposed converter has a wide input range and achieves excellent load regulation. Index Terms—DC–DC power conversion, step-up/step-down, switched capacitor (SC).
I. I NTRODUCTION
M
ORE and more portable bioelectronic products have been introduced to the market recently, and most of them are supplied by batteries, such as cardiac pacemaker and capsule endoscopy. In other words, the service life of these products is determined by their battery life. Moreover, since the battery voltage would decrease with time, a dc–dc converter is typically required to provide a steady output voltage. Hence, a versatile step-up/step-down dc–dc converter is a good choice to extend the battery life and the service life of biomedical electronics. The versatile step-up/step-down dc–dc converters can be implemented by either switching regulator architecture or switched-capacitor (SC) circuits. The switching regulators can provide a high load current with excellent efficiency, but bulky transformers or inductors are required for energy transfer. On the other hand, the SC converters only use capacitors, rather than inductors, but their supplied power is typically less than that of the switching regulators. In fact, portable bio-electronics are typically low-power designs to prolong their service life, but they are very strict with their sizes. Therefore, the SC-based converter is a good choice for these products [1]–[17]. When SC converters were introduced a few decades ago, they had two main drawbacks. First, their voltage conversion ratio is predetermined by the circuit structure. If the input voltage varies, the output voltage changes as well. In other words, their line regulation is very poor. The second problem is the lack of feedback mechanism; thus, their load regulation is also poor. In the past few decades, different control schemes have been Manuscript received May 7, 2010; accepted June 21, 2010. Date of publication August 26, 2010; date of current version October 15, 2010. This work was supported by the National Science Council, Taiwan, under Grant NSC-98-2220-E-006-012. This paper was recommended by Associate Editor H. S.-H. Chung. The authors are with the Department of Electrical Engineering, National Cheng Kung University, Tainan 70101, Taiwan (e-mail: [email protected]. edu.tw). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TCSII.2010.2058594
Fig. 1. Step-up/step-down SC-based dc–dc converter.
proposed to solve these issues [2]–[7], and one of the best solutions is to use a current control scheme [3], [5]–[8]. Fig. 1 shows the adopted SC converter architecture of this work [8]. Moreover, the frequencies of most bio-related signals are very low, and fast transient responses rarely occur. Therefore, to reduce switching loss and also to avoid high-frequency noise, it is preferred to have a low switching frequency for the SC converters used in portable bio-electronics. It means that the bandwidth of the SC converter would be lower, and the poles/zeros of its feedback compensator would also be located at lower frequencies. Furthermore, a built-in compensator would be preferred, because it reduces both device size and cost. However, due to the limited chip area, it is actually difficult to design such a compensator. In this brief, it is proposed to implement the built-in compensator with SC technique. A kilohertz-order pole/zero can be easily realized by SC circuits with a low switching frequency. In addition, it is a trend to integrate microelectromechanical system (MEMS) biosensors with CMOS integrated circuits into a single chip by using CMOS/MEMS processes. Therefore, a MEMS-compatible 0.35-μm CMOS mixed-signal 2P4M polycide 3.3/5 V process is adopted in our design. In fact, it is more possible to achieve a lab-on-a-chip (LOC) by using a 0.35-μm CMOS process, as compared with old technologies. An integrated step-up/step-down SC-based dc–dc converter for bio-electronics is presented. Except for the two energytransferring capacitors, the other parts of the presented
1549-7747/$26.00 © 2010 IEEE
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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 57, NO. 10, OCTOBER 2010
Fig. 2. Block diagram of the integrated SC-based dc–dc converter.
converter, such as its power stage and compensator, were implemented and integrated into a single chip. The load regulation of the presented converter is excellent. Section II describes its block diagram, frequency response, and main circuits, whereas Section III shows the measured results. A short discussion and the conclusion are given in Section IV. II. B LOCK D IAGRAM AND M AIN C IRCUITS Fig. 2 shows the block diagram of the presented converter. The desired input voltage range is 2.5–5.0 V, and its output voltage is set to 3.6 V.
Fig. 3. Timing diagrams of the power switches in the (a) step-up and (b) stepdown modes.
A. SC-Based Power Stage The SC-based power stage is shown in Fig. 1, and it consists of one flying capacitor CM , one load capacitor CL , four power switches (S1 , S1a , S2 , and S2a ), and a voltage-controlled current source (VCCS), which is realized by a PMOS. The timing diagrams of the four switches for the step-up mode (VIN ≤ VOUT ) is shown in Fig. 3(a), whereas those for the step-down mode (VIN > VOUT ) is shown in Fig. 3(b). All clock signals are nonoverlapping, and their frequency is set to 100 kHz in our design [17]. To improve efficiency, switches S1 and S2a were implemented by using transmission gates to reduce their ON -resistance. The other two switches were realized by either NMOS or PMOS only, since they are always conducting to either ground or a high voltage. In the charging phase of the step-up mode, both S1 and S1a are turned on, and the capacitor CM is charged by the VCCS. At this time, the intermediate node voltage VX (see Fig. 1) is slightly lower than the input voltage VIN . In the discharging phase, both S2 and S2a are turned on almost simultaneously, and CM is flipped to be connected in series with VIN to serve the load and CL . During this phase, VX is slightly higher than the output voltage VOUT . Notably, when switching from the discharging phase back to the charging phase again, VX may be temporarily higher than VIN , which would reverse the charging current. To solve this issue, S1a is designed to be turned on slightly earlier than S1 , and S2a is turned on slightly earlier than S2 . In the step-down mode, switch S1a is always turned on, whereas switch S2a is always turned off. During the charging phase, switch S1 is turned on, and CM is charged by the VCCS. During the discharging phase, switch S2 is turned on, and the load and CL are served by CM .
Fig. 4. Equivalent circuits of the SC-based power stage in the (a) step-up and (b) step-down modes.
B. Feedback Circuit To design the feedback circuits, the control-to-output transfer function of the converter is required. The equivalent circuit of the SC-based power stage can be obtained by using the average current method [8], [17], [18]. Fig. 4(a) and (b) shows the equivalent circuit in the step-up and step-down modes, respectively, where r1(AVG) and r2(AVG) is the average resistance
WEI et al.: INTEGRATED STEP-UP/STEP-DOWN DC–DC CONVERTER IMPLEMENTED WITH SC CIRCUITS
Fig. 5.
815
Fig. 6. Soft-start circuit.
PI compensator circuit.
where of switches S1 and S2 over a complete cycle, respectively. Moreover, since the duty ratio of switches S1a and S2a is almost the same as that of S1 and S2 , respectively, their average resistances are assumed to be the same as those of S1 and S2 . Their values can be calculated by r1(AVG) = r1a(AVG) −1 1 ron = 0 · (1 − D) + D = ron D r2(AVG) = r2a(AVG) −1 1 ron = 0 · (D) + (1 − D) = ron 1−D
(1a)
(1b)
(2a)
where Vc is the control voltage of the VCCS, and gm is the transconductance of the VCCS. Similarly, the control-to-output transfer function of the step-down mode is 1 VOUT 2 (1 + sron CL )RL gm . (2b) = 2 Vc 4ron RL CL s2 + (4ron CL + 2RL CL )s + 1
Notably, since S1a is always turned on in the step-down mode, the average resistance of S1a is ron , which is different from r1(AVG) . From (2a) and (2b), both of them have two poles and one zero, and their Bode plots are also similar. Typically, the first pole is located at a very low frequency, and the zero and the second pole are located at relatively high frequencies. Hence, a proportional–integral (PI) compensator is used in this work. Fig. 5 shows the circuit of the PI compensator. In our design, C1 is 50 fF, C2 is 10 pF, Req1 is 2.5 MΩ, and Req2 is 25 MΩ. To save chip area of the built-in compensator, the resistors are actually implemented by using SC circuits. The transfer function of the PI compensator can be derived as HPI (s) =
(1 + s/ω1 ) s/ω2 (1 + s/ω3 )
(3)
1
=
fR CR2 C2
Req2 C2 fR CR1 1 = ω2 = Req1 (C1 + C2 ) (C1 + C2 ) ω3 =
where ron is the ON-resistance of the switches, and D is the duty ratio of S1 [8], [17]. By letting D = 0.5 and CM = CL , the control-to-output transfer function of the converter working in the step-up mode can be derived as 1 VOUT 2 (1 + sron CL )RL gm = 2 Vc 3ron RL CL s2 + (3ron CL + 2RL CL )s + 1
ω1 =
C1 + C2 fR CR2 (C1 + C2 ) = Req2 C1 C2 C1 C2
and fR is the switching frequency of the PI compensator. In our design, fR is set to 400 kHz, four times faster than the switching frequency of the SC-based power stage. The PI compensator contributes one dc pole, one zero, and one high-frequency pole. The dc pole increases the dc loop gain to reduce the steady-state error. The zero is used to cancel the effect of the first pole in the control-to-output transfer function to achieve an adequate phase margin. In addition, the high-frequency pole is used to attenuate the switching noise. In fact, there is one more important advantage by using the SC-implemented resistances. The pole/zero locations of the PI compensator are determined by the RC products. If true resistors are used, it is difficult to precisely control the pole/zero locations due to the large variation in the chip resistance values. On the other hand, when the resistors are implemented by the SC circuits, the pole/zero locations are actually determined by the ratios of capacitors, which is much easier to be well controlled in chip fabrication. Moreover, by alternating the clock sequences of Req1 , it becomes a negative resistance. Therefore, the dc gain of the PI compensator is positive, although the inverting operational amplifier (op amp) configuration is used. A two-stage op amp is adopted as the error amplifier in the PI compensator, because it has a wide output voltage range, which determines the available charging current range of the VCCS. The unity-gain bandwidth of the op amp is designed to be at least ten times higher than its switching frequency fR . C. Soft Start Because the output voltage increases from zero at start-up, a large inrush current will flow through the VCCS if there is not any protection step taken. To prevent this inrush current from damaging the VCCS, it is necessary to implement a soft-start scheme. Fig. 6 shows the soft-start circuit, where the shown op amp is the error amplifier of the PI compensator. A constant current source is used to charge the capacitor Cs at start-up; thus, the capacitor voltage Vcap will increase with time. Before
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Fig. 8. Steady-state output waveform in the step-up mode with Iload = 7.5 mA. Fig. 7. Vhigh -selection circuit.
Vcap passes the threshold voltage of the followed inverter, the gradually increasing Vcap is passed to be the reference voltage of the error amplifier. Since the output voltage also starts from zero, the output of the error amplifier would not immediately saturate, and the inrush current is limited. After Vcap gets larger than the threshold voltage of the inverter, the bandgap voltage Vbg is chosen instead, and the converter comes to work normally. The soft-start operational time could be controlled by adjusting the value of the off-chip capacitor Cs. D. Clock Selector There are two tasks for the clock selector. First, it determines the operational mode of the converter, either the step-up or the step-down mode, by comparing the divided voltage of VIN to the bandgap voltage Vbg . The corresponding timing sequences of the power switches are then generated, according to the output of the comparator. To work for a wide input voltage range, the comparator adopts the rail-to-rail input architecture. Moreover, since VIN may be higher or lower than VOUT in this chip, it is important to make sure that n-wells are connected to the highest voltage of the chip. Therefore, the second function of the clock selector is to choose the higher voltage Vhigh from VIN and VOUT , and Vhigh is also used to power up the drivers of the power switches. Fig. 7 shows the circuit to choose Vhigh . Notably, to completely turn off either M1 or M2 , level shifting circuits are required to boost the gate-driving signals of M1 and M2 . III. M EASURED R ESULTS The presented converter is meant for powering up lower power bio-electronics; thus, it was designed to provide at least a 7.5-mA load current in all conditions. In addition, both the flying and load capacitances are chosen to 1 μF in this work. Fig. 8 shows the steady-state output waveform with a 7.5-mA load current in the step-up mode. The output ripple is around 40 mV. Fig. 9 shows the transient response of the output voltage in the step-down mode, whereas the load current Iload changes from 7.5 to 0.4 mA. The settling time is around 6.3 ms with an overshoot of 170 mV. Fig. 10 plots the measured output voltage versus the load current. When the input voltage is 5 V, the maximal load current
Fig. 9. Transient response of the output voltage in the step-down mode with Iload = 7.5 mA → 0.4 mA.
Fig. 10.
Measured output voltage at different load currents.
is 16.8 mA. When the input voltage becomes 2.5 V, the maximal load current goes to 8.3 mA. Notably, its load regulation is excellent for the SC-type dc–dc converters. Fig. 11 plots the power efficiency versus the input voltage VIN , where the dotted line is the ideal efficiency of this architecture [3], [6], [8], and the solid line is the measured efficiency. The measured efficiency values are very close to its theoretical values. It means that the built-in compensator and control circuits consume very little power. Fig. 12 shows the photograph of the whole chip, and Table I summarizes the measured performances of the presented converter.
WEI et al.: INTEGRATED STEP-UP/STEP-DOWN DC–DC CONVERTER IMPLEMENTED WITH SC CIRCUITS
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signal 2P4M polycide 3.3/5 V process. The presented converter has a wide input range, i.e., 2.4–5 V, which is important for battery-powered devices. Take lithium ion cells, whose output voltage range is 2.5–4.2 V, as an example. Its battery life is estimated to extend approximately 15%–20% by using our proposed converter, as compared with that of using a step-down only converter. ACKNOWLEDGMENT The chip fabrication was supported by National Chip Implementation Center (CIC), National Applied Research Laboratories, Taiwan. Fig. 11. Plot of efficiency versus input voltage.
R EFERENCES
Fig. 12. Chip photograph. TABLE I SUMMARY OF MEASURED PERFORMANCES
IV. D ISCUSSION AND C ONCLUSION From Fig. 11, the measured efficiency was only around 40% at VIN = 4.2 V, just before switching from the step-up mode to the step-down mode. This minimal efficiency actually can be improved if the mode-switching voltage gets lower, which can be achieved by increasing the power switch size to reduce their ON -resistance. In fact, it is a tradeoff between efficiency and area and is a topic for future improvement. An integrated step-up/step-down dc–dc converter for batterypowered bio-electronics is proposed. Both the power stage and the PI compensator were implemented by using the SC technique. The chip was implemented by a 0.35-μm CMOS mixed-
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