Analysis and Design of Fanout-Free Networks of ... - Semantic Scholar
Analysis and Design of Fanout-Free Networks of Positive Symmetric Gates JON
T. BUTLER
Northwestern Umverstty, Evanston, llhnms ABSTRACT Art algorithm is presented for assigning functmns to gates in a fanout-free network so that a gwen function is reahzed Since the method is tabular, ~t IS easily programmed As long as the gates used are symmetric and positive the synthesis technique can be tadored to the particular set of gates available, for example, AND, OR, and majority gates It is shown that the functions realized by such networks are a proper subset of the set of unate functions but not of threshold functions Also, ~t is shown that the fanout-free functions that are threshold realizable are exactly those reahzed by the cascade, a special case of the fanout-free network KEY WORDS AND PHRASES swItchmg funcuons, fanout, fanout-free functions, fanout-free networks, unate funcUons, threshold funcUons, posmve symmetnc funcUons, Chow parameters CR CATEGORIES. 6 1
1. Introduction
An important characteristic of switching circuits is fanout. In particular, a circuit where at least one network input or one gate output connects to more than one gate input is said to possess fanout; otherwise, it is fanout-free. Figure 1 shows three fanout-free networks. Note that for each input x,, there is a unique path to the output. Because of this, it is very easy to fred an assignment of values to other network inputs so that the output is sensitized to x,; that is, the output varies when x, varies. Such assignments constitute tests for stuckat faults (Kohavi [101). Unique paths also imply the absence of both static and dynamic hazards. Because it is difficult and expenswe to replicate bubbles in magnetic bubble logic, fanout-free circuits are preferred over clrcmts wtth fanout (Minmck [13]). In view of these advantages, the fanout-free network is an important area of research. For example, Hayes [6] has shown that fanout-free functions realized by networks of AND's, OR's, and inverters can be identified by the use of the adjacency relation. Kodandapani and Seth [9] extended this concept to circuits with AND's, OR's, exclusive OR's, majority gates, and mverters. Although all switching functions can be realized by a network of AND's, OR's, and inverters, not all switching functions can be reahzed by a fanout-free network of such gates. With respect to just fanout-free circmts, there is a significant advantage to making the gate set as large as possible (Bender and Butler [2]). Thus, a natural extension of present studies is to consider more general gate sets. In particular it is shown here that positive symmetric gates (such as the AND, OR, and majority gate) have properties that allow an easily applied tabular synthesis algorithm. More general gates, on the other hand, do not have these properties. The format of the paper is as follows. General permission to make fair use in teaching or research of all or part of this material is granted to |ndlvldual readers and to nonprofit hbranes acting for them provided that ACM's copyright notice is given and that reference is made to the pubhcatlon, to its date of issue, and to the fact that reprinting privileges were granted by permission of the Association for Computing Machinery To otherwise reprint a figure, table, other substanual excerpt, or the entire work requires specific permission as does republication, or systematic or multiple reproduction This research was supported by the National Science Foundation under Grant MCS-7600326 Author's address Department of Electrical Engineering, Northwestern Umversity, Evanston, IL 60201 © 1978 A C M 0004-5411/78/0700-0481 $00 75 Journal of the Assocaatlonfor ComputingMachinery,Vol 25, No 3, July 1978,pp 481-498
482
JON T BUTLER xI
x 2
x3 x4
x5 x6
(a)
x1
x2 x3 x4
x5 x6
(b)
xI
x2 x3
x4 x5 x6 (¢)
FIG 1
Examples of three fanout-fre¢ networks
Section 2 defines switching theory concepts that have a direct bearing on the subject. Of specific interest are positive, negative, unate, voting, threshold, cascade realizable, and fanout-free realizable switching functions. In Section 3 it m shown that a necessary and sufficient condition for a fanout-free function to be unate Is that it be reahzed by unate gates. Thus, part of the synthesis algorithm is a test for unateness. Section 4 m a description of the algorithm. It m shown that the Chow parameters of a funcuon and symmetry among variables can be used to identify inputs to specific gates. In Section 5 the relationship between fanout-free, unate, and threshold functions is shown, and in Section 6 possible extensions of this research are presented.
2. Definitions and Introductory Concepts L e t f ( X ) denote an n-vanable switching function, where X = {xl, x2 . . . . . xn}. Function
f(X) lmphes g(X), denotedf(X) ~ g(X), if for all assignments of values to xl, x2 ..... and Xn, g(X) = 1 wheneverf(X) = 1. For example, if fi(X)
= xlx2
(1)
Analysis and Design of Fanout-Free Networks of Posmve Symmetric Gates
483
and
J~(X) = xlx223,
(2)
thenj'~(X) ~ fi(X). Let f ( X l O --> x,) and f ( X I 1 ---> x3 denote the residue functions obtained from f ( X ) by setting x, = 0 and x, ffi 1, respectively. Thus, f i ( X I 0 ~ xl) ffi 0 and f2(X I 1 --.~ xl) = xl~a. This can be extended to more than one variable in a logical fashion; for example, ./~(XI 1 --, xl, 1 ~ x2, 0 ~ x3) = 1. f ( X ) is positive (monotone increasing) m x, i f f ( X I 1 ~ x,) ~ f ( X I 0 ~ x,). Simdarly, f ( X ) is negative (monotone decreasing) in x, i f f ( X I 1 ~ x,) ~ f ( X I 0 ~ xj. For example, f i ( X ) is positive in x~ and x2, while f i ( X ) is positive in x~ and x2 and negauve in x3. A function which is either positive or negatwe in x, is said to be unate in x,. 1 A function which is either positive, negative, or unate m all variables mssaid to be a positive, negative, or unate function, respectively. For example, fi(X) is both a positive and a unate function, while/~(X) is simply unate. Consider the Shannon decomposition o f f ( X ) about x, ~ X,
f ( X ) = f ( X l 0 ~ x,)~, + f ( X l 1 ~ x,)x,. I f f ( X ) is positwe (negative) in x,, t h e n f ( X I 0 ---> x,) ~ f ( X [ f ( X I 0 - - > x,)), a n d f ( X ) has the alternate form
f ( X ) = f ( X I 0 ~ x,) + f ( X I 1 ~ x,)x,,
1 ---> x,) ( f ( X I 1 ---> x,) ~-0
( f ( X ) = f ( X l O ~ x,)Sc, + f ( X I 1 ~ x,)).
Note that for any assignment of values to X - {x,}, i f f ( X ) is positive in x,, either ( l ) f ( X ) is independent of x, or (2)f(X) = x,; f ( X ) is never ~,. Furthermore, the converse is also true. f ( X ) is a threshold function if there exists a set of real-valued weights {w~, w2. . . . . wn} and a real-valued threshold T, such that f ( X ) = 1 if and only if W~Xl + w2x2 + .. • + WnXn --> T, where the logic values of x,, 0 and 1, are viewed as integer values, 0 and 1, respectively; where + denotes ordinary addition; and where concatenation represents ordinary multiplication. Let (w~, w2, ... , wn; T) denote the weight-threshold vector of f ( X ) . For example, fx(X) andf2(X) are threshold functions with weight-threshold vectors (1, 1, 0; 2) and (1, 1, - 1 ; 2), respectively. The set of threshold functions has been shown to be a subset of the set of unate functions. That it is a proper subset follows from the fact that the unate function, x~x2 + x3x4, is not threshold realizable. Of particular interest in this paper is the voting funcUon. A voting functionfin(X) is 1 if and only if t 9r more of its n variables are 1. Thus, fin(X) is a threshold function with weight-threshold vector (1, 1, ..., 1;t). For example, the two-input A N D and OR functions correspond to fi2(xl, x2) and fi2(x~, x2), respectively, while the three-input majority function, MAJ(xl, x2, x3), corresponds t o i l 3(x~, x2, x3). f ( X ) is (totally) symmetric if all permutations of variables leave the function mvariant. For example,fi(X) is symmetric, for X = {x~, x2}, whilefi(X) andf2(X) are not symmetric, for X = {Xl, x2, x3}. The gates used in the fanout-free networks considered in this paper are both positive and symmetric. The following result shows that these are also voting functions. LEMMA 1 [5, p. 180]. f ( X ) is a positive symmetrw functwn if and only if it is a voting funclton.
Figure 2(a) shows an n-input gate that realizesfi n(X). Standard symbols will be used for the n-input A N D gate (Figure 2(b)), the n-input OR gate (Figure 2(c)), and the three-input majority gate (Figure 2(d)). AND, OR, and majority gates are commonly available, while of the gates on three or more variables, the voting functions are among the easiest to implement. Let G denote the set of gates used to implement a fanout-free funcuon. It will be 1 A f u n c U o n w h i c h IS b o t h p o s m v e a n d n e g a U v e m
x, ts i n d e p e n d e n t
o f x,
484
JON T BUTLER
x
x2
~
xl x2
•
xn x
Xn"-~....,,/
x3
n
(a)
(b) F{o 2
(e)
(d)
Voting, AND, OR, and majority representatmns
assumed that all such sets include the inverter. It follows, therefore, that iffi n(X) is in G, thenfn-t+l n(X) is also effectively in G. Since fn-t+l n(X) =ftn(Xl~, ~ x,, for 1 ~ i _< n),
(3)
fi-t+t n(X) can be implemented by connecting inverters to the output and inputs of a gate which reahzesfin. In this paper it will be assumed that iffi~(X) ts realized by a gate in G, so also isfn-t+~ n(X). Note that (3) is De Morgan's theorem if t = 1 or n. If the two-input A N D or OR gate is in G, then G, in effect, contains the n-input A N D or OR gate, respectively, for n. This follows because the latter gates can be implemented by a fanout-free network of two-input gates. It will be convenient to assume that an minput A N D (OR) gate output never drives an n-input A N D (OR) gate input, since the combination is equivalent to an m + n - 1 input A N D (OR) gate. As in [9], G will be denoted by a set of letters specifying the gates. For example, A O M N refers to the set of two-input AND's, OR's, three-input majority gates, and inverters. Ft~ is a gate realizing fi n(X). Thus, F24Fa 4Fa 5N denotes a gate set consisting of voting gates f24(X),fi 4(X), a n d ~ 5(X) and inverters. Note M = F~ a and F35 have no counterpart since adding mverters to the inputs and output of these gates leaves their function unchanged. It can be seen that, in general, when n is odd, Frn/21,~has no counterpart. In many design applications the complements of network inputs are also available (for example, as the outputs of flip-flops). Because of this, it is useful to consider networks where inverters occur only on primary inputs. A fanout-free network of positive symmetric gates and inverters is canonical if all inverters appear on network inputs only. 2 LEMMA 2. Let G be a gate set consisting of positive symmetric gates and an inverter. For each fanout-free network N on G, there extsts a canonical network Nc on G which reahzes the same function. PROOF. If N is already canonical, N = Nc. Otherwise, N contains at least one inverter which connects to the output of some gate Ft n. From (3), the function realized by this combination is also realized by a gate F~-t÷t ~ with inverters on all inputs. These, in turn, connect to primary inputs or gate outputs. In the latter case a similar sttuation exists and the inverters can be "pushed back" toward the network inputs again. In this way internal inverters can be eliminated without changing the network's function. Q.E.D Lernma 2 shows that when complements of pnmary inputs are available, any fanoutfree network can be converted to an reverter-free circuit. 3. Fanout-Free Networks of General Gates
Although many switching circuit designs use unate gates, such as inverters, OR's, AND's, and threshold elements, it ts of interest to consider fanout-free designs composed of more general gates. The main result of this section is a proof that the existence of at least one nonunate gate in a fanout-free realization o f f ( X ) imphes f ( X ) is nonunate, and if only unate gates are used, f ( X ) is unate. An analysis tool of significant application is the simple disjunctive decomposition (Curtis [31). In particular, f ( X ) has a simple disjunctive decomposition (SDD) if and only if 2 This excludes any mverters used to Implement fn-t+l n(X) fromfi ~(X) These are assumed to be part of the gate tmplementatmn, not part of the network.
Analysis and Design o f Fanout-Free Networks o f Positive Symmetric Gates
(
485
f(X)= g(h,Z)
Z L FiG 3. Network rcahzmgf(X) = g(h(Y), Z)
f ( X ) = g(h(Y), Z),
(4)
where X = Y O Z a n d Y tq Z = O ( 0 = null set). A n S D D is nontrivial if [ YI > 1 a n d I Z [ _> 1. Example, f2(X) = xlx2Yc3 has a n o n t n v i a l S D D of the form f2(X) = g2(h2(xl, x2), x3),
(5)
where g2 = h2~3 a n d h2 = xlx2. F u n c t i o n s with a n S D D of the form (4) can be realized by the network shown in Figure 3. F r o m a n information theoretic point of view, the information about the value of Y required to determine the value o f f ( X ) can be encoded in a single bit h. T h u s , f (X) "needs to know" only that a particular assignment of values to Y, A r, falls into one of two categories represented by h = 0 a n d h = I. As a n example, let X = {Xm, x2, x3}, Y = {xl, x2}, a n d Z = (xs}. j~(X) = x~x2~s has a n S D D o f the form shown in (5) because, with respect to x, a n d x2, f ( X ) needs to know that either I. xl = x2 = l (in which c a s e f ( X ) = Yc3),or 2. one or both of Xl a n d x2 are 0 ( f ( X ) = 0 regardless of x3). O n the other hand, i f f ( X ) = MAJ(Xl, x2, xa), assignments o f values to Y must fall into three categories:
I. Xl = x2 = l ( f ( X ) = l regardless o f xa), 2. exactly one of xl a n d xz is 1 ( f ( X ) = x3), or 3. xl = x2 = 0 ( f ( X ) = 0 regardless of x3). Since at least two bits are required to encode this information, it follows that the majority function has n o nontrivial SDD. The significance of S D D ' s with respect to fanout-free functions is shown by the following result. THEOREM 1. Let f ( X ) be a function reahzed by a fanout-free network o f two or more gates. Then, f ( X ) has at least one nontrivial S D D o f the form f ( X ) = g(h(Y), Z), where g and h are fanout-free functions. Note that T h e o r e m 1 is not true, in general, for fanout-free functions of one gate. F o r example, the majority function has no SDD, a n d so a fanout-free network composed o f just a single such gate has no SDD. 3 T h e o r e m l provides the background for the m a i n result of this section; that is, a fanoutfree function f ( X ) is unate if a n d only if it can be realized by unate gates exclusively. Intuitively, the proof ts based o n the fact that w h e n the o u t p u t f i s sensitized to a n input x, by some choice o f values for X - (x,}, e l t h e r f = x, o r f = ~,. Each gate between x, a n d f acts as a n inverter or a n identity gate. If there are a n odd n u m b e r of inverters, f = .L; otherwise f = x,. I f a unate gate acts as an inverter for some assignment o f values to its other inputs, it can never act as a n identity gate a n d vice versa. Thus, if the path from x, t o f i s through unate gates only, e i t h e r f = x, o r f = Yc,, but not both. Thus, f ( X ) is u n a t e a In fact, it Is easy to show that the only voting functions with SDD's are the AND and OR of n variables, n>_2
486
J O N T. B U T L E R
in x,. A gate nonunate in x,, on the other hand, can act as both an inverter and identity gate. If such a gate appears in the path between x, andfi there are assignments to network inputs such that f = x, and f = ~¢,. Thus, f ( X ) is not unate in x,. THEOREM 2. A fanout-free function f ( X ) is unate if and only if it is reahzable by a
fanout-free network composed entirely of unate gates. Theorem 2 extends Hayes' [6] result for fanout-free networks o f AND's, OR's, and inverters (AON) and Muldaopadhyay's [14] result for AON cascades. It Is an immediate result o f Theorem 2 that nonunate functions are not realizable as networks of inverters and positive symmetric gates. An appropriate first step in the synthesis algorithm for fanout-free networks of such gates, therefore, is to test for unateness. An immediate corollary to Theorem 2 is: COROLLARY 1. A fanout-free function ts a positive function if it ,s realized by a fanout-
free network of positive gates. The converse of Corollary 1 is not true. For example, consider the trivial network in which the primary inputs Xl and x2 are each apphed to inverters with outputs which are in turn applied to a gate which realizes M~, a negative function. The function reahzed is ab, a positive function. Thus, a fanout-free network of negative gates can realize a positive function.
4. Synthesis of Canonical Fanout-Free Networks of Positive Symmetric Gates and lnverters In order to determine the assignment of functions to gates in a fanout-free czrcuit so that a given function f ( X ) is realized, it is necessary to identify which network inputs drive certain gates. In the algorithms of Hayes [6] and of Kodandapani and Seth [9], all pairs of variables are tested to determine if a relatton, called adjacency, exists. Since adjacency is an equivalence relation, it divides the set of variables into equivalence classes. These classes are then used to determine variables which are applied to the same gate. In this section a tabular method which identifies equivalence classes is presented. It is based on the Chow parameter [11, pp. 417--422] characterization of variables. Since the algorithm is tabular, it is very easily programmed. Originally studied by Golomb [41 to classify switching funcUon symmetry types, Chow parameters have found extensive applicauon in the analysis of threshold functions [11] and in the synthesis of A O N cascades [ 1]. Although a number of different definitions exist, it will be convement to use the following one. Let f ( X ) be a swttching function on n variables. The 0th order Chow parameter of f(X), Co, is 2n
Co = Y f(XIA, ~ X), ~0
where A, is an assignment of values to X whose binary equivalent is i andf(X[A, ~ X) is the value o f f ( X ) for that assignment. For example, Ao corresponds to all O's, A1 corresponds to all O's except xn = 1, etc. The summation sign denotes integer addition, where f(X[ A, --* X) = 0(1) is taken as the integer 0(1). Co is just the number of l's m the truth table o f f ( X ) . For example, forf3(X) shown in Table I, Co = 6. TABLE
I. A N EXAMPLE TO ILLUSTRATE CHOW PARAMETER CALCULATION
x,
x2
x3
x,
f~tx,, x2, x3, x,)
0 0 0 0 0 0 0 0
0 0 0 0 I I 1 1
0 0 1 1 0 0 1 1
0 ! 0 I 0 ! 0 1
0 0 0 ! 0 0 0 1
x,
x2
x~
x,
f~fx,, x2, x~, x,)
0 0 0 0 ! 1 1 !
0 0 1 1 0 0 1 1
0 I 0 1 0 1 0 1
0 0 0 ! 0 1 1 1
Analysis and Design of Fanout-Free Networks of Positive Symmetric Gates
4 87
2® x3
~
x4 FIG 4
1
f3 (xl'x2'x3'x4)
I
A fanout-free network which reahzesf3(xl, x2, x3, x4)
The first-order Chow parameters Cj o f f ( X ) for 1 _<j _< n are defined as follows. 2n
cj = ~ ~f(X).x+lA,~ X). tzO
Cj is the number of times 1 appears m both the xj column and t h e f c o l u m n o f the truth table f o r f ( X ) F o r example, f o r f l ( X ) shown m Table I, C1 = 4, Ce -- 4, C3 -- 5, C4 = 5. Chow parameters on a network diagram will be denoted by circles. F o r example, a fanoutfree network to realize the function of Table I is shown in Figure 4. Note that inputs which are symmetric, such as xl and x2, have the same Chow parameter value. In addition it is interesting to note that the smallest Chow parameters are those associated with inputs to a gate which has no inputs from other gates. One then wonders if this is a general characteristic. As a step toward the answer of this question, consider the following. THEOREM
3.
fin(X) = f i n - 2 ( X - (x,, xj}) + (x, + xj)fi-~ n-2(X - (x,, x~}) + (x,xj)fi-2n-2(X- {x,, xj})
for
IX[ _> 2.
(6)
PROOF. The hypothesis follows directly from the observation that fin(X) = 1 if and only if one o f the following three conditions holds. 1. at least t of the variables in X - {x, xj} are 1, 2. t - 1 of X - {x,, xj} are 1 and either x, or xj (or both) are 1, or 3. t - 2 of X - {x,, xj} are 1 and both x, and xj are 1. 4 Q.E.D. Theorem 3 shows that a positwe symmetric function can be decomposed into the sumof-products of lower order positive symmetric functions, since both x, + xj and x,xj are positive symmetric. Thus, wRh respect to assignments of values to X - {x,, xj}, f i n ( X ) = 0, 1, x, + xj, or x,xj. In a fanout-free network, the network output can be sensitized to the output o f any gate G. F o r a fanout-free network o f positive gates, the path from G to the network output is inverter-free. Thts yields the following corollary. COROLLARY 2. Let f ( X ) be a function realized by a fanout-free network of posttive symmetrtc gates, and let x, and xj be inputs to the same gate. For any assignment of values to X - {x,, xj} etther
1. f ( X ) is independent of x, and xj, 2. f ( X ) = x, + xj, or 3. f ( X ) = x,x,. Consider a case where x, and xj are not applied to the same gate. Figure 5 shows a network in which x~ is applied to a gate G which is also driven by a network N1 of at least one gate. x,, in this case, denotes an input to N1. The relative value of C, and Cj, the Chow parameters of x, and xj, respectively, can be calculated by observing that each o f the 2 Ivl assignments to V produces a (possibly 0) contribution to C, and Cj. F r o m Corollary 2, assignments of values to V c a u s e f ( X ) to respond in different ways to a and xj. Consider each in turn. 4 W h e n t ffi n or n - !, voting functions to the right o f the e q u a h t y sign ta (6) h a v e a threshold larger than the n u m b e r o f inputs If it ts assumed t h a t f i n ( X ) = 0 for t > n, then (6) wall be correct for these cases.
488
JON T BUTLER
xjQ FiG 5
f(x)
An example for the calculation of relauve Chow parameters
1. Assignments to V s u c h t h a t f ( X ) i s i n d e p e n d e n t o f a a n d x / S m c e f ( X ) i s i n d e p e n d e n t of a, it is also independent o f x, (and U). Thus, for all 2 T M assignments of values to U O {x, xj}, f ( X ) = 0 or 1. It follows, therefore, that the contribution o f these assignments to C and Cj is the same. 2. Assignments to Vsuch t h a t f ( X ) = a + x / F o r this c a s e , f ( X ) = 1 when a = 1. Thus, all assignments to U O {x,, xj} for which xj = 1 contribute 1 to C2. There are 2 T M such assignments. However, the contribution to C, can be at most 2 IUl+l, and this occurs only when x, = 1 implies a = 1, or stated algebraically, when a = g(U) + x~. 3. Assignments to Vsuch t h a t f ( X ) = a x / F o r this c a s e , f (X) = 1 when a = x = 1. The contribution to Cj is Co o f N~, the number o f assignments to U U {x,} which cause a to be 1. However, the contribution to C, can be at most Co of N1. This occurs only when a = 1 implies x, = 1 or a = g(U)x,. If G realizesflm, the O R function, then no assignment to V exists such t h a t f ( X ) = axe. Thus, only cases 1 and 2 occur. Case 1 corresponds to the same contnbutton to C, and Cj always, while for case 2, the contribuUons are identical only when a = g(U) + x,. But the latter is impossible; otherwise x, would have been applied to G not N~. Thus, C, < C~. Similarly, if G realizesf, n, the A N D funcUon, only cases 1 and 2 occur, and it follows in like fashion that C, < Cj. F o r all other choices for functions of G, cases 1, 2, and 3 occur, and again C, < Cj. This proves the following. THEOREM 4. The smallest first-order Chow parameters in a fanout-free network of positive symmetric gates are associated with gates whose inputs are network inputs. Since the Chow parameters o f any funcUon are very easily calculated, Theorem 4 provides a simple way to identify gates at the primary input level. However, as is shown in Figure 6, this characterization is not complete. Here four inputs, x~, x2, x3, and x4, all have the same parameters, but are not all apphed to the same gate. However, this problem is alleviated by observing that xl and x2 are symmetric, x3 and x4 are symmetric, while no other pairs are symmetric. A generalization o f this observation is: THEOREM 5. Two inputs to a fanout-free network of positive symmetrw gates are symmetric if and only if they are applied to the same gate. The identification o f symmetric inputs can be accomplished easily in tabular form (Yau and Tang [17]). In partwular a symmetry test follows from: THEOREM 6 [17, p. 1611]. f ( X ) ts symmetric in x~ and x~ if and only if f ( X I l ~ x,, 0---~ xj) = f ( X I 0 - - , x,, 1 ~ xj).
(7)
Theorem 6 shows that to determine symmetry between variables x, and xj, it is necessary only to determine that residue f u n c t i o n f ( X I 1 ~ x,, 0 ~ x~) is 1 w h e n e v e r f ( X [ 0 ~ x,, 1 ~ x~) is 1 and vice versa. In the truth table f o r f ( X ) , this amounts to determining ff for every assignment Ap to X such that x, = 0 and xj = 1 (x, = 1 and x~ = 0) for w h i c h f ( X ) = 1, there is another assignment h q , identical to Ap except x, = 1 and xj = 0 (x, = 0 and xj = 1), for w h i c h f ( X ) = 1. Thus, a second step in the algorithm is to determine symmetry o f variables. The Chow parameter and symmetry tests alone are not sufficient to identify completely
Analysis and Design of Fanout-Free Networks of Positive Symmetric Gates
489
z2
x3
Flo 6 A fanout-free network m which the Chow parameters of the inputs of two gates are ~denttcal
FIG 7 Example of a threshold funetton which ts not fanout°freem posture symmetricgates
gates at the input level. For example, consider fi(X) reahzed by the threshold gate of Figure 7. xl, x2, and xa have the lowest Chow parameters and are symmetric, b u t f ( X ) has no nontrivial SDD, and so is not fanout-free in positive symmetric gates. L e t f ( X ) be a switching function symmetric in Y C X, where I Yt > 1. Let AY(j) be an assignment of values to Y c o n t a m i n g j l's, 0 _<j _< [ Y [. Then t h e j t h weight parameter of Y, wj(Y), is the number of assignments A to X where f(XIA ~ X) -- 1 in which the assignment to Y corresponds to AY(j). F o r example, c o n s i d e r f i ( X ) of Figure 7, and let Y = {xl, x2, x3}. wo(Y) is the number of assignments to X for w h i c h f ( X ) = 1 where no l's appear in x~, x2, or xa. Only x~, x~, xa, x4, x5 = 0, 0, 0, 1, i c a u s e s f ( X ) to be 1. Thus, wo(Y) = 1. Let A~Y = 001. Then, two assignments, xl, x2, xa, x4, x5 = 0, 0, 1, 0, 1 and 0, 0, 1, 1, 1, map to 1. Thus, Wl(Y) = 2. Similarly, w2(Y) = 3 and w3(Y) = 3. THEOREM 7. Let f ( X ) be a positive function symmetric in Y, Y C X and l Y[ > 1. f ( X )
has the SDD f ( X ) = g ( f t*lrl (Y), X -
Y),
(8)
if and only if there exist posmve integers m and m' such that wj(Y) = m for j < t and wj(Y) = m' for t _<j, where * indicates etther the complement or identity operation, and m#m'. PROOF (if) Ifwj(Y) = m f o r j < t and wj(Y) = m' for t _<j, t h e n f ( X ) must know the assignments o f values to Y to within two classes. Thus, with respect to Y, f ( X ) has an S D D o f the form
f ( X ) = g(h*(Y), X -
Y).
Thus, h(Y) =filvl(Y) follows from the fact that h(Y) must be 0(1) for assignments to Y which have i < t l's and 1(0) for assignments in which there are t _< i l's. (only if) Assume f ( X ) is gwen by (8). Since f ( X ) is positive for all assignments to X - Y either
1. f ( X ) = 0 regardless offitrt(Y ) (0 contribution to wj(Y) for a l l j ) , 2. f ( X ) = 1 regardless offilyt(Y ) (contribution the same to all wj(Y)), or 3. f ( X ) = f i l r l ( Y ) (0 contribution to wj(Y) w h e r e j < t and contribution o f I to all wj(Y) where t _<j). Thus, it follows that wj(Y) = m for j < t and wj(Y) = m' for t _<j, where m # m'. Q.E.D. Theorem 7 shows that an SDD revolving a positive symmetric function can be identified by counting entries in a truth table. In fact the test indicated by Theorem 7 can be the sole basis of a synthesis algonthm. It would, however, entail the examination of subsets o f the set X of which there are 2 Ixl. Since the Chow parameter and symmetry tests are simple, they provide an effective means of eliminating this search. An immediate corrollary to Theorem 7 is the following. COROLLARY 3. Let f ( X ) be a posittve function symmetric in Yi, Y2, .... and Yp; Y, C X
and [ Y,I > 1. f ( X ) has the complex dtsjunctive decomposition
490
JON T BUTLER
f(X)
= g(f~,r,,(Y~),f~lr~,(Y2) .... ,f~lr~,(Yp), X -
Y,-
Y2 . . . .
Yv)
i f and only i f there exist p pairs o f positive integers (mcn~), 1 _< i _< p, such that wj(Y,) = m, f o r j < t, and wl(Y,) ffi m; f o r t, _<j, where m, ~ m[. C o r o l l a r y 3 is used in the synthesis a l g o r i t h m d e s c r i b e d as follows. SYNTHESIS ALGORITHM. To determine iff (X) is fanout-free m a set G consisting of mverters and at least one type of posmve symmetric gate and to find a reallzaUon off(X) whenever it exists Inverters in the network synthesized appear on primary inputs (canomcal fanout-free realization) 1 Determine fff(X) is unate If ~t ~s, go to 2, otherwise go to 7 2 Convertf(X) to a posmve funcUon h(X) by complementing appropriate values m X If h(X) is not a posmve symmetric function, go to 3 If h(X) is a posmve symmetric functmn realized by a gate m G, go to 6 Otherwise, go to 7. 3 Compute the Chow parameters of h(X) 5 Let Y be the set of variables whose Chow parameters have the smallest magmtude If[ Y[ = 1 go to 7; otberwlse go to 4 4 Dlwde Y into disjoint subsets Yt, Y2, •, Yp such that for all x,, x~ ~ Yk, x, Js symmetric to x~, but to no other variable outside of Yk If I Y, {= 1 for any i, go to 7 Otherwise, go to 5. 5 For each Y, calculate w,(Y,), 0 _<j _< [Y,I If for each there exists a t, such that wj(Y,) = m forj < t, and ws( Y,) = m' for t, T.
Therefore, h ( Y ) is a threshold function with weight-threshold vector (wl, w2..... wp; T - W~). Let W2 be the weighted sum W2 = wlyl + w2y2 + "" + W,yplAY--~ Y,
corresponding to an assignment A Y to Y such t h a t f ( Y ) = 1. Thus, g(1, Z ) is 1 if and only if W2 + W]Zl + w~z2 + "
Since h(Y) is positive, h(Y) = 0 when y~ = y2 . . . . . if
.-1- WqZq ~ T.
(11)
yp = O. Thus, q(0, Z) is l if and only
0 "1- W~Zl '4" W2Z2 "[" "" "1- W ~ q --> T.
(12)
Analysis and Design of Fanout-Free Networks of Posittve Symmetric Gates
493
f7(X) = x l x 2 + x3x4 x3
FIG 9.
A fanout-free network of threshold gates which does not realize a threshold function
It follows from (11) and (12) that g(h,Z) is 1 if and only if
W2h + w~zl + w~z2 + "'" + W~Zq_> T, and so g(h, Z ) is threshold reahzable with weight-threshold vector (W2, w~, w~. . . . . w~; 7)). Q.E.D. Consider the case w h e r e f ( X ) is a function realized by a fanout-free network on some gate set G. If f (X) is realized by a single gate g, then f ( X ) is a threshold function if and only if g is a threshold gate. If f (X) is realized by a network with two or more gates, then Theorem 9 can be applied repeatedly to show that all gates must be threshold gates. Thus, THEOREM 10. I f f ( X ) is fanout-free and a threshold function, its fanout-free reahzation
contains only threshold gates. Unlike the result with respect to functions realized by fanout-free networks o f unate gates (Theorem 2), the converse of Theorem 10 is not true. F o r example, consider ~ ( X ) = xlx2 + xax4. Althoughf7(X) is realized by the fanout-free network o f threshold gates shown m Figure 9, it itself is not a threshold function. Note that Theorem l0 holds for the case in which gate set G contains both symmetnc and nonsymmetric gates. If G is restricted to contain only symmetric gates, then Theorem 10 implies that a fanout-free threshold function is always realized by a gate set consisting of positive or negative symmetric gates. This follows from the fact that a threshold function is also unate and that a unate function which is symmetric is either positive or negative in all variables. Consider now the problem of idenUfying fanout-free networks that realize threshold functions. A cascade is a fanout-free network m which all gates except one (at the input level) receive an input from exactly one other gate in the network. Figure 1(b) shows an example. Because of their simple topology, cascades are more easily analyzed, and so much o f the research on these networks precedes that o f the more general fanout-free network. F o r a survey o f papers on cascades before 1967, see Minnick [12]. Note that all one- and two-gate fanout-free networks are also cascades. Since a single positive symmetric function is a threshold functton, it follows that cascades of one and two positive symmetric gates realize threshold functions, exclusively. However, a more general statement can be made. THEOREM I I. Let f ( X ) be realizable by a canonical fanout-free network of positive
symmetric gates and mverters. Then f ( X ) is a threshold function if and only if it is realizable by a cascade. 6 PROOF. Although the proof is straightforward, it is long. See the Appendix. This is an unexpected result. It is convenient to represent the set of functions discussed in the diagram o f Figure 10. This shows the relationship between unate, threshold, and fanout-free functions. Note t h a t , ( X ) , the function used to show a unate function which is not fanout-free, is also not a threshold function. Also note t h a t , ( X ) , o f Figure 10, is a threshold function 6 Sasao and KmoshRa [16] have recently shown that lff(X) is realw.ableby an AON fanout-free network, then
f(X) is a threshold function if and only iff(X) is reahzable by an AON cascade
JON T BUTLER
494 Threshold functzons
f8(X ) = XlX 5 + x2x 5 + x3x 5 + + XlX3X 4 + x2x3x 4 + XlX3X 4 + x4x 5
Unate functzons
f6(X) =
x3x4 f7(X) = XlX ~
"..v.,~.~.~
•
a. b.
Fanout-Free Functions realzzed by symmetric gates and znverters all gates unate (top half clrcle) at least one nonunate gate (bottom half elrcle)
FIG 10 Relationships between unate functions, threshold funcuons, and fanout-free functions reahzed by symmetricgates and mverters (with weight-threshold vector (1, 1, 1, 3, 4; 4½)) that is also not fanout-free. This is because it has no SDD and is not itself symmetric. 6. Concluding Remarks
The synthesis technique described in this paper is basically a four-step process. 1. Determine whether the given function is unate. 2. Check which inputs drive gates at the input level (using Chow parameters). 3. Check for symmetry among these inputs. 4. Determine the gate functions. An interesting question concerns the extenmon of the synthesis techmque to more general networks. Unfortunately, some of the useful properties of fanout-free networks of positive symmetric gates and inverters do not carry over. For example, when nonunate gates are included in the gate set, the unateness test does not eliminate nonrealizable functions. Also, first-order Chow parameters have limited apphcation. For example, consider f9(X) = (xlx2) @ x3 @ x4,
(13)
where ~ denotes the exclusive OR function, which is nonunate. A fanout-free network which realizes (13) is shown in Figure 11. Note that the Chow parameters of all inputs are identical. Thus, Xl and x2 cannot be identified as inputs to a gate on the input level by the method of Section 3. In fact, it is not difficult to show that regardless of what network connects to q of Figure 11, the Chow parameters will be the same for all inputs. In effect the exclusive OR gate "washes out" the necessary reformation. Additionally, there is a problem of calculating the weights w~(Y) for a set of symmetric inputs Y. For example, when Y = (xl, x2), we have for f i ( X ) , wo(Y) = w f f Y ) = w2(Y) = 2. Thus, a simple counting procedure does not identify the two-input A N D gate of Figure 11. It seems, therefore, that a more extensive algorithm is required for the nonunate case. However, there is promise that a counting of truth table entries may stall be applicable. Golomb [4] shows that all switching function symmetry types have distinct Chow parameters if orders higher than one are considered. Another interesting question concerns stzes of various classes of functions. For example, it is of interest to know what fraction of unate functions are realized by fanout-free functions of unate gates. Unfortunately, neither closed form solutions nor recurrence
Analysts and Design of Fanout-Free Networks of Positive Symmetric Gates Xl ( ~ '
495
q
x2 x3
f9 (X)
x4 FIG 11 Exampleof a fanout-freenetwork containinga nonunategate TABLE V COMPARISONOF THENUMBEROF UNATEFUNCTIONSWiTHTHE NUMBERREALIZEDBYAON ANDAOMN FANOUT-FREENETWORKS Number of Number of Number of AON Numberof AOMN fanout-free fanout-free varmblesn unate functions funcUons functions 2 3 4 5 6
8 72 1,824 220,608 498,238,208
8 64 832 !5,104 352,256
8 72 1,152 26,304 773,376
relations have been found for the number of unate and threshold functions. The problem of unate function enumeration is similar to a problem which dates back to the 19th century (Kleitman [8]). Threshold function enumeration has received considerable attention, but the best results are values produced by computer enumeration (Muroga, Tsuboi, and Faugh [15]). Counting of fanout-free functions is somewhat more tractable. Hayes [7] and Kodandapani and Seth [9] have found recurrence relations for the n u m b e r of functions realized by AON and AOMN fanout-free networks. Bender and Butler [2] have derived closed form approximations to these recurrence relations. Table V is a summary of some of the results. It shows how the number of unate functions7 on exactly n variables compares with the number of functions reahzed by AON and A O M N fanout-free networks. Hayes [7] has shown that the ratio of the number of n-variable AON fanout-free functions to the n u m b e r of unate functions approaches 0 as n approaches oo. Table V indicates this ratio is small even for moderate n. Also, note that significantly more functions result when an M is added to an AON gate set. Thus, the trade-off between gate complexity and the n u m b e r of functions realized seems to favor increased gate set complexity. A n interesting question, therefore, is the number of functions realized by fanout-free networks of larger gate sets.
Appendtx. Proof of Theorem 11 THEOREM 11. Let f ( X ) be realizable by a fanoutfree network of positive symmetric gates and inverters. Then f ( X ) is a threshold functzon if and only tf tt is reahzable by a cascade. PROOF. Since f ( X ) is realized by a fanout-free network N of positive symmetric gates and inverters, it is also realized by a canonical network Nc obtained from N by pushing inverters to the primary inputs (as in Lemma 2). Since the transformation from N to Nc does not alter topology, N is a cascade if and only if Nc is a cascade. Therefore, it is necessary to consider only functions realized by canonical fanout-free networks. ( i f - - b y induction on the number of gates) Consider a cascade realizable function f ( X ) . If the cascade has one gate, then it follows immediately that f ( X ) is a threshold funcUon. Now assume that all functions realized by cascades of m - 1 gates are threshold functions, w h e r e f ( X ) is realized by a cascade of m gates.f (X) has the decomposition
f ( X ) =fi, nm (g(X-- U), U), wherefim rim(g, U) is the function realized by the output gate and g(X - U) is the function r This was obtained from Hamson's [5] table for the number N(n) of monotomc functionson n, n - 1, n 2, . , and l variable
496
JON T BUTLER
realized by a cascade o f m - I gates. Thus, by assumption, g is threshold reahzable and is associated with a weight-threshold vector, say (w~, wz . . . . . Wp; T). Let W be the sum o f weights; that is, W = ~¢-1 w,, and let T' = (tin - 1) W + T. S i n c e f ( X ) is positive, w, and T a r e positive [10, p. 189]. Thus, W i s the maximum weighted sum o f g . Further, W_> T; o t h e r w i s e f ( X ) ffi 0. It follows, therefore, that (wl, w2. . . . . wp+~. . . . . wp+n -~;T'), where wp+j = W for 1 .~ j _< nm - 1, is a weight-threshold vector f o r f ( X ) . (only if) L e t f ( X ) be a threshold function, and assume, on the contrary, t h a t f ( X ) is not reahzed by a cascade. It follows, therefore, that any fanout-free network N realizing f ( X ) has at least one gate g which receives inputs from two other gates gl and g2. Further, g~ and g2 do not connect to g through inverters, since it can be assumed, without loss o f generality, that N as a canonical network. Figure 12 shows the subnetwork N~ o f N containing just g~, g2, and g. Inputs a,, b,, and e, come from other subnetworks or are primary inputs to N and q drives another subnetwork o f N or is itself the output o f N. If f ( X ) is a threshold function, the successive applications o f Theorem 9 can be used to show that q = G(A, B, C) is a threshold function also. Since the variables in A are symmetric with each other they can be associated with the same weight w3 in the threshold realization o f q = G(A, B, C). Similarly, all vanables in B and C can be associated with the same weights we and wc, respectively. Thus, q = G(A, B, C) = 1 if and only if nA
nB
nC
WA ~ a ~ + w ~ ~ b , + w c ~ c~_> T. L--1
z~l
z--1
Since gl, g2, and g are positive symmetric gates with thresholds t~, t2, and t, respectively, it follows that
T > (tl
hWA + (t -- I)Wc _> T,
(14)
t2ws +
05)
(t -
l)wc _> T,
-- I)WA -I- (/2 --
I)WB + (t -- I)Wc,
(16)
for l _< t _< nc + I. Adding (14) to (15), multiplying (16) by 2, and comparing the resulting two inequalities yields tlWA + t2WB + 2(t -- I)Wc _> 2T > 2(h - l)WA + 2(t2 -- 1)W8 + 2(t -- l)wc.
Rearranging yields (2 - tl)WA + (2 -- t2)WB > 0.
(17)
(17) is satisfied only when tl = l or t2 = l or both. The case for t = nc + 2 never occurs. That is, for t = nc + 2 (g is an A N D gate), a similar derivation shows that tl = nA (g~ is an
Af
a2 al
Bt
b2
b% C
q = G(A,B,C)
c2 CnC FIG 12 SubnetworkN~of N containingthree posRlvesymmetricgates
A n a l y s i s a n d D e s i g n o f F a n o u t - F r e e N e t w o r k s o f Positive S y m m e t r i c Gates
497
A N D gate) or t2 = nn (g2 Is an A N D gate) or both. However, this is impossible, since the output o f an A N D gate in a fanout-free network is never apphed to the input of another A N D gate. Consider the following set of inequahties, which must also hold tf q = G(A, B, C) is a threshold function. tlWA + t2wn + (t -- 2)Wc --> T,
(18)
T > nAWa + (t2 -- I)WB -t- (t -- 2 ) w e ,
(19)
T > (tl - 1)wA + nBwn + (t - 2 ) w c ,
(20)
for 2 0.
(21)
(20) tS satisfied only when tx = nA or t2 = nn or both. The case for t = 1 (g is an O R gate) is impossible, because a similar derivation shows that this imphes tl = 1 (gl is an O R gate) or t2 = 1 (g2 is an OR gate) or both. However, the interconnection of two O R gates never occurs in a fanout-free network. To satisfy both (17) and (21), either t l = 1 and
t2=nB
(22)
or
tl = h A
and
t 2 = 1.
(23)
Consider only (22); the result for (23) is analogous. Substituting (22) into (14) and (16) and comparing yields WA > (rib -- OWn.
(24)
Substituting (22) into (18) and (19) and comparing yields wn > (hA -- I)WA.
(25)
Since na >-- 2 and nn --> 2, (24) and (25) Imply the contradictory requirements WA> WB and WB > WA. Thus, q = G(A, B, C ) is not realizable and it must be that the o n g m a l assumption t h a t f ( X ) is a threshold function is correct. Q.E.D. ACKNOWLEDGMENTS. The author is indebted to Mark L. Ketelsen and Kyung-Yong Chwa for conversations which inspired topics in this paper. Also, special thanks are due Professor Ketelsen, Professor Edward Bender, and the referees for a careful review. REFERENCES 1 BANDYOPADHYAY,S, PAL, A, AND CHOUDHURY, A K Characterization of unate cascade reahzabdlty using parameters IEEE Trans Comptrs C-24 (Feb 1975), 218-219 2 BENDER, E A, AND BUTLER, J T Asymptotic approxtmanons to the number of fanout*free functions Submitted to IEEE Trans. Comptrs 3 CURTIS, H A A New Approach to the Design ofSwttchmg Czrcutts Van Nostrand, Pnnceton, N J, 1962 4 GOLOMB, S W On the classification of Boolean functions IRE Trans CIrcmt Theory CT-6, Spec Supp (May 1959), 176-186 5 HARRISON,M A Introductwn to Swltchmg and Automata Theory McGraw-Hdl, NewYork, 1965 6 HAYES,J P The fanout structure of switching functions J ACM 22, 4 (Oct 1975), 551-571 7 HAYES, J P Enumeration of fanout-free Boolean functions J ACM 23, 4 (Oct 1976), 700-709 8 KLEITMAN,D On Dedekmd's problem The number of monotone Boolean functions Proc. Amer Math Soc 21 (1969), 677-682 9 KODANDAPANI,K L, AND SETH, S C On combinational networks with restricted fanout To appear in 1EEE Trans Comptrs 10 KOHAVI,Z Switching and Finite Automata Theory McGraw-Hall, New York, 1970 11 LEwis II, P M, AND COATES, C L Threshold Logic Wiley, New York, 1967 12 MINNICK,R C A survey of mlcrocellular research J ACM 14, 2 (Aprd 1967), 203-241 13 MINNICK,R C A system of magnetic bubble logic IEEE Trans Comptrs C-24 (Feb 1975), 217-218
498
JON T BUTLER
M U K H O P A D H Y A Y , A Unate cellular logic 1EEE Trans Comptrs. C-18 (Feb 1969), 114-121 15. MUROGA, S., TSUBOI, T., AND BAUGH, C Enumeration of threshold functions of eight variables. IEEE Trans. Comptrs. C-19 (Sept. 1970), 818-825. 16. SAS^O, T., AND KINOSHITA, K. On fanout-free functions and unate cascade functions (in Japanese) In Papers Tech. Group Electron Comput, lnst Electron Commun Eng Japan, Paper EC77-7, May 1977 17 YAU, S.S., AND TANO, Y S. On identification of redundancy and symmetry of swathing funcUons IEEE Trans. Comptrs C-20 (Dec 1970, 1609-1613. 14
RECEIVED MARCH
1977,
REVISED SEPTEMBER 1977
Journal of the Assoclauon for Computing Machinery, Vol 25, No 3, July 1978
T. BUTLER
Northwestern Umverstty, Evanston, llhnms ABSTRACT Art algorithm is presented for assigning functmns to gates in a fanout-free network so that a gwen function is reahzed Since the method is tabular, ~t IS easily programmed As long as the gates used are symmetric and positive the synthesis technique can be tadored to the particular set of gates available, for example, AND, OR, and majority gates It is shown that the functions realized by such networks are a proper subset of the set of unate functions but not of threshold functions Also, ~t is shown that the fanout-free functions that are threshold realizable are exactly those reahzed by the cascade, a special case of the fanout-free network KEY WORDS AND PHRASES swItchmg funcuons, fanout, fanout-free functions, fanout-free networks, unate funcUons, threshold funcUons, posmve symmetnc funcUons, Chow parameters CR CATEGORIES. 6 1
1. Introduction
An important characteristic of switching circuits is fanout. In particular, a circuit where at least one network input or one gate output connects to more than one gate input is said to possess fanout; otherwise, it is fanout-free. Figure 1 shows three fanout-free networks. Note that for each input x,, there is a unique path to the output. Because of this, it is very easy to fred an assignment of values to other network inputs so that the output is sensitized to x,; that is, the output varies when x, varies. Such assignments constitute tests for stuckat faults (Kohavi [101). Unique paths also imply the absence of both static and dynamic hazards. Because it is difficult and expenswe to replicate bubbles in magnetic bubble logic, fanout-free circuits are preferred over clrcmts wtth fanout (Minmck [13]). In view of these advantages, the fanout-free network is an important area of research. For example, Hayes [6] has shown that fanout-free functions realized by networks of AND's, OR's, and inverters can be identified by the use of the adjacency relation. Kodandapani and Seth [9] extended this concept to circuits with AND's, OR's, exclusive OR's, majority gates, and mverters. Although all switching functions can be realized by a network of AND's, OR's, and inverters, not all switching functions can be reahzed by a fanout-free network of such gates. With respect to just fanout-free circmts, there is a significant advantage to making the gate set as large as possible (Bender and Butler [2]). Thus, a natural extension of present studies is to consider more general gate sets. In particular it is shown here that positive symmetric gates (such as the AND, OR, and majority gate) have properties that allow an easily applied tabular synthesis algorithm. More general gates, on the other hand, do not have these properties. The format of the paper is as follows. General permission to make fair use in teaching or research of all or part of this material is granted to |ndlvldual readers and to nonprofit hbranes acting for them provided that ACM's copyright notice is given and that reference is made to the pubhcatlon, to its date of issue, and to the fact that reprinting privileges were granted by permission of the Association for Computing Machinery To otherwise reprint a figure, table, other substanual excerpt, or the entire work requires specific permission as does republication, or systematic or multiple reproduction This research was supported by the National Science Foundation under Grant MCS-7600326 Author's address Department of Electrical Engineering, Northwestern Umversity, Evanston, IL 60201 © 1978 A C M 0004-5411/78/0700-0481 $00 75 Journal of the Assocaatlonfor ComputingMachinery,Vol 25, No 3, July 1978,pp 481-498
482
JON T BUTLER xI
x 2
x3 x4
x5 x6
(a)
x1
x2 x3 x4
x5 x6
(b)
xI
x2 x3
x4 x5 x6 (¢)
FIG 1
Examples of three fanout-fre¢ networks
Section 2 defines switching theory concepts that have a direct bearing on the subject. Of specific interest are positive, negative, unate, voting, threshold, cascade realizable, and fanout-free realizable switching functions. In Section 3 it m shown that a necessary and sufficient condition for a fanout-free function to be unate Is that it be reahzed by unate gates. Thus, part of the synthesis algorithm is a test for unateness. Section 4 m a description of the algorithm. It m shown that the Chow parameters of a funcuon and symmetry among variables can be used to identify inputs to specific gates. In Section 5 the relationship between fanout-free, unate, and threshold functions is shown, and in Section 6 possible extensions of this research are presented.
2. Definitions and Introductory Concepts L e t f ( X ) denote an n-vanable switching function, where X = {xl, x2 . . . . . xn}. Function
f(X) lmphes g(X), denotedf(X) ~ g(X), if for all assignments of values to xl, x2 ..... and Xn, g(X) = 1 wheneverf(X) = 1. For example, if fi(X)
= xlx2
(1)
Analysis and Design of Fanout-Free Networks of Posmve Symmetric Gates
483
and
J~(X) = xlx223,
(2)
thenj'~(X) ~ fi(X). Let f ( X l O --> x,) and f ( X I 1 ---> x3 denote the residue functions obtained from f ( X ) by setting x, = 0 and x, ffi 1, respectively. Thus, f i ( X I 0 ~ xl) ffi 0 and f2(X I 1 --.~ xl) = xl~a. This can be extended to more than one variable in a logical fashion; for example, ./~(XI 1 --, xl, 1 ~ x2, 0 ~ x3) = 1. f ( X ) is positive (monotone increasing) m x, i f f ( X I 1 ~ x,) ~ f ( X I 0 ~ x,). Simdarly, f ( X ) is negative (monotone decreasing) in x, i f f ( X I 1 ~ x,) ~ f ( X I 0 ~ xj. For example, f i ( X ) is positive in x~ and x2, while f i ( X ) is positive in x~ and x2 and negauve in x3. A function which is either positive or negatwe in x, is said to be unate in x,. 1 A function which is either positive, negative, or unate m all variables mssaid to be a positive, negative, or unate function, respectively. For example, fi(X) is both a positive and a unate function, while/~(X) is simply unate. Consider the Shannon decomposition o f f ( X ) about x, ~ X,
f ( X ) = f ( X l 0 ~ x,)~, + f ( X l 1 ~ x,)x,. I f f ( X ) is positwe (negative) in x,, t h e n f ( X I 0 ---> x,) ~ f ( X [ f ( X I 0 - - > x,)), a n d f ( X ) has the alternate form
f ( X ) = f ( X I 0 ~ x,) + f ( X I 1 ~ x,)x,,
1 ---> x,) ( f ( X I 1 ---> x,) ~-0
( f ( X ) = f ( X l O ~ x,)Sc, + f ( X I 1 ~ x,)).
Note that for any assignment of values to X - {x,}, i f f ( X ) is positive in x,, either ( l ) f ( X ) is independent of x, or (2)f(X) = x,; f ( X ) is never ~,. Furthermore, the converse is also true. f ( X ) is a threshold function if there exists a set of real-valued weights {w~, w2. . . . . wn} and a real-valued threshold T, such that f ( X ) = 1 if and only if W~Xl + w2x2 + .. • + WnXn --> T, where the logic values of x,, 0 and 1, are viewed as integer values, 0 and 1, respectively; where + denotes ordinary addition; and where concatenation represents ordinary multiplication. Let (w~, w2, ... , wn; T) denote the weight-threshold vector of f ( X ) . For example, fx(X) andf2(X) are threshold functions with weight-threshold vectors (1, 1, 0; 2) and (1, 1, - 1 ; 2), respectively. The set of threshold functions has been shown to be a subset of the set of unate functions. That it is a proper subset follows from the fact that the unate function, x~x2 + x3x4, is not threshold realizable. Of particular interest in this paper is the voting funcUon. A voting functionfin(X) is 1 if and only if t 9r more of its n variables are 1. Thus, fin(X) is a threshold function with weight-threshold vector (1, 1, ..., 1;t). For example, the two-input A N D and OR functions correspond to fi2(xl, x2) and fi2(x~, x2), respectively, while the three-input majority function, MAJ(xl, x2, x3), corresponds t o i l 3(x~, x2, x3). f ( X ) is (totally) symmetric if all permutations of variables leave the function mvariant. For example,fi(X) is symmetric, for X = {x~, x2}, whilefi(X) andf2(X) are not symmetric, for X = {Xl, x2, x3}. The gates used in the fanout-free networks considered in this paper are both positive and symmetric. The following result shows that these are also voting functions. LEMMA 1 [5, p. 180]. f ( X ) is a positive symmetrw functwn if and only if it is a voting funclton.
Figure 2(a) shows an n-input gate that realizesfi n(X). Standard symbols will be used for the n-input A N D gate (Figure 2(b)), the n-input OR gate (Figure 2(c)), and the three-input majority gate (Figure 2(d)). AND, OR, and majority gates are commonly available, while of the gates on three or more variables, the voting functions are among the easiest to implement. Let G denote the set of gates used to implement a fanout-free funcuon. It will be 1 A f u n c U o n w h i c h IS b o t h p o s m v e a n d n e g a U v e m
x, ts i n d e p e n d e n t
o f x,
484
JON T BUTLER
x
x2
~
xl x2
•
xn x
Xn"-~....,,/
x3
n
(a)
(b) F{o 2
(e)
(d)
Voting, AND, OR, and majority representatmns
assumed that all such sets include the inverter. It follows, therefore, that iffi n(X) is in G, thenfn-t+l n(X) is also effectively in G. Since fn-t+l n(X) =ftn(Xl~, ~ x,, for 1 ~ i _< n),
(3)
fi-t+t n(X) can be implemented by connecting inverters to the output and inputs of a gate which reahzesfin. In this paper it will be assumed that iffi~(X) ts realized by a gate in G, so also isfn-t+~ n(X). Note that (3) is De Morgan's theorem if t = 1 or n. If the two-input A N D or OR gate is in G, then G, in effect, contains the n-input A N D or OR gate, respectively, for n. This follows because the latter gates can be implemented by a fanout-free network of two-input gates. It will be convenient to assume that an minput A N D (OR) gate output never drives an n-input A N D (OR) gate input, since the combination is equivalent to an m + n - 1 input A N D (OR) gate. As in [9], G will be denoted by a set of letters specifying the gates. For example, A O M N refers to the set of two-input AND's, OR's, three-input majority gates, and inverters. Ft~ is a gate realizing fi n(X). Thus, F24Fa 4Fa 5N denotes a gate set consisting of voting gates f24(X),fi 4(X), a n d ~ 5(X) and inverters. Note M = F~ a and F35 have no counterpart since adding mverters to the inputs and output of these gates leaves their function unchanged. It can be seen that, in general, when n is odd, Frn/21,~has no counterpart. In many design applications the complements of network inputs are also available (for example, as the outputs of flip-flops). Because of this, it is useful to consider networks where inverters occur only on primary inputs. A fanout-free network of positive symmetric gates and inverters is canonical if all inverters appear on network inputs only. 2 LEMMA 2. Let G be a gate set consisting of positive symmetric gates and an inverter. For each fanout-free network N on G, there extsts a canonical network Nc on G which reahzes the same function. PROOF. If N is already canonical, N = Nc. Otherwise, N contains at least one inverter which connects to the output of some gate Ft n. From (3), the function realized by this combination is also realized by a gate F~-t÷t ~ with inverters on all inputs. These, in turn, connect to primary inputs or gate outputs. In the latter case a similar sttuation exists and the inverters can be "pushed back" toward the network inputs again. In this way internal inverters can be eliminated without changing the network's function. Q.E.D Lernma 2 shows that when complements of pnmary inputs are available, any fanoutfree network can be converted to an reverter-free circuit. 3. Fanout-Free Networks of General Gates
Although many switching circuit designs use unate gates, such as inverters, OR's, AND's, and threshold elements, it ts of interest to consider fanout-free designs composed of more general gates. The main result of this section is a proof that the existence of at least one nonunate gate in a fanout-free realization o f f ( X ) imphes f ( X ) is nonunate, and if only unate gates are used, f ( X ) is unate. An analysis tool of significant application is the simple disjunctive decomposition (Curtis [31). In particular, f ( X ) has a simple disjunctive decomposition (SDD) if and only if 2 This excludes any mverters used to Implement fn-t+l n(X) fromfi ~(X) These are assumed to be part of the gate tmplementatmn, not part of the network.
Analysis and Design o f Fanout-Free Networks o f Positive Symmetric Gates
(
485
f(X)= g(h,Z)
Z L FiG 3. Network rcahzmgf(X) = g(h(Y), Z)
f ( X ) = g(h(Y), Z),
(4)
where X = Y O Z a n d Y tq Z = O ( 0 = null set). A n S D D is nontrivial if [ YI > 1 a n d I Z [ _> 1. Example, f2(X) = xlx2Yc3 has a n o n t n v i a l S D D of the form f2(X) = g2(h2(xl, x2), x3),
(5)
where g2 = h2~3 a n d h2 = xlx2. F u n c t i o n s with a n S D D of the form (4) can be realized by the network shown in Figure 3. F r o m a n information theoretic point of view, the information about the value of Y required to determine the value o f f ( X ) can be encoded in a single bit h. T h u s , f (X) "needs to know" only that a particular assignment of values to Y, A r, falls into one of two categories represented by h = 0 a n d h = I. As a n example, let X = {Xm, x2, x3}, Y = {xl, x2}, a n d Z = (xs}. j~(X) = x~x2~s has a n S D D o f the form shown in (5) because, with respect to x, a n d x2, f ( X ) needs to know that either I. xl = x2 = l (in which c a s e f ( X ) = Yc3),or 2. one or both of Xl a n d x2 are 0 ( f ( X ) = 0 regardless of x3). O n the other hand, i f f ( X ) = MAJ(Xl, x2, xa), assignments o f values to Y must fall into three categories:
I. Xl = x2 = l ( f ( X ) = l regardless o f xa), 2. exactly one of xl a n d xz is 1 ( f ( X ) = x3), or 3. xl = x2 = 0 ( f ( X ) = 0 regardless of x3). Since at least two bits are required to encode this information, it follows that the majority function has n o nontrivial SDD. The significance of S D D ' s with respect to fanout-free functions is shown by the following result. THEOREM 1. Let f ( X ) be a function reahzed by a fanout-free network o f two or more gates. Then, f ( X ) has at least one nontrivial S D D o f the form f ( X ) = g(h(Y), Z), where g and h are fanout-free functions. Note that T h e o r e m 1 is not true, in general, for fanout-free functions of one gate. F o r example, the majority function has no SDD, a n d so a fanout-free network composed o f just a single such gate has no SDD. 3 T h e o r e m l provides the background for the m a i n result of this section; that is, a fanoutfree function f ( X ) is unate if a n d only if it can be realized by unate gates exclusively. Intuitively, the proof ts based o n the fact that w h e n the o u t p u t f i s sensitized to a n input x, by some choice o f values for X - (x,}, e l t h e r f = x, o r f = ~,. Each gate between x, a n d f acts as a n inverter or a n identity gate. If there are a n odd n u m b e r of inverters, f = .L; otherwise f = x,. I f a unate gate acts as an inverter for some assignment o f values to its other inputs, it can never act as a n identity gate a n d vice versa. Thus, if the path from x, t o f i s through unate gates only, e i t h e r f = x, o r f = Yc,, but not both. Thus, f ( X ) is u n a t e a In fact, it Is easy to show that the only voting functions with SDD's are the AND and OR of n variables, n>_2
486
J O N T. B U T L E R
in x,. A gate nonunate in x,, on the other hand, can act as both an inverter and identity gate. If such a gate appears in the path between x, andfi there are assignments to network inputs such that f = x, and f = ~¢,. Thus, f ( X ) is not unate in x,. THEOREM 2. A fanout-free function f ( X ) is unate if and only if it is reahzable by a
fanout-free network composed entirely of unate gates. Theorem 2 extends Hayes' [6] result for fanout-free networks o f AND's, OR's, and inverters (AON) and Muldaopadhyay's [14] result for AON cascades. It Is an immediate result o f Theorem 2 that nonunate functions are not realizable as networks of inverters and positive symmetric gates. An appropriate first step in the synthesis algorithm for fanout-free networks of such gates, therefore, is to test for unateness. An immediate corollary to Theorem 2 is: COROLLARY 1. A fanout-free function ts a positive function if it ,s realized by a fanout-
free network of positive gates. The converse of Corollary 1 is not true. For example, consider the trivial network in which the primary inputs Xl and x2 are each apphed to inverters with outputs which are in turn applied to a gate which realizes M~, a negative function. The function reahzed is ab, a positive function. Thus, a fanout-free network of negative gates can realize a positive function.
4. Synthesis of Canonical Fanout-Free Networks of Positive Symmetric Gates and lnverters In order to determine the assignment of functions to gates in a fanout-free czrcuit so that a given function f ( X ) is realized, it is necessary to identify which network inputs drive certain gates. In the algorithms of Hayes [6] and of Kodandapani and Seth [9], all pairs of variables are tested to determine if a relatton, called adjacency, exists. Since adjacency is an equivalence relation, it divides the set of variables into equivalence classes. These classes are then used to determine variables which are applied to the same gate. In this section a tabular method which identifies equivalence classes is presented. It is based on the Chow parameter [11, pp. 417--422] characterization of variables. Since the algorithm is tabular, it is very easily programmed. Originally studied by Golomb [41 to classify switching funcUon symmetry types, Chow parameters have found extensive applicauon in the analysis of threshold functions [11] and in the synthesis of A O N cascades [ 1]. Although a number of different definitions exist, it will be convement to use the following one. Let f ( X ) be a swttching function on n variables. The 0th order Chow parameter of f(X), Co, is 2n
Co = Y f(XIA, ~ X), ~0
where A, is an assignment of values to X whose binary equivalent is i andf(X[A, ~ X) is the value o f f ( X ) for that assignment. For example, Ao corresponds to all O's, A1 corresponds to all O's except xn = 1, etc. The summation sign denotes integer addition, where f(X[ A, --* X) = 0(1) is taken as the integer 0(1). Co is just the number of l's m the truth table o f f ( X ) . For example, forf3(X) shown in Table I, Co = 6. TABLE
I. A N EXAMPLE TO ILLUSTRATE CHOW PARAMETER CALCULATION
x,
x2
x3
x,
f~tx,, x2, x3, x,)
0 0 0 0 0 0 0 0
0 0 0 0 I I 1 1
0 0 1 1 0 0 1 1
0 ! 0 I 0 ! 0 1
0 0 0 ! 0 0 0 1
x,
x2
x~
x,
f~fx,, x2, x~, x,)
0 0 0 0 ! 1 1 !
0 0 1 1 0 0 1 1
0 I 0 1 0 1 0 1
0 0 0 ! 0 1 1 1
Analysis and Design of Fanout-Free Networks of Positive Symmetric Gates
4 87
2® x3
~
x4 FIG 4
1
f3 (xl'x2'x3'x4)
I
A fanout-free network which reahzesf3(xl, x2, x3, x4)
The first-order Chow parameters Cj o f f ( X ) for 1 _<j _< n are defined as follows. 2n
cj = ~ ~f(X).x+lA,~ X). tzO
Cj is the number of times 1 appears m both the xj column and t h e f c o l u m n o f the truth table f o r f ( X ) F o r example, f o r f l ( X ) shown m Table I, C1 = 4, Ce -- 4, C3 -- 5, C4 = 5. Chow parameters on a network diagram will be denoted by circles. F o r example, a fanoutfree network to realize the function of Table I is shown in Figure 4. Note that inputs which are symmetric, such as xl and x2, have the same Chow parameter value. In addition it is interesting to note that the smallest Chow parameters are those associated with inputs to a gate which has no inputs from other gates. One then wonders if this is a general characteristic. As a step toward the answer of this question, consider the following. THEOREM
3.
fin(X) = f i n - 2 ( X - (x,, xj}) + (x, + xj)fi-~ n-2(X - (x,, x~}) + (x,xj)fi-2n-2(X- {x,, xj})
for
IX[ _> 2.
(6)
PROOF. The hypothesis follows directly from the observation that fin(X) = 1 if and only if one o f the following three conditions holds. 1. at least t of the variables in X - {x, xj} are 1, 2. t - 1 of X - {x,, xj} are 1 and either x, or xj (or both) are 1, or 3. t - 2 of X - {x,, xj} are 1 and both x, and xj are 1. 4 Q.E.D. Theorem 3 shows that a positwe symmetric function can be decomposed into the sumof-products of lower order positive symmetric functions, since both x, + xj and x,xj are positive symmetric. Thus, wRh respect to assignments of values to X - {x,, xj}, f i n ( X ) = 0, 1, x, + xj, or x,xj. In a fanout-free network, the network output can be sensitized to the output o f any gate G. F o r a fanout-free network o f positive gates, the path from G to the network output is inverter-free. Thts yields the following corollary. COROLLARY 2. Let f ( X ) be a function realized by a fanout-free network of posttive symmetrtc gates, and let x, and xj be inputs to the same gate. For any assignment of values to X - {x,, xj} etther
1. f ( X ) is independent of x, and xj, 2. f ( X ) = x, + xj, or 3. f ( X ) = x,x,. Consider a case where x, and xj are not applied to the same gate. Figure 5 shows a network in which x~ is applied to a gate G which is also driven by a network N1 of at least one gate. x,, in this case, denotes an input to N1. The relative value of C, and Cj, the Chow parameters of x, and xj, respectively, can be calculated by observing that each o f the 2 Ivl assignments to V produces a (possibly 0) contribution to C, and Cj. F r o m Corollary 2, assignments of values to V c a u s e f ( X ) to respond in different ways to a and xj. Consider each in turn. 4 W h e n t ffi n or n - !, voting functions to the right o f the e q u a h t y sign ta (6) h a v e a threshold larger than the n u m b e r o f inputs If it ts assumed t h a t f i n ( X ) = 0 for t > n, then (6) wall be correct for these cases.
488
JON T BUTLER
xjQ FiG 5
f(x)
An example for the calculation of relauve Chow parameters
1. Assignments to V s u c h t h a t f ( X ) i s i n d e p e n d e n t o f a a n d x / S m c e f ( X ) i s i n d e p e n d e n t of a, it is also independent o f x, (and U). Thus, for all 2 T M assignments of values to U O {x, xj}, f ( X ) = 0 or 1. It follows, therefore, that the contribution o f these assignments to C and Cj is the same. 2. Assignments to Vsuch t h a t f ( X ) = a + x / F o r this c a s e , f ( X ) = 1 when a = 1. Thus, all assignments to U O {x,, xj} for which xj = 1 contribute 1 to C2. There are 2 T M such assignments. However, the contribution to C, can be at most 2 IUl+l, and this occurs only when x, = 1 implies a = 1, or stated algebraically, when a = g(U) + x~. 3. Assignments to Vsuch t h a t f ( X ) = a x / F o r this c a s e , f (X) = 1 when a = x = 1. The contribution to Cj is Co o f N~, the number o f assignments to U U {x,} which cause a to be 1. However, the contribution to C, can be at most Co of N1. This occurs only when a = 1 implies x, = 1 or a = g(U)x,. If G realizesflm, the O R function, then no assignment to V exists such t h a t f ( X ) = axe. Thus, only cases 1 and 2 occur. Case 1 corresponds to the same contnbutton to C, and Cj always, while for case 2, the contribuUons are identical only when a = g(U) + x,. But the latter is impossible; otherwise x, would have been applied to G not N~. Thus, C, < C~. Similarly, if G realizesf, n, the A N D funcUon, only cases 1 and 2 occur, and it follows in like fashion that C, < Cj. F o r all other choices for functions of G, cases 1, 2, and 3 occur, and again C, < Cj. This proves the following. THEOREM 4. The smallest first-order Chow parameters in a fanout-free network of positive symmetric gates are associated with gates whose inputs are network inputs. Since the Chow parameters o f any funcUon are very easily calculated, Theorem 4 provides a simple way to identify gates at the primary input level. However, as is shown in Figure 6, this characterization is not complete. Here four inputs, x~, x2, x3, and x4, all have the same parameters, but are not all apphed to the same gate. However, this problem is alleviated by observing that xl and x2 are symmetric, x3 and x4 are symmetric, while no other pairs are symmetric. A generalization o f this observation is: THEOREM 5. Two inputs to a fanout-free network of positive symmetrw gates are symmetric if and only if they are applied to the same gate. The identification o f symmetric inputs can be accomplished easily in tabular form (Yau and Tang [17]). In partwular a symmetry test follows from: THEOREM 6 [17, p. 1611]. f ( X ) ts symmetric in x~ and x~ if and only if f ( X I l ~ x,, 0---~ xj) = f ( X I 0 - - , x,, 1 ~ xj).
(7)
Theorem 6 shows that to determine symmetry between variables x, and xj, it is necessary only to determine that residue f u n c t i o n f ( X I 1 ~ x,, 0 ~ x~) is 1 w h e n e v e r f ( X [ 0 ~ x,, 1 ~ x~) is 1 and vice versa. In the truth table f o r f ( X ) , this amounts to determining ff for every assignment Ap to X such that x, = 0 and xj = 1 (x, = 1 and x~ = 0) for w h i c h f ( X ) = 1, there is another assignment h q , identical to Ap except x, = 1 and xj = 0 (x, = 0 and xj = 1), for w h i c h f ( X ) = 1. Thus, a second step in the algorithm is to determine symmetry o f variables. The Chow parameter and symmetry tests alone are not sufficient to identify completely
Analysis and Design of Fanout-Free Networks of Positive Symmetric Gates
489
z2
x3
Flo 6 A fanout-free network m which the Chow parameters of the inputs of two gates are ~denttcal
FIG 7 Example of a threshold funetton which ts not fanout°freem posture symmetricgates
gates at the input level. For example, consider fi(X) reahzed by the threshold gate of Figure 7. xl, x2, and xa have the lowest Chow parameters and are symmetric, b u t f ( X ) has no nontrivial SDD, and so is not fanout-free in positive symmetric gates. L e t f ( X ) be a switching function symmetric in Y C X, where I Yt > 1. Let AY(j) be an assignment of values to Y c o n t a m i n g j l's, 0 _<j _< [ Y [. Then t h e j t h weight parameter of Y, wj(Y), is the number of assignments A to X where f(XIA ~ X) -- 1 in which the assignment to Y corresponds to AY(j). F o r example, c o n s i d e r f i ( X ) of Figure 7, and let Y = {xl, x2, x3}. wo(Y) is the number of assignments to X for w h i c h f ( X ) = 1 where no l's appear in x~, x2, or xa. Only x~, x~, xa, x4, x5 = 0, 0, 0, 1, i c a u s e s f ( X ) to be 1. Thus, wo(Y) = 1. Let A~Y = 001. Then, two assignments, xl, x2, xa, x4, x5 = 0, 0, 1, 0, 1 and 0, 0, 1, 1, 1, map to 1. Thus, Wl(Y) = 2. Similarly, w2(Y) = 3 and w3(Y) = 3. THEOREM 7. Let f ( X ) be a positive function symmetric in Y, Y C X and l Y[ > 1. f ( X )
has the SDD f ( X ) = g ( f t*lrl (Y), X -
Y),
(8)
if and only if there exist posmve integers m and m' such that wj(Y) = m for j < t and wj(Y) = m' for t _<j, where * indicates etther the complement or identity operation, and m#m'. PROOF (if) Ifwj(Y) = m f o r j < t and wj(Y) = m' for t _<j, t h e n f ( X ) must know the assignments o f values to Y to within two classes. Thus, with respect to Y, f ( X ) has an S D D o f the form
f ( X ) = g(h*(Y), X -
Y).
Thus, h(Y) =filvl(Y) follows from the fact that h(Y) must be 0(1) for assignments to Y which have i < t l's and 1(0) for assignments in which there are t _< i l's. (only if) Assume f ( X ) is gwen by (8). Since f ( X ) is positive for all assignments to X - Y either
1. f ( X ) = 0 regardless offitrt(Y ) (0 contribution to wj(Y) for a l l j ) , 2. f ( X ) = 1 regardless offilyt(Y ) (contribution the same to all wj(Y)), or 3. f ( X ) = f i l r l ( Y ) (0 contribution to wj(Y) w h e r e j < t and contribution o f I to all wj(Y) where t _<j). Thus, it follows that wj(Y) = m for j < t and wj(Y) = m' for t _<j, where m # m'. Q.E.D. Theorem 7 shows that an SDD revolving a positive symmetric function can be identified by counting entries in a truth table. In fact the test indicated by Theorem 7 can be the sole basis of a synthesis algonthm. It would, however, entail the examination of subsets o f the set X of which there are 2 Ixl. Since the Chow parameter and symmetry tests are simple, they provide an effective means of eliminating this search. An immediate corrollary to Theorem 7 is the following. COROLLARY 3. Let f ( X ) be a posittve function symmetric in Yi, Y2, .... and Yp; Y, C X
and [ Y,I > 1. f ( X ) has the complex dtsjunctive decomposition
490
JON T BUTLER
f(X)
= g(f~,r,,(Y~),f~lr~,(Y2) .... ,f~lr~,(Yp), X -
Y,-
Y2 . . . .
Yv)
i f and only i f there exist p pairs o f positive integers (mcn~), 1 _< i _< p, such that wj(Y,) = m, f o r j < t, and wl(Y,) ffi m; f o r t, _<j, where m, ~ m[. C o r o l l a r y 3 is used in the synthesis a l g o r i t h m d e s c r i b e d as follows. SYNTHESIS ALGORITHM. To determine iff (X) is fanout-free m a set G consisting of mverters and at least one type of posmve symmetric gate and to find a reallzaUon off(X) whenever it exists Inverters in the network synthesized appear on primary inputs (canomcal fanout-free realization) 1 Determine fff(X) is unate If ~t ~s, go to 2, otherwise go to 7 2 Convertf(X) to a posmve funcUon h(X) by complementing appropriate values m X If h(X) is not a posmve symmetric function, go to 3 If h(X) is a posmve symmetric functmn realized by a gate m G, go to 6 Otherwise, go to 7. 3 Compute the Chow parameters of h(X) 5 Let Y be the set of variables whose Chow parameters have the smallest magmtude If[ Y[ = 1 go to 7; otberwlse go to 4 4 Dlwde Y into disjoint subsets Yt, Y2, •, Yp such that for all x,, x~ ~ Yk, x, Js symmetric to x~, but to no other variable outside of Yk If I Y, {= 1 for any i, go to 7 Otherwise, go to 5. 5 For each Y, calculate w,(Y,), 0 _<j _< [Y,I If for each there exists a t, such that wj(Y,) = m forj < t, and ws( Y,) = m' for t, T.
Therefore, h ( Y ) is a threshold function with weight-threshold vector (wl, w2..... wp; T - W~). Let W2 be the weighted sum W2 = wlyl + w2y2 + "" + W,yplAY--~ Y,
corresponding to an assignment A Y to Y such t h a t f ( Y ) = 1. Thus, g(1, Z ) is 1 if and only if W2 + W]Zl + w~z2 + "
Since h(Y) is positive, h(Y) = 0 when y~ = y2 . . . . . if
.-1- WqZq ~ T.
(11)
yp = O. Thus, q(0, Z) is l if and only
0 "1- W~Zl '4" W2Z2 "[" "" "1- W ~ q --> T.
(12)
Analysis and Design of Fanout-Free Networks of Posittve Symmetric Gates
493
f7(X) = x l x 2 + x3x4 x3
FIG 9.
A fanout-free network of threshold gates which does not realize a threshold function
It follows from (11) and (12) that g(h,Z) is 1 if and only if
W2h + w~zl + w~z2 + "'" + W~Zq_> T, and so g(h, Z ) is threshold reahzable with weight-threshold vector (W2, w~, w~. . . . . w~; 7)). Q.E.D. Consider the case w h e r e f ( X ) is a function realized by a fanout-free network on some gate set G. If f (X) is realized by a single gate g, then f ( X ) is a threshold function if and only if g is a threshold gate. If f (X) is realized by a network with two or more gates, then Theorem 9 can be applied repeatedly to show that all gates must be threshold gates. Thus, THEOREM 10. I f f ( X ) is fanout-free and a threshold function, its fanout-free reahzation
contains only threshold gates. Unlike the result with respect to functions realized by fanout-free networks o f unate gates (Theorem 2), the converse of Theorem 10 is not true. F o r example, consider ~ ( X ) = xlx2 + xax4. Althoughf7(X) is realized by the fanout-free network o f threshold gates shown m Figure 9, it itself is not a threshold function. Note that Theorem l0 holds for the case in which gate set G contains both symmetnc and nonsymmetric gates. If G is restricted to contain only symmetric gates, then Theorem 10 implies that a fanout-free threshold function is always realized by a gate set consisting of positive or negative symmetric gates. This follows from the fact that a threshold function is also unate and that a unate function which is symmetric is either positive or negative in all variables. Consider now the problem of idenUfying fanout-free networks that realize threshold functions. A cascade is a fanout-free network m which all gates except one (at the input level) receive an input from exactly one other gate in the network. Figure 1(b) shows an example. Because of their simple topology, cascades are more easily analyzed, and so much o f the research on these networks precedes that o f the more general fanout-free network. F o r a survey o f papers on cascades before 1967, see Minnick [12]. Note that all one- and two-gate fanout-free networks are also cascades. Since a single positive symmetric function is a threshold functton, it follows that cascades of one and two positive symmetric gates realize threshold functions, exclusively. However, a more general statement can be made. THEOREM I I. Let f ( X ) be realizable by a canonical fanout-free network of positive
symmetric gates and mverters. Then f ( X ) is a threshold function if and only if it is realizable by a cascade. 6 PROOF. Although the proof is straightforward, it is long. See the Appendix. This is an unexpected result. It is convenient to represent the set of functions discussed in the diagram o f Figure 10. This shows the relationship between unate, threshold, and fanout-free functions. Note t h a t , ( X ) , the function used to show a unate function which is not fanout-free, is also not a threshold function. Also note t h a t , ( X ) , o f Figure 10, is a threshold function 6 Sasao and KmoshRa [16] have recently shown that lff(X) is realw.ableby an AON fanout-free network, then
f(X) is a threshold function if and only iff(X) is reahzable by an AON cascade
JON T BUTLER
494 Threshold functzons
f8(X ) = XlX 5 + x2x 5 + x3x 5 + + XlX3X 4 + x2x3x 4 + XlX3X 4 + x4x 5
Unate functzons
f6(X) =
x3x4 f7(X) = XlX ~
"..v.,~.~.~
•
a. b.
Fanout-Free Functions realzzed by symmetric gates and znverters all gates unate (top half clrcle) at least one nonunate gate (bottom half elrcle)
FIG 10 Relationships between unate functions, threshold funcuons, and fanout-free functions reahzed by symmetricgates and mverters (with weight-threshold vector (1, 1, 1, 3, 4; 4½)) that is also not fanout-free. This is because it has no SDD and is not itself symmetric. 6. Concluding Remarks
The synthesis technique described in this paper is basically a four-step process. 1. Determine whether the given function is unate. 2. Check which inputs drive gates at the input level (using Chow parameters). 3. Check for symmetry among these inputs. 4. Determine the gate functions. An interesting question concerns the extenmon of the synthesis techmque to more general networks. Unfortunately, some of the useful properties of fanout-free networks of positive symmetric gates and inverters do not carry over. For example, when nonunate gates are included in the gate set, the unateness test does not eliminate nonrealizable functions. Also, first-order Chow parameters have limited apphcation. For example, consider f9(X) = (xlx2) @ x3 @ x4,
(13)
where ~ denotes the exclusive OR function, which is nonunate. A fanout-free network which realizes (13) is shown in Figure 11. Note that the Chow parameters of all inputs are identical. Thus, Xl and x2 cannot be identified as inputs to a gate on the input level by the method of Section 3. In fact, it is not difficult to show that regardless of what network connects to q of Figure 11, the Chow parameters will be the same for all inputs. In effect the exclusive OR gate "washes out" the necessary reformation. Additionally, there is a problem of calculating the weights w~(Y) for a set of symmetric inputs Y. For example, when Y = (xl, x2), we have for f i ( X ) , wo(Y) = w f f Y ) = w2(Y) = 2. Thus, a simple counting procedure does not identify the two-input A N D gate of Figure 11. It seems, therefore, that a more extensive algorithm is required for the nonunate case. However, there is promise that a counting of truth table entries may stall be applicable. Golomb [4] shows that all switching function symmetry types have distinct Chow parameters if orders higher than one are considered. Another interesting question concerns stzes of various classes of functions. For example, it is of interest to know what fraction of unate functions are realized by fanout-free functions of unate gates. Unfortunately, neither closed form solutions nor recurrence
Analysts and Design of Fanout-Free Networks of Positive Symmetric Gates Xl ( ~ '
495
q
x2 x3
f9 (X)
x4 FIG 11 Exampleof a fanout-freenetwork containinga nonunategate TABLE V COMPARISONOF THENUMBEROF UNATEFUNCTIONSWiTHTHE NUMBERREALIZEDBYAON ANDAOMN FANOUT-FREENETWORKS Number of Number of Number of AON Numberof AOMN fanout-free fanout-free varmblesn unate functions funcUons functions 2 3 4 5 6
8 72 1,824 220,608 498,238,208
8 64 832 !5,104 352,256
8 72 1,152 26,304 773,376
relations have been found for the number of unate and threshold functions. The problem of unate function enumeration is similar to a problem which dates back to the 19th century (Kleitman [8]). Threshold function enumeration has received considerable attention, but the best results are values produced by computer enumeration (Muroga, Tsuboi, and Faugh [15]). Counting of fanout-free functions is somewhat more tractable. Hayes [7] and Kodandapani and Seth [9] have found recurrence relations for the n u m b e r of functions realized by AON and AOMN fanout-free networks. Bender and Butler [2] have derived closed form approximations to these recurrence relations. Table V is a summary of some of the results. It shows how the number of unate functions7 on exactly n variables compares with the number of functions reahzed by AON and A O M N fanout-free networks. Hayes [7] has shown that the ratio of the number of n-variable AON fanout-free functions to the n u m b e r of unate functions approaches 0 as n approaches oo. Table V indicates this ratio is small even for moderate n. Also, note that significantly more functions result when an M is added to an AON gate set. Thus, the trade-off between gate complexity and the n u m b e r of functions realized seems to favor increased gate set complexity. A n interesting question, therefore, is the number of functions realized by fanout-free networks of larger gate sets.
Appendtx. Proof of Theorem 11 THEOREM 11. Let f ( X ) be realizable by a fanoutfree network of positive symmetric gates and inverters. Then f ( X ) is a threshold functzon if and only tf tt is reahzable by a cascade. PROOF. Since f ( X ) is realized by a fanout-free network N of positive symmetric gates and inverters, it is also realized by a canonical network Nc obtained from N by pushing inverters to the primary inputs (as in Lemma 2). Since the transformation from N to Nc does not alter topology, N is a cascade if and only if Nc is a cascade. Therefore, it is necessary to consider only functions realized by canonical fanout-free networks. ( i f - - b y induction on the number of gates) Consider a cascade realizable function f ( X ) . If the cascade has one gate, then it follows immediately that f ( X ) is a threshold funcUon. Now assume that all functions realized by cascades of m - 1 gates are threshold functions, w h e r e f ( X ) is realized by a cascade of m gates.f (X) has the decomposition
f ( X ) =fi, nm (g(X-- U), U), wherefim rim(g, U) is the function realized by the output gate and g(X - U) is the function r This was obtained from Hamson's [5] table for the number N(n) of monotomc functionson n, n - 1, n 2, . , and l variable
496
JON T BUTLER
realized by a cascade o f m - I gates. Thus, by assumption, g is threshold reahzable and is associated with a weight-threshold vector, say (w~, wz . . . . . Wp; T). Let W be the sum o f weights; that is, W = ~¢-1 w,, and let T' = (tin - 1) W + T. S i n c e f ( X ) is positive, w, and T a r e positive [10, p. 189]. Thus, W i s the maximum weighted sum o f g . Further, W_> T; o t h e r w i s e f ( X ) ffi 0. It follows, therefore, that (wl, w2. . . . . wp+~. . . . . wp+n -~;T'), where wp+j = W for 1 .~ j _< nm - 1, is a weight-threshold vector f o r f ( X ) . (only if) L e t f ( X ) be a threshold function, and assume, on the contrary, t h a t f ( X ) is not reahzed by a cascade. It follows, therefore, that any fanout-free network N realizing f ( X ) has at least one gate g which receives inputs from two other gates gl and g2. Further, g~ and g2 do not connect to g through inverters, since it can be assumed, without loss o f generality, that N as a canonical network. Figure 12 shows the subnetwork N~ o f N containing just g~, g2, and g. Inputs a,, b,, and e, come from other subnetworks or are primary inputs to N and q drives another subnetwork o f N or is itself the output o f N. If f ( X ) is a threshold function, the successive applications o f Theorem 9 can be used to show that q = G(A, B, C) is a threshold function also. Since the variables in A are symmetric with each other they can be associated with the same weight w3 in the threshold realization o f q = G(A, B, C). Similarly, all vanables in B and C can be associated with the same weights we and wc, respectively. Thus, q = G(A, B, C) = 1 if and only if nA
nB
nC
WA ~ a ~ + w ~ ~ b , + w c ~ c~_> T. L--1
z~l
z--1
Since gl, g2, and g are positive symmetric gates with thresholds t~, t2, and t, respectively, it follows that
T > (tl
hWA + (t -- I)Wc _> T,
(14)
t2ws +
05)
(t -
l)wc _> T,
-- I)WA -I- (/2 --
I)WB + (t -- I)Wc,
(16)
for l _< t _< nc + I. Adding (14) to (15), multiplying (16) by 2, and comparing the resulting two inequalities yields tlWA + t2WB + 2(t -- I)Wc _> 2T > 2(h - l)WA + 2(t2 -- 1)W8 + 2(t -- l)wc.
Rearranging yields (2 - tl)WA + (2 -- t2)WB > 0.
(17)
(17) is satisfied only when tl = l or t2 = l or both. The case for t = nc + 2 never occurs. That is, for t = nc + 2 (g is an A N D gate), a similar derivation shows that tl = nA (g~ is an
Af
a2 al
Bt
b2
b% C
q = G(A,B,C)
c2 CnC FIG 12 SubnetworkN~of N containingthree posRlvesymmetricgates
A n a l y s i s a n d D e s i g n o f F a n o u t - F r e e N e t w o r k s o f Positive S y m m e t r i c Gates
497
A N D gate) or t2 = nn (g2 Is an A N D gate) or both. However, this is impossible, since the output o f an A N D gate in a fanout-free network is never apphed to the input of another A N D gate. Consider the following set of inequahties, which must also hold tf q = G(A, B, C) is a threshold function. tlWA + t2wn + (t -- 2)Wc --> T,
(18)
T > nAWa + (t2 -- I)WB -t- (t -- 2 ) w e ,
(19)
T > (tl - 1)wA + nBwn + (t - 2 ) w c ,
(20)
for 2 0.
(21)
(20) tS satisfied only when tx = nA or t2 = nn or both. The case for t = 1 (g is an O R gate) is impossible, because a similar derivation shows that this imphes tl = 1 (gl is an O R gate) or t2 = 1 (g2 is an OR gate) or both. However, the interconnection of two O R gates never occurs in a fanout-free network. To satisfy both (17) and (21), either t l = 1 and
t2=nB
(22)
or
tl = h A
and
t 2 = 1.
(23)
Consider only (22); the result for (23) is analogous. Substituting (22) into (14) and (16) and comparing yields WA > (rib -- OWn.
(24)
Substituting (22) into (18) and (19) and comparing yields wn > (hA -- I)WA.
(25)
Since na >-- 2 and nn --> 2, (24) and (25) Imply the contradictory requirements WA> WB and WB > WA. Thus, q = G(A, B, C ) is not realizable and it must be that the o n g m a l assumption t h a t f ( X ) is a threshold function is correct. Q.E.D. ACKNOWLEDGMENTS. The author is indebted to Mark L. Ketelsen and Kyung-Yong Chwa for conversations which inspired topics in this paper. Also, special thanks are due Professor Ketelsen, Professor Edward Bender, and the referees for a careful review. REFERENCES 1 BANDYOPADHYAY,S, PAL, A, AND CHOUDHURY, A K Characterization of unate cascade reahzabdlty using parameters IEEE Trans Comptrs C-24 (Feb 1975), 218-219 2 BENDER, E A, AND BUTLER, J T Asymptotic approxtmanons to the number of fanout*free functions Submitted to IEEE Trans. Comptrs 3 CURTIS, H A A New Approach to the Design ofSwttchmg Czrcutts Van Nostrand, Pnnceton, N J, 1962 4 GOLOMB, S W On the classification of Boolean functions IRE Trans CIrcmt Theory CT-6, Spec Supp (May 1959), 176-186 5 HARRISON,M A Introductwn to Swltchmg and Automata Theory McGraw-Hdl, NewYork, 1965 6 HAYES,J P The fanout structure of switching functions J ACM 22, 4 (Oct 1975), 551-571 7 HAYES, J P Enumeration of fanout-free Boolean functions J ACM 23, 4 (Oct 1976), 700-709 8 KLEITMAN,D On Dedekmd's problem The number of monotone Boolean functions Proc. Amer Math Soc 21 (1969), 677-682 9 KODANDAPANI,K L, AND SETH, S C On combinational networks with restricted fanout To appear in 1EEE Trans Comptrs 10 KOHAVI,Z Switching and Finite Automata Theory McGraw-Hall, New York, 1970 11 LEwis II, P M, AND COATES, C L Threshold Logic Wiley, New York, 1967 12 MINNICK,R C A survey of mlcrocellular research J ACM 14, 2 (Aprd 1967), 203-241 13 MINNICK,R C A system of magnetic bubble logic IEEE Trans Comptrs C-24 (Feb 1975), 217-218
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JON T BUTLER
M U K H O P A D H Y A Y , A Unate cellular logic 1EEE Trans Comptrs. C-18 (Feb 1969), 114-121 15. MUROGA, S., TSUBOI, T., AND BAUGH, C Enumeration of threshold functions of eight variables. IEEE Trans. Comptrs. C-19 (Sept. 1970), 818-825. 16. SAS^O, T., AND KINOSHITA, K. On fanout-free functions and unate cascade functions (in Japanese) In Papers Tech. Group Electron Comput, lnst Electron Commun Eng Japan, Paper EC77-7, May 1977 17 YAU, S.S., AND TANO, Y S. On identification of redundancy and symmetry of swathing funcUons IEEE Trans. Comptrs C-20 (Dec 1970, 1609-1613. 14
RECEIVED MARCH
1977,
REVISED SEPTEMBER 1977
Journal of the Assoclauon for Computing Machinery, Vol 25, No 3, July 1978
