Automatic Constraint Transformation with Integrated Parameter Space ...
Automatic Constraint Transformation with Integrated Parameter Space Exploration in Analog System Synthesis Nagu R. Dhanwada, Adrian Nunez-Aldana and Ranga Vemuri y Laboratory for Digital Design Environments Department of ECECS, University of Cincinnati Cincinnati, OH 45221{0030
Abstract
In this paper, we present a constraint transformation and topology selection methodology that explores the system level parameter space to compute acceptable regions in the component parameter space. The search process of an underlying circuit synthesis tool could be con ned to these regions of valid solutions. Experimental results showing the impact of parameter space exploration at a higher level on analog circuit synthesis are presented, demonstrating the e ectiveness of this technique.
1 Introduction
Crucial to a top-down analog design process [10] is an interfacing mechanism to communicate the speci cations and constraints on the design elements used at one level with those at the next level. The task of transforming the high-level speci cations onto module parameters is called Constraint Transformation [3]. Ecient automation of this task is one of the the most important steps in automating the design of analog and mixed analog-digital systems. There are two important aspects to this problem: Constraint Model Generation, which is the task of generating a model that relates the design/performance parameters at the di erent levels, and Constraint Allocation, where actual values are assigned to the parameters. Most of the existing methods [3, 7, 6, 9] address either model generation or allocation. To the best of our knowledge none of them take into account the problem of parameter space exploration. All these approaches attempt to nd point values (not ranges) for the design parameters which is equivalent to computing a single point in the parameter space of the system that meets the constraints. We present the constraint transformation method in the context of an overall analog synthesis
ow consisting of the constraint transformation step followed by the circuit and layout synthesis. The circuit synthesis tool sizes the components to meet the constraints. The task of the circuit synthesis tool can be seen as one of, searching the vast parameter space of the circuit to nd a point that meets the constraints. In this paper, we present a method for performing automatic constraint transformation, with system level parameter space exploration to nd component design parameter ranges. This amounts to nding This work is sponsored by USAF, Air Force Research Laboratory, WPAFB under contract number F33615-96-C-1911 y Author for Correspondence,[email protected]
constraint satisfying regions in the system parameter space, thus providing exibility to the underlying circuit synthesis tool in nding a sizing solution that satis es the constraints. By performing such a system level exploration, we prune the vast search space of the circuit synthesis tool. Our method consists of an interval genetic algorithm IGA interacting with an analog performance estimator APE, that is capable of producing approximate sizing solutions. These sizing solutions constitute a valid solution space within which the circuit synthesis tool can conduct it's search. We present experimental evidence showing the impact of pruning the search space of the circuit synthesis tool. The pruning technique could be used with any optimization based circuit synthesis tool. We have used ASTRX/OBLX [8] to demonstrate this technique. This constraint transformation method forms a part of the VASE (VHDL-AMS Synthesis Environment) [13], mixed-signal synthesis system being developed at the University of Cincinnati.
2 Motivation
The parameter space is de ned to be the space having as many dimensions as the number of design parameters, and in which each point represents a single circuit having those design parameter values [4]. Design parameter ranges de ne, not a point, but a region in the parameter space. The system performance speci cations are provided by means of upper and lower bounds of acceptability on system performance, and the space in which these speci cations are represented is called the performance space. Constraint transformation can be abstractly described as the task of mapping speci cations given in the performance space onto the parameter space. Such a mapping from the performance space to the parameter space can be achieved by a search process. The output parameter space of the constraint transformation step becomes the constraint space of the circuit synthesis tool, because it has to come up with a sizing solution that meets the design constraints imposed by the constraint transformation step. The constraint space can be de ned to be the space comprising of both design and performance constraints. So, if the constraint transformation process computes a point in the design parameter space then the task of the circuit synthesis tool is made even more dicult because it has to search in it's vast parameter space for a solution that is exactly equivalent to this point in it's constraint
space. On the other hand if the constraint transformation method computes ranges for the design parameters, then the result of constraint transformation is a region. If such regions are produced by the constraint transformation process, then the circuit synthesis tool has some
exibility in it's search for a sizing solution. Since we know the acceptable region in the input space of the circuit synthesis tool (by virtue of exploring the parameter space at the system-level) within which the sizing solution should lie, this information could be used to prune the search space of the circuit synthesis tool e ectively. In our approach, during parameter space exploration, the performance estimator generates approximate sizing solutions, and all these solutions that correspond to the acceptable region in the parameter space are used to bound the search space of the circuit synthesis tool.
3 A Real Coded Genetic Algorithm for Constraint Transformation Genetic Algorithms (GAs) are stochastic search techniques based on the mechanism of natural selection and natural genetics[1]. In this section we present a genetic algorithm that produces point values for the design parameters. This enables the reader to get an overall view of how constraint transformation is done using genetic algorithms.
3.1 Encoding Scheme
The solution is encoded as an array of real numbers, hence the name Real-Coded Genetic Algorithm. The solution representation has two parts, the rst part representing the values to be assumed by the design parameters of the components constituting the system, and the second part represents topology information. Each value in the topology part of the representation indicates the type of topology to be selected from the set of alternatives provided in the library. Each component can have more than one entry in the topology part of the array if that component has sub-components having di erent topologies.
3.2 Cost Function Evaluation
We present the method used to evaluate the cost of a solution by rst describing the structure of the Analog Performance Estimator (APE) [5] which is used in the evaluation process. The Analog Performance Estimator : The analog performance estimator accepts design parameters (Bias current etc) of an analog circuit and determines it's performance parameters (area, UGF, slew rate, etc) along with the anticipated sizes of the circuit elements. The APE is structured hierarchically and contains symbolic performance equations of analog circuits at various levels of abstraction. The di erent levels in the APE are the following: CMOS transistor level : is the lowest level in the hierarchy of APE. The transistor is sized based on its DC operating point and the fabrication process parameters and the small signal characteristics are evaluated. Basic Circuit Level : This level has DC-bias voltages, current sources, gain ampli ers, output bu ers, di erential ampli ers.
Operational Ampli ers : This consists of op amp topologies. Each op amp stage is composed of basic circuit elements. Analog Module Level : This library of analog modules forms the fourth level in the APE. Each of the modules are built using the operational ampli ers, basic circuit elements, transistors, resistors and capacitors. This level consists of elements like ampli ers, adders, converters, etc. At the cascaded component level the APE estimates the performance of system of cascaded blocks, given the performances of the individual blocks. APE uses technology process parameters, SPICE models and performance composition equations for determining circuit performance at di erent levels of abstraction. The APE also has built into it some rules that detect the cases where transistors in the design go into saturation, or when some basic conditions governing the functionality of the circuit have been violated. The cost function evaluation is a two step process. This consists of invoking the APE rst at the component level to calculate the performances of the individual modules, and next at the cascaded component level to compute the system performance. Cost Function : The cost function is N 1 X
N
i=1
i i
W :F
where N represents the number of speci cations, i is the weight associated with that performance speci cation and i is de ned as: 0 i est i constraint = W
F
i
F
if P
Pi est ?Pi constraint Pi constraint
satisf ies P
otherwise
i est is the value for the performance parameter in the current solution, and i constraint is the user speci ed constraint on that performance parameter. Such a cost function is typical of GAs that handle multiple constraints. The GA works towards minimizing the cost function. During the evolution process, there might be infeasible solutions generated. i.e the design parameters might be assigned values that might lead to a circuit that does not work. Such conditions are detected during performance estimation of the individual components, and the resulting infeasible solutions are removed from the current population by imposing a heavy penalty on them. Non-uniform mutation, uniform crossover and uniform selection operators were used in the RCGA [2].
P
P
3.3 Some Constraint Transformation Experiments with the RCGA
In this section we present the results of some experiments conducted using RCGA and ASTRX/OBLX. The inputs to ASTRX/OBLX consists of: (a) Set of circuit topologies (b) User-speci ed variables, that correspond to the transistor sizes and bias points. A range is speci ed on each of these variables. The range of values these variables can assume gives the size of the parameter space. Usually the user is expected to give a
Name
Circuit Description 3 stage opamp (wilson source, CMOS gain stage, o/p buffer)
User Specification area 3000sq power 8mW gain 150 ugf 10Mhz
ckt2
2 stage opamp (curr mirror, CMOS gain stage)
area 2000sq power 5mW gain 75 ugf 5Mhz
ckt3
3 stage opamp (curr mirror, CMOS gain stage, o/p buffer)
area 4000sq power 6mW gain 100 ugf 8Mhz
ckt4
Non Inv Amplifier
ckt5
Cascaded Amplifiers
area 8000 sq gain 10 power 6mW BW 300Khz SR 1V/s area 18000 sq gain 15 power 12mW BW 400Khz SR 0.5V/s
ckt1
Constraints Generated by RCGA Ibias=2.8A gain = 788 power = 2mW area=800sq ugf = 20Mhz Zout = 1757.6 Ibias=5.8A gain = 611 power = 4mW area=1500sq ugf = 21.7Mhz Zout = 643 Ibias=3.3A gain = 988 power = 2mW area=1225sq ugf = 20.6Mhz Zout = 1129.64 Res1 = 498
Rf = 15351
DCgain = 80 BW = 380Khz SR = 1.2V/s Res1 = 3000
Rf = 12000
DCgain = 80 BW = 580Khz SR = 0.9V/s
Table 1: Circuit description and constraints wide range, because there is no prior knowledge about where in the parameter space the feasible sizing solution lies. A sanity value could be speci ed for each of the variables as the starting point from where the search could proceed. Pruning the parameter space of the circuit synthesis tool corresponds to setting the reduced ranges for these variables. (c) bias circuits (d) Set of AWE circuits, (e) Objective/Constraint functions, Each user performance speci cation given can be an objective or a constraint. Each speci cation needs to have a good and a bad value, which are used to indicate the direction in which the optimization should proceed. ASTRX/OBLX requires ranges to be provided for each of the constraints. It is not enough if the constraint transformation step produces point values. Also in our case the set of point values for the design parameters does not allow us to bound the search space of the circuit synthesis tool. At best what we can do is to provide a starting solution for the circuit synthesis task using the set of design parameters and the approximate sizing solution produced by the RCGA. Table 1 shows a description of the circuit along with the user imposed constraints and the ones generated by the RCGA. The user speci cations shown in column 3 of Table 1 and the circuit are taken as input by the constraint transformation GA. The constraints generated by the GA are given as speci cations to the circuit synthesis tool. The sizing solution that was generated during the constraint transformation process is used to set the sanity points for the circuit synthesis tool. For ckt4, the non inverting ampli er the constraints for the opamp are generated by the GA along with a sizing solution. For ckts 1-3, design parameters for the opamps that meet the user given performance speci cations were generated by the GA. Table 2 shows the ranges on Ws and Ls of the transistors for each of the circuits along with the starting point generated by the RCGA and the performance of the circuit after taking it through the synthesis process with these values. The number of W and L entries do not indicate the number of transistors. A single variable can represent the W/L of more than one transistor in the case of transistors being matched. In all the cases it was found that the
Design Name ckt1
Search space for circuit synthesis() W1=L1=(0.6,500) W2=L2=(0.6,500) W3=L3=(0.6,500) W4=L4=(0.6,500) W5=L5=(0.6,500) W6=L9=(0.6,500) W7=(0.6,2000) W8=L8=(0.6,500) W1=L1=(0.6,500) W2=L2=(0.6,500) W4=L4=(0.6,500) W5=L5=(0.6,500) W6=(0.6,500) W1=L1=(0.6,500) W2=L2=(0.6,500) W4=L4=(0.6,500) W5=L5=(0.6,500) W6=W7=(0.6,500) W8=L8=(0.6,500) W1=L1=(0.6,500) W2=L2=(0.6,500) W4=L4=(0.6,500) W5=L5=(0.6,500) W6=(0.6,500) R1=(10,5000) Rfd=(10,50000) W1=L1=(0.6,500) W2=L2=(0.6,500) W4=(0.6,5000) L4=(0.6,500) W5=L5=(0.6,500) W6=(0.6,500) R1=(10,5000) Rfd=(10,50000)
ckt2 ckt3 ckt4
ckt5
Sizing soln generated by RCGA() W1=3,L1=1 W2=1,L2=65 W3=8.5,L3=1 W4=1.5,L4=1 W5=3,L5=1 W6=40,L9=1 W7=320 W8=32,L8=20 W1=5,L1=1 W2=1,L2=83 W4=6,L4=2 W5=7.5,L5=1 W6=125 W1=2.4,L1=1 W2=1,L2=154 W4=8.5,L4=1 W5=1.5,L5=1 W6=3,W7=1 W8=40,L8=1 W1=5,L1=1 W2=1,L2=83 W4=6,L4=2 W5=7.5,L5=1 W6=125 R1=498 Rfd=15351 W1=2,L1=1 W2=1,L2=83 W4=1200 L4=2 W5=8,L5=1 W6=125 R1=3000 Rfd=10000
performance after synthesis area=8.48 sq power=2.5mW gain=1.6 ugf= ? area=4.08sq power=2.1mW ugf= ? gain=1.2 area=8.48 sq power=2.5mW gain=1.6 ugf= ? area = 4.08sq power=3.1mW ugf=? gain < 1 area = 8.16sq power=6.1mW ugf= ? gain < 1
Table 2: Circuit Synthesis Results for RCGA Center Delta (0 - 1)
A.1
A.2
A.3
B.1
B.2
C.1
C.2
D.1
D.2
A.t1 A.t2 B.t1 B.t2 C.t1 D.t1
∆A.1 ∆A.2 ∆A.3 ∆ B.1 ∆B.2 ∆C.1 ∆C.2 ∆D.1 ∆D.2 − Design Parameters
−
−
−
−
−
Topology Information
Upper Bound of the Interval - [Center + Delta * Center] Lower Bound of the Interval - [Center - Delta * Center]
Figure 1: Solution Representation for the IGA circuit synthesis tool produced a circuit that had a very low value of gain. These tests show that there are cases where the circuit synthesis tool was unable to come up with a working solution because of the vastness of it's search space. This might mean that reducing the ranges of the independent variables would help the circuit synthesis tool in it's search. In general, such a reduced space would greatly bene t a random exploration based search method like simulated annealing [12] that forms the optimization engine in ASTRX/OBLX. Later in the paper we present results which show that by reducing the search space of the circuit synthesis tool we are able to guide it towards a constraint satisfying solution. The RCGA is not adequate to reduce ranges of the independent variables so that the search space of the circuit synthesis tool could be pruned.
4 An Interval Genetic Algorithm for Parameter Space Exploration
The GA for constraint transformation accepts a system level net-list along with the constraints, and computes intervals for the component design parameters along with their topologies. The rst step in the GA is to suitably encode the solution representation. This is followed by the steps of selection, crossover, mutation and replacement are repeated till convergence is reached.
4.1 Solution Representation
Figure 1 shows the solution representation for the Interval Genetic Algorithm (IGA). It is a two dimensional array of real numbers. The rst row represents the center of the interval, and the second row is a delta value, which
lies between 0 and 1. The upper and lower bound of the interval are calculated as shown in Figure 1. These are calculated for every design parameter in the solution. A set of point values for the design parameters constitute a point in the region de ned by the design parameter intervals. Thus, moving from one point to an other in this region of points requires us to de ne a step size, with which the design parameters would be incremented from their lower bound to the upper bound. These step sizes are calculated for each design parameter in the solution, based on the width of the interval. The smaller the step size, more would be the number of points in the region represented by the design parameter intervals. The step size in the IGA is set to about ve percent of the width of the interval.
4.2 Cost Function Evaluation
Each solution represents a set of points, forming a region in the component parameter space. If all the points in the solution are constraint satisfying, then the entire solution is a constraint satisfying one having a cost function value of zero. The evaluation of the solution quality is done using a two-level cost function. The Cost Function : It consists of a local part and a global one, which are shown below. Local Cost function This one is exactly the same as the cost function used in the RCGA. Global Cost function which is de ned as follows: N 1 X () i=1 where N, denotes the number of points in the region. This global cost function returns a value of zero only if all the points in the region represented by the solution are constraint satisfying. Non-uniform mutation and uniform crossover operators were suitably extended.A uniform selection scheme was employed. The probabilities of crossover and mutation used were 0.9, 0.1 and the population size was 1000. The IGA was implemented in C++ and it uses the GALIB genetic algorithm package [11].
N
local obj f n i
5 Experimentation
The IGA was run for the circuits and the constraints shown in Table 1. The ranges on the design/performance parameters computed by the IGA were used. Table 3 shows the pruned space generated by the IGA and the performance of the circuit produced by the circuit synthesis tool using this pruned space. The measurement of the results were made using HSPICE with SPICE level 1 models and process parameters from run N58A of HP 0.8 process from MOSIS. We see in Table 3 that the performance of circuits 1, 2, 4 and 5 satisfy the user speci ed constraints. Recall that earlier when we did not provide a pruned space for the circuit synthesis tool, it came up with a circuit that had a very low value of gain. In the case of circuit 3, we gave the ranges for variables, that were obtained from a solution given by the IGA that had a high cost function value. This means that this solution is not a constraint satisfying one, for all the other cases the reduced ranges for variables was produced from a solution given by the IGA that had an cost function value
Design name ckt1
ckt2 ckt3 ckt4
ckt5
Pruned space generated by IGA W1=(2,5),L1=(0.6,2) W2=(0.6,2),L2=(40,100) W3=(5,12),L3=(0.6,2) W4=(1,3),L4=(0.6,2) W5=(2,6),L5=(0.6,2) W6=(60,120),L9=(0.6,2) W7=(200,500) W8=(20,44),L8=(10,30) W1=(3,7),L1=(0.6,3) W2=(0.6,3),L2=(60,100) W4=(1,10),L4=(0.6,3) W5=(6,12),L5=(0.6,3) W6=(100,145) W1=(2,4),L1=(0.6,3) W2=(0.6,3),L2=(137,172) W4=(1,7),L4=(1,6) W5=(3,5),L5=(0.6,3) W6=(29,53),W7=(438,1039) W8=(26,36),L8=(12,18) W1=(1,8),L1=(0.6,2) W2=(0.6,2),L2=(70,300) W4=(6,20) L4=(0.6,2) W5=(2,12),L5=(0.6,2) W6=(120,160) R1=(498,800) Rfd=(10000,30000) W1=(1,8),L1=(0.6,2) W2=(0.6,2),L2=(70,300) W4=(1200,5000) L4=(0.6,2) W5=(2,10),L5=(0.6,2) W6=(120,160) R1=(2000,5000) Rfd=(8000,40000)
Performance after synthesis area = 324 sq power = 1.67mW gain = 170 UGF = 18Mhz area = 149 sq power = 1.824mW gain = 80 UGF = 20Mhz power = 3.71mW gain < 5 area = 6710 sq power = 1.95 mW gain = 25 BW = 400Khz SR = 11V/s area = 11992 sq power = 7.11 mW BW = 503Khz gain = 20 SR = 12.5V/s
Table 3: Circuit synthesis results for IGA of zero. It is possible that the IGA might not come up with solutions having a cost of zero, for very tight set of constraints, in which cases care should be exercised in setting the ranges for the variables in circuit synthesis.
6 Conclusion
An automatic constraint transformation methodology was presented. The idea of parameter space exploration during constraint transformation was introduced and it's use in pruning the search space of a circuit synthesis tool was presented. Experimental results to show the e ect of parameter space exploration were provided using the ASTRX/OBLX circuit synthesis tool. An Interval Genetic Algorithm that interacts with a performance estimator was presented to perform this task of constraint transformation.
References [1] M. Gen and R. Cheng, \Genetic Algorithms and Engineering De-
sign", John Wiley & Sons, 1997. [2] F. Herrera, M.Lozano, J.L. Verdegay, \Tackling Real-Coded Genetic Algorithms : Operators and Tools for Behavioural Analysis", Tech Report DECSAI - 95107, February 1995. [3] B.G. Arsintescu et al, \General AC Constraint Transformation for Analog ICs", Proc 35th Design Automation Conference 1998. [4] R. Spence and R.S. Soin, \Tolerance Design of Electronic Circuits",Addison-Wesley Publishing Co., 1988. [5] A. Nunez and R. Vemuri, \Performance Estimation for CMOS Analog Circuit Synthesis", Submitted for ICCD'98. [6] W. Kruiskamp and D. Leenaerts," DARWIN : Analogue Circuit Synthesis based on Genetic Algorithms", International Journal of Circuit Theory and Applications, Vol 23, pp. 285-296, 1995. [7] P.C. Maulik, L.R. Carley, and R.A. Rutenbar, \A Mixed-Integer Non-linear programming approach to analog circuit synthesis", Proc 29th Design Automation Conference, 1992. [8] E.S.Ochotta, \Synthesis of High Performance Analog Cells in ASTRX/OBLX", Ph.D Dissertation, Feb 1994, CMU. [9] N.R. Dhanwada and R. Vemuri, \ Constraint Allocation in Analog System Synthesis", International Conference on VLSI Design 1998. [10] H. Chang et al, \A Top-down Constraint Driven Methodology for Analog Integrated Circuits", Kluwer Academic, 1997. [11] M. Wall, \GAlib: A C++ Library of Genetic Algorithm Components". [12] S. Kirkpatrick, C.D. Gelatt and M.P. Vecchi, \Optimization by Simulated Annealing", Science,220(4598), November 1983. [13] R. Vemuri, N.R. Dhanwada, A. Nunez, P. Campisi, \VASE: VHDL-AMS Synthesis Environment - Tools for Synthesis of MixedSignal Systems from VHDL-AMS", Proc Analog and Mixed-Signal Applications Conference, July 1997.
Abstract
In this paper, we present a constraint transformation and topology selection methodology that explores the system level parameter space to compute acceptable regions in the component parameter space. The search process of an underlying circuit synthesis tool could be con ned to these regions of valid solutions. Experimental results showing the impact of parameter space exploration at a higher level on analog circuit synthesis are presented, demonstrating the e ectiveness of this technique.
1 Introduction
Crucial to a top-down analog design process [10] is an interfacing mechanism to communicate the speci cations and constraints on the design elements used at one level with those at the next level. The task of transforming the high-level speci cations onto module parameters is called Constraint Transformation [3]. Ecient automation of this task is one of the the most important steps in automating the design of analog and mixed analog-digital systems. There are two important aspects to this problem: Constraint Model Generation, which is the task of generating a model that relates the design/performance parameters at the di erent levels, and Constraint Allocation, where actual values are assigned to the parameters. Most of the existing methods [3, 7, 6, 9] address either model generation or allocation. To the best of our knowledge none of them take into account the problem of parameter space exploration. All these approaches attempt to nd point values (not ranges) for the design parameters which is equivalent to computing a single point in the parameter space of the system that meets the constraints. We present the constraint transformation method in the context of an overall analog synthesis
ow consisting of the constraint transformation step followed by the circuit and layout synthesis. The circuit synthesis tool sizes the components to meet the constraints. The task of the circuit synthesis tool can be seen as one of, searching the vast parameter space of the circuit to nd a point that meets the constraints. In this paper, we present a method for performing automatic constraint transformation, with system level parameter space exploration to nd component design parameter ranges. This amounts to nding This work is sponsored by USAF, Air Force Research Laboratory, WPAFB under contract number F33615-96-C-1911 y Author for Correspondence,[email protected]
constraint satisfying regions in the system parameter space, thus providing exibility to the underlying circuit synthesis tool in nding a sizing solution that satis es the constraints. By performing such a system level exploration, we prune the vast search space of the circuit synthesis tool. Our method consists of an interval genetic algorithm IGA interacting with an analog performance estimator APE, that is capable of producing approximate sizing solutions. These sizing solutions constitute a valid solution space within which the circuit synthesis tool can conduct it's search. We present experimental evidence showing the impact of pruning the search space of the circuit synthesis tool. The pruning technique could be used with any optimization based circuit synthesis tool. We have used ASTRX/OBLX [8] to demonstrate this technique. This constraint transformation method forms a part of the VASE (VHDL-AMS Synthesis Environment) [13], mixed-signal synthesis system being developed at the University of Cincinnati.
2 Motivation
The parameter space is de ned to be the space having as many dimensions as the number of design parameters, and in which each point represents a single circuit having those design parameter values [4]. Design parameter ranges de ne, not a point, but a region in the parameter space. The system performance speci cations are provided by means of upper and lower bounds of acceptability on system performance, and the space in which these speci cations are represented is called the performance space. Constraint transformation can be abstractly described as the task of mapping speci cations given in the performance space onto the parameter space. Such a mapping from the performance space to the parameter space can be achieved by a search process. The output parameter space of the constraint transformation step becomes the constraint space of the circuit synthesis tool, because it has to come up with a sizing solution that meets the design constraints imposed by the constraint transformation step. The constraint space can be de ned to be the space comprising of both design and performance constraints. So, if the constraint transformation process computes a point in the design parameter space then the task of the circuit synthesis tool is made even more dicult because it has to search in it's vast parameter space for a solution that is exactly equivalent to this point in it's constraint
space. On the other hand if the constraint transformation method computes ranges for the design parameters, then the result of constraint transformation is a region. If such regions are produced by the constraint transformation process, then the circuit synthesis tool has some
exibility in it's search for a sizing solution. Since we know the acceptable region in the input space of the circuit synthesis tool (by virtue of exploring the parameter space at the system-level) within which the sizing solution should lie, this information could be used to prune the search space of the circuit synthesis tool e ectively. In our approach, during parameter space exploration, the performance estimator generates approximate sizing solutions, and all these solutions that correspond to the acceptable region in the parameter space are used to bound the search space of the circuit synthesis tool.
3 A Real Coded Genetic Algorithm for Constraint Transformation Genetic Algorithms (GAs) are stochastic search techniques based on the mechanism of natural selection and natural genetics[1]. In this section we present a genetic algorithm that produces point values for the design parameters. This enables the reader to get an overall view of how constraint transformation is done using genetic algorithms.
3.1 Encoding Scheme
The solution is encoded as an array of real numbers, hence the name Real-Coded Genetic Algorithm. The solution representation has two parts, the rst part representing the values to be assumed by the design parameters of the components constituting the system, and the second part represents topology information. Each value in the topology part of the representation indicates the type of topology to be selected from the set of alternatives provided in the library. Each component can have more than one entry in the topology part of the array if that component has sub-components having di erent topologies.
3.2 Cost Function Evaluation
We present the method used to evaluate the cost of a solution by rst describing the structure of the Analog Performance Estimator (APE) [5] which is used in the evaluation process. The Analog Performance Estimator : The analog performance estimator accepts design parameters (Bias current etc) of an analog circuit and determines it's performance parameters (area, UGF, slew rate, etc) along with the anticipated sizes of the circuit elements. The APE is structured hierarchically and contains symbolic performance equations of analog circuits at various levels of abstraction. The di erent levels in the APE are the following: CMOS transistor level : is the lowest level in the hierarchy of APE. The transistor is sized based on its DC operating point and the fabrication process parameters and the small signal characteristics are evaluated. Basic Circuit Level : This level has DC-bias voltages, current sources, gain ampli ers, output bu ers, di erential ampli ers.
Operational Ampli ers : This consists of op amp topologies. Each op amp stage is composed of basic circuit elements. Analog Module Level : This library of analog modules forms the fourth level in the APE. Each of the modules are built using the operational ampli ers, basic circuit elements, transistors, resistors and capacitors. This level consists of elements like ampli ers, adders, converters, etc. At the cascaded component level the APE estimates the performance of system of cascaded blocks, given the performances of the individual blocks. APE uses technology process parameters, SPICE models and performance composition equations for determining circuit performance at di erent levels of abstraction. The APE also has built into it some rules that detect the cases where transistors in the design go into saturation, or when some basic conditions governing the functionality of the circuit have been violated. The cost function evaluation is a two step process. This consists of invoking the APE rst at the component level to calculate the performances of the individual modules, and next at the cascaded component level to compute the system performance. Cost Function : The cost function is N 1 X
N
i=1
i i
W :F
where N represents the number of speci cations, i is the weight associated with that performance speci cation and i is de ned as: 0 i est i constraint = W
F
i
F
if P
Pi est ?Pi constraint Pi constraint
satisf ies P
otherwise
i est is the value for the performance parameter in the current solution, and i constraint is the user speci ed constraint on that performance parameter. Such a cost function is typical of GAs that handle multiple constraints. The GA works towards minimizing the cost function. During the evolution process, there might be infeasible solutions generated. i.e the design parameters might be assigned values that might lead to a circuit that does not work. Such conditions are detected during performance estimation of the individual components, and the resulting infeasible solutions are removed from the current population by imposing a heavy penalty on them. Non-uniform mutation, uniform crossover and uniform selection operators were used in the RCGA [2].
P
P
3.3 Some Constraint Transformation Experiments with the RCGA
In this section we present the results of some experiments conducted using RCGA and ASTRX/OBLX. The inputs to ASTRX/OBLX consists of: (a) Set of circuit topologies (b) User-speci ed variables, that correspond to the transistor sizes and bias points. A range is speci ed on each of these variables. The range of values these variables can assume gives the size of the parameter space. Usually the user is expected to give a
Name
Circuit Description 3 stage opamp (wilson source, CMOS gain stage, o/p buffer)
User Specification area 3000sq power 8mW gain 150 ugf 10Mhz
ckt2
2 stage opamp (curr mirror, CMOS gain stage)
area 2000sq power 5mW gain 75 ugf 5Mhz
ckt3
3 stage opamp (curr mirror, CMOS gain stage, o/p buffer)
area 4000sq power 6mW gain 100 ugf 8Mhz
ckt4
Non Inv Amplifier
ckt5
Cascaded Amplifiers
area 8000 sq gain 10 power 6mW BW 300Khz SR 1V/s area 18000 sq gain 15 power 12mW BW 400Khz SR 0.5V/s
ckt1
Constraints Generated by RCGA Ibias=2.8A gain = 788 power = 2mW area=800sq ugf = 20Mhz Zout = 1757.6 Ibias=5.8A gain = 611 power = 4mW area=1500sq ugf = 21.7Mhz Zout = 643 Ibias=3.3A gain = 988 power = 2mW area=1225sq ugf = 20.6Mhz Zout = 1129.64 Res1 = 498
Rf = 15351
DCgain = 80 BW = 380Khz SR = 1.2V/s Res1 = 3000
Rf = 12000
DCgain = 80 BW = 580Khz SR = 0.9V/s
Table 1: Circuit description and constraints wide range, because there is no prior knowledge about where in the parameter space the feasible sizing solution lies. A sanity value could be speci ed for each of the variables as the starting point from where the search could proceed. Pruning the parameter space of the circuit synthesis tool corresponds to setting the reduced ranges for these variables. (c) bias circuits (d) Set of AWE circuits, (e) Objective/Constraint functions, Each user performance speci cation given can be an objective or a constraint. Each speci cation needs to have a good and a bad value, which are used to indicate the direction in which the optimization should proceed. ASTRX/OBLX requires ranges to be provided for each of the constraints. It is not enough if the constraint transformation step produces point values. Also in our case the set of point values for the design parameters does not allow us to bound the search space of the circuit synthesis tool. At best what we can do is to provide a starting solution for the circuit synthesis task using the set of design parameters and the approximate sizing solution produced by the RCGA. Table 1 shows a description of the circuit along with the user imposed constraints and the ones generated by the RCGA. The user speci cations shown in column 3 of Table 1 and the circuit are taken as input by the constraint transformation GA. The constraints generated by the GA are given as speci cations to the circuit synthesis tool. The sizing solution that was generated during the constraint transformation process is used to set the sanity points for the circuit synthesis tool. For ckt4, the non inverting ampli er the constraints for the opamp are generated by the GA along with a sizing solution. For ckts 1-3, design parameters for the opamps that meet the user given performance speci cations were generated by the GA. Table 2 shows the ranges on Ws and Ls of the transistors for each of the circuits along with the starting point generated by the RCGA and the performance of the circuit after taking it through the synthesis process with these values. The number of W and L entries do not indicate the number of transistors. A single variable can represent the W/L of more than one transistor in the case of transistors being matched. In all the cases it was found that the
Design Name ckt1
Search space for circuit synthesis() W1=L1=(0.6,500) W2=L2=(0.6,500) W3=L3=(0.6,500) W4=L4=(0.6,500) W5=L5=(0.6,500) W6=L9=(0.6,500) W7=(0.6,2000) W8=L8=(0.6,500) W1=L1=(0.6,500) W2=L2=(0.6,500) W4=L4=(0.6,500) W5=L5=(0.6,500) W6=(0.6,500) W1=L1=(0.6,500) W2=L2=(0.6,500) W4=L4=(0.6,500) W5=L5=(0.6,500) W6=W7=(0.6,500) W8=L8=(0.6,500) W1=L1=(0.6,500) W2=L2=(0.6,500) W4=L4=(0.6,500) W5=L5=(0.6,500) W6=(0.6,500) R1=(10,5000) Rfd=(10,50000) W1=L1=(0.6,500) W2=L2=(0.6,500) W4=(0.6,5000) L4=(0.6,500) W5=L5=(0.6,500) W6=(0.6,500) R1=(10,5000) Rfd=(10,50000)
ckt2 ckt3 ckt4
ckt5
Sizing soln generated by RCGA() W1=3,L1=1 W2=1,L2=65 W3=8.5,L3=1 W4=1.5,L4=1 W5=3,L5=1 W6=40,L9=1 W7=320 W8=32,L8=20 W1=5,L1=1 W2=1,L2=83 W4=6,L4=2 W5=7.5,L5=1 W6=125 W1=2.4,L1=1 W2=1,L2=154 W4=8.5,L4=1 W5=1.5,L5=1 W6=3,W7=1 W8=40,L8=1 W1=5,L1=1 W2=1,L2=83 W4=6,L4=2 W5=7.5,L5=1 W6=125 R1=498 Rfd=15351 W1=2,L1=1 W2=1,L2=83 W4=1200 L4=2 W5=8,L5=1 W6=125 R1=3000 Rfd=10000
performance after synthesis area=8.48 sq power=2.5mW gain=1.6 ugf= ? area=4.08sq power=2.1mW ugf= ? gain=1.2 area=8.48 sq power=2.5mW gain=1.6 ugf= ? area = 4.08sq power=3.1mW ugf=? gain < 1 area = 8.16sq power=6.1mW ugf= ? gain < 1
Table 2: Circuit Synthesis Results for RCGA Center Delta (0 - 1)
A.1
A.2
A.3
B.1
B.2
C.1
C.2
D.1
D.2
A.t1 A.t2 B.t1 B.t2 C.t1 D.t1
∆A.1 ∆A.2 ∆A.3 ∆ B.1 ∆B.2 ∆C.1 ∆C.2 ∆D.1 ∆D.2 − Design Parameters
−
−
−
−
−
Topology Information
Upper Bound of the Interval - [Center + Delta * Center] Lower Bound of the Interval - [Center - Delta * Center]
Figure 1: Solution Representation for the IGA circuit synthesis tool produced a circuit that had a very low value of gain. These tests show that there are cases where the circuit synthesis tool was unable to come up with a working solution because of the vastness of it's search space. This might mean that reducing the ranges of the independent variables would help the circuit synthesis tool in it's search. In general, such a reduced space would greatly bene t a random exploration based search method like simulated annealing [12] that forms the optimization engine in ASTRX/OBLX. Later in the paper we present results which show that by reducing the search space of the circuit synthesis tool we are able to guide it towards a constraint satisfying solution. The RCGA is not adequate to reduce ranges of the independent variables so that the search space of the circuit synthesis tool could be pruned.
4 An Interval Genetic Algorithm for Parameter Space Exploration
The GA for constraint transformation accepts a system level net-list along with the constraints, and computes intervals for the component design parameters along with their topologies. The rst step in the GA is to suitably encode the solution representation. This is followed by the steps of selection, crossover, mutation and replacement are repeated till convergence is reached.
4.1 Solution Representation
Figure 1 shows the solution representation for the Interval Genetic Algorithm (IGA). It is a two dimensional array of real numbers. The rst row represents the center of the interval, and the second row is a delta value, which
lies between 0 and 1. The upper and lower bound of the interval are calculated as shown in Figure 1. These are calculated for every design parameter in the solution. A set of point values for the design parameters constitute a point in the region de ned by the design parameter intervals. Thus, moving from one point to an other in this region of points requires us to de ne a step size, with which the design parameters would be incremented from their lower bound to the upper bound. These step sizes are calculated for each design parameter in the solution, based on the width of the interval. The smaller the step size, more would be the number of points in the region represented by the design parameter intervals. The step size in the IGA is set to about ve percent of the width of the interval.
4.2 Cost Function Evaluation
Each solution represents a set of points, forming a region in the component parameter space. If all the points in the solution are constraint satisfying, then the entire solution is a constraint satisfying one having a cost function value of zero. The evaluation of the solution quality is done using a two-level cost function. The Cost Function : It consists of a local part and a global one, which are shown below. Local Cost function This one is exactly the same as the cost function used in the RCGA. Global Cost function which is de ned as follows: N 1 X () i=1 where N, denotes the number of points in the region. This global cost function returns a value of zero only if all the points in the region represented by the solution are constraint satisfying. Non-uniform mutation and uniform crossover operators were suitably extended.A uniform selection scheme was employed. The probabilities of crossover and mutation used were 0.9, 0.1 and the population size was 1000. The IGA was implemented in C++ and it uses the GALIB genetic algorithm package [11].
N
local obj f n i
5 Experimentation
The IGA was run for the circuits and the constraints shown in Table 1. The ranges on the design/performance parameters computed by the IGA were used. Table 3 shows the pruned space generated by the IGA and the performance of the circuit produced by the circuit synthesis tool using this pruned space. The measurement of the results were made using HSPICE with SPICE level 1 models and process parameters from run N58A of HP 0.8 process from MOSIS. We see in Table 3 that the performance of circuits 1, 2, 4 and 5 satisfy the user speci ed constraints. Recall that earlier when we did not provide a pruned space for the circuit synthesis tool, it came up with a circuit that had a very low value of gain. In the case of circuit 3, we gave the ranges for variables, that were obtained from a solution given by the IGA that had a high cost function value. This means that this solution is not a constraint satisfying one, for all the other cases the reduced ranges for variables was produced from a solution given by the IGA that had an cost function value
Design name ckt1
ckt2 ckt3 ckt4
ckt5
Pruned space generated by IGA W1=(2,5),L1=(0.6,2) W2=(0.6,2),L2=(40,100) W3=(5,12),L3=(0.6,2) W4=(1,3),L4=(0.6,2) W5=(2,6),L5=(0.6,2) W6=(60,120),L9=(0.6,2) W7=(200,500) W8=(20,44),L8=(10,30) W1=(3,7),L1=(0.6,3) W2=(0.6,3),L2=(60,100) W4=(1,10),L4=(0.6,3) W5=(6,12),L5=(0.6,3) W6=(100,145) W1=(2,4),L1=(0.6,3) W2=(0.6,3),L2=(137,172) W4=(1,7),L4=(1,6) W5=(3,5),L5=(0.6,3) W6=(29,53),W7=(438,1039) W8=(26,36),L8=(12,18) W1=(1,8),L1=(0.6,2) W2=(0.6,2),L2=(70,300) W4=(6,20) L4=(0.6,2) W5=(2,12),L5=(0.6,2) W6=(120,160) R1=(498,800) Rfd=(10000,30000) W1=(1,8),L1=(0.6,2) W2=(0.6,2),L2=(70,300) W4=(1200,5000) L4=(0.6,2) W5=(2,10),L5=(0.6,2) W6=(120,160) R1=(2000,5000) Rfd=(8000,40000)
Performance after synthesis area = 324 sq power = 1.67mW gain = 170 UGF = 18Mhz area = 149 sq power = 1.824mW gain = 80 UGF = 20Mhz power = 3.71mW gain < 5 area = 6710 sq power = 1.95 mW gain = 25 BW = 400Khz SR = 11V/s area = 11992 sq power = 7.11 mW BW = 503Khz gain = 20 SR = 12.5V/s
Table 3: Circuit synthesis results for IGA of zero. It is possible that the IGA might not come up with solutions having a cost of zero, for very tight set of constraints, in which cases care should be exercised in setting the ranges for the variables in circuit synthesis.
6 Conclusion
An automatic constraint transformation methodology was presented. The idea of parameter space exploration during constraint transformation was introduced and it's use in pruning the search space of a circuit synthesis tool was presented. Experimental results to show the e ect of parameter space exploration were provided using the ASTRX/OBLX circuit synthesis tool. An Interval Genetic Algorithm that interacts with a performance estimator was presented to perform this task of constraint transformation.
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