Buck Converter Modeling, Control, and Compensator Design
Buck Converter Modeling, Control, and Compensator Design
1
OUTLINE • Three terminal PWM switch modeling • Open loop transfer function • Voltage Mode Control and Peak Current Mode Control • Closed loop transfer functions • Closed loop gain • Compensator Design • Pspice and Mathcad Simulation • Experimental verification
2
Voltage Mode Switching Regulator VO
Converter Power Stage
VIN +
d
PWM Comparator Fm
+
Feedback Control To Achieve
• • •
R K Loop Compensator A(S) +
VREF
Accuracy: Steady-State Error Speed:
Transient Response
Stability
Gain and Phase Margin 3
Average Small Signal PWM Switch Modeling
4
Average Model L
Q1 Vin +
?
RL Rc
D
Ro
Co
Nonlinear Characteristics for Switching Elements Q1 and Q2 Modeling Method: 1. Space Average Model-----Middlebrook (CIT) 2. Three Terminal Switch --- Vorperian (VPEC) 3. DC Transformer Based 5
PWM Switch in Basic DC-DC Converters Boost Buck A Vin +
Q1 C
?
P
C D
Co D
L
L
Ro
+
VIN
Co
? Q1
P
R
A
Buck-Boost A
• A: Active Switch Node • C: Common Node • P: Passive switch (Diode)
D
Q1 C
P
? Vin +
L
Co
Ro
6
Non-Linear PWM Switch A
Q1 C D P
DC Model A
D C
AC Model A
d C
D’
d’
P
P
Where D’ = 1 - D 7
Average Model for Buck Regulator (Cont.) A
C iL L
Q1
+
iin +
Vin
?
vPH
-
RL
iin Rc
Ip Iv
iL
d
Co Vin
vQ2
P
i in =
I p + Iv 2
• d = d iL
Transformer Characteristics
DC Average Model iin A 1:d C iL +
i in = i L d v PH = v ind Model valid only at CCM
vPH
P 8
What is Small Signal Model? • Adding a small signal near the operating point v in = Vin + vˆ in i in = I in + iˆin d = D + dˆ i L = I L + iˆL v PH = VPH + vˆ PH
A
C iL L
Q1
+
iin +
Vin
?
vPH
-
RL Rc Co
P
9
Small Signal Average Model of three Terminal PWM Switch
i in = i L d v PH = v ind
Linearization v in = Vin + vˆ in i in = I in + iˆin d = D + dˆ i L = I L + iˆL
iˆin = I L dˆ + D iˆL vˆ PH = Vindˆ + D vˆ in
C
Q1
A 1:d C iL
iin
+
?
vPH
P
P
Small Signal Average Model iˆin A C +
v PH = VPH + vˆ PH
A
ILdˆ 1:D Vindˆ
P
10
Small Signal Average Model Buck Converter
+
A
C
A
C
L
ILdˆ 1:D Vindˆ
VIN
Co
+
P
R
P
+ Vˆ in
+
A
ILdˆ 1:D Vindˆ
C L Co
R
P 11
Open Loop Line to Output Transfer Function (Buck)
vˆ o z Gv = =D vˆ in ˆ S S2 d =0 1 + Qω + 2 o ω o
+
1 + ωS
L
ILdˆ 1:D Vindˆ
+
vˆ o
C RL
A
RC
Vˆin
R
C
Vo Gv = =D Vin S =0
P C RL
A
vˆ o
L
1:D
RC
+
Vˆin
R
C
1 1 RL R P ωo ≈ , ωz = , ωzL = , Q≈ L Rc C L LC C
12
Open Loop Line to Output Transfer Function (buck)
vˆ o Gv = vˆ in Vo Gv = Vin
=D dˆ =0
1 + ωS
z
S 1 + Qω o
+
S2 2 ωo
Q factor
Gv
D ωo
-40db/dec
S =0 = D
ESR Zero -20db/dec RL 1 R ωo ≈ , ωz = , ωzL = , Q≈ L R C L LC c 1
C
13
Open Loop Control to Output Transfer Function (Buck)
vˆ o
C RL +
A
L
ILdˆ 1:D Vindˆ
+
RC
Vˆin
C
P
1+ = VIN vˆ in =0
S 1 + Qω + o
S2 2 ωo
Vindˆ
P Vo Gd ( DC ) = = VIN D
1 + ωS
z
S 1 + Qω + o
vˆ o
L
+
vˆ o Gd = dˆ
RL
S ωz
S2 2 ωo S =0
R
C RC
R
C
= VIN ωo ≈
1 1 RL R , ωz = , ωzL = , Q≈ L Rc C L LC
C
14
Control to Output Transfer Function (buck) Q factor
vˆ o Gd = dˆ
= VIN vˆ in =0
VIN
Gd
1 + ωS
z
S 1 + Qω o
+
S2 2 ωo
ωo
-40db/dec
ESR Zero -20db/dec RL 1 R ωo ≈ , ωz = , ωzL = , Q≈ L R C L LC c 1
C
15
Open Loop Output Impedance +
Zp
vˆ o = iˆ
vˆ o
C RL
A
L
ILdˆ 1:D Vindˆ
+
RC
Vˆin
o dˆ =vˆ =0 in
R
C
P
Zp
S ωz
(1 + vˆ o = = RL // R • ˆi o 1+
Z p (S = 0 ) = RL // R
) • ( 1 + ωS zL S S2 Qωo + ω2 o
)
vˆ o
RL L
RC
R
ZO
C
Z p (s = ∞) = Rc // R
16
Open Loop Output Impedance
Zp
S ωz
(1 + vˆ o = = RL // R • ˆi o 1+
) • ( 1 + ωS zL S S2 Qωo + ω2 o
vˆ o
RL
)
L RC C
Z p (S = 0 ) = RL // R Z p (s = ∞) = Rc // R
ZO
R
Zp Q factor RL //R
ωZL
ωo
20db/dec RL 1 R ωo ≈ , ωz = , ωzL = , Q≈ L R C L LC c 1
-20db/dec Rc //R ESR Zero ω Z
C 17
Single Close Loop Controlled Switching Regulator
18
Small Signal Close Loop Controlled Switching Regulator Small Signal Block Diagram
vˆ in
dˆ
Converter Power Stage
iˆo
vˆ in
vˆ vˆ o vˆ o , , , ... vˆ in iˆo dˆ
vˆ o
iˆo
Compensator -A(S) Fm
GV ZP
Power Stage
vˆ o
X T
Gd
dˆ
-A(S)
Fm
PWM Comparator 19
Open-loop Transfer Function
vˆ in Open Loop Voltage Gain
iˆo
(Open loop audio Susceptibility) vˆ o Gv = @ iˆo = 0 and dˆ = 0 vˆ in
GV ZP
vˆ o
X T
Gd
dˆ
Fm
-A(S)
vˆ C
Open Loop Output Impedance vˆ o Zp = @ dˆ = 0 and vˆ = 0 iˆ o
20
Open-loop Transfer Function (Cont.) vˆ in GV
Control to Output Transfer Function vˆ o Gd = @ vˆ in = iˆo = 0 dˆ
iˆo
ZP
vˆ o
X T
Gd Loop Compensator Gain
vˆ c A(s) = vˆ o
dˆ
-A(S)
vˆ C
Fm
PWM Comparator Gain
dˆ Fm = vˆ c 21
Small Signal PWM Comparator Gain Fm
PWM Comparator
vˆc
vcomp
vramp
Vc
dˆ
+ Fm -
DTs
Fm
vc
vˆ c VP
dˆTs
dd dˆ 1 = = = ˆ dv c v c VP 22
Closed Loop Audio-Susceptibility (Line Trans. Response)
vˆ o vˆ in Audio Susceptibility GV vˆ in ˆ i o = 0 iˆ o vˆ o = Gv vˆ in + Gd dˆ dˆ = -Fm A vˆ o
vˆ o Gv Gv = = vˆ in 1 + Gd Fm A 1 + T
ZP
vˆ o
X T
Gd
dˆ
Fm
-A(S)
vˆ C
Audio-Susceptibility Physical meaning: Line transient response Loop Gain:
T = Fm Gd A
• High loop gain T will improve the line transient response 23
Closed Loop Output Impedance (Load Transient Response)
vˆ o Closed Loop Output Impedance iˆo vˆ in = 0 vˆ o = Z p iˆo - Gd Fm A vˆ o
Zp Zp vˆ o ˆi = 1 + Gd Fm A = 1 + T o
iˆo vˆ in
ZP GV
vˆ o
X T
Gd
dˆ
-A
Fm
Output Impedance Physical meaning: Load step transient response • The smaller the output impedance, the faster the transient response • Higher loop gain is desired 24
Loop Gain Analysis
Loop Gain Provides: • System performance analysis: Transient response • Stability analysis: • Absolute stability • Degree of stability • Design insight • Measurement verification
25
Function of Loop Gain T: Closed-Loop Audio Susceptibility
vˆ o Gv = =D vˆ in
1 + ωSz 1 + QSωo +
vˆ in S2 2 ωo
iˆo
GV ZP
X
fC (bandwidth)
Gd
vˆ o
1+T
fo
GV
T ESR Zero
GCL
T dˆ
-A
Fm
vˆ o Gv GCL = = vˆ in 1 + T
• The smaller GCL, the faster line transient response • Require higher bandwidth fc
26
Function of Loop Gain T: Closed-Loop Output Impedance vˆ o Z p = ˆ = RL // R • io
( 1 + ωSz ) • ( 1 + ωSzL ) 1 + QSωo
+
1+T
S2 2 ωo
fC (bandwidth)
fo
ZP ωzL =
ESR
ZCL
iˆo
GV ZP
vˆ o
X T
Gd
dˆ
T ESR Zero
RL L
vˆ in
-A
Fm
vˆ o Z p ZCL = ˆ = io 1 + T
• ZCL used for load transient analysis • The smaller ZCL, the faster load transient response • The minimum high frequency Zo is ESR 27
Closed-Loop Output Impedance L
Q1
RL Rc
+ Q2
ZO
Ro
Co
1+T fC (bandwidth)
fo
ZP ωzL =
T ESR Zero
RL L
ESR
ZCL
ZCL
Zp vˆ o = = ˆi 1 +T o
When f • C shorts and L open • Minimum ZO: ESR • Smaller ESR, better load transient • Higher T, better load transient 28
Ideal Loop Gain Characteristics • • • •
High DC gain (Low frequency) for small DC error Wide bandwidth for fast transient response -20dB/dec slope near cross-over frequency for higher phase margin High attenuation at high frequency for noise reduction
|T|
fC (bandwidth)
0dB
fo
Gm: Gain margin
∠T Phase margin Φm
-180o 29
Examples of Loop Gain T S=jω Definition
• Single Order System ; T = Gm S ω 1+ p T ωp -20dB/Dec
Magnitude = 20 log T Phase = Angle (T )
ω S-Plane 0o
(-1,0)
Gm (S=0)
-45o -90o Phase Margin: 90o -180o • Always stable • 90o phase margin
T=1/(1 + j) @ S=jωp Magnitude = -20 log 2 Phase = -45 degree 30
Examples of Loop Gain T • 2nd Order System ; T =
T
ωo
Gm S S2 1+ + 2 ωoQ ωo
ω -40dB/Dec
|T|=1 (-1,0)
0o -90o
S-Plane Gm (S=0)
ϕ
-180o • Stable • ϕ phase margin: may be very small • Gain margin: infinite (theoretical)
S = jωo QGm T = j 31
Basic Pole and Zero Characteristics
ωp One Pole
T 20dB/Dec
• 45 degree at the Pole (frequency fp) • Total of
90o
ω
phase delay after >10 fp
• -20 db/dec One Zero • 45o phase lead at the zero • Total of 90o phase lead after >10 fz • +20db/dec
1+ G( S ) = 1+
90o 45o 0o
S 10 3 S 10 5 32
DC Loop Gain
iˆo vˆ in
ZP
+
GV
Gd
dˆ
OUTPUT
T Fm
A
Error
-
Vo
+ VREF
vˆ in = iˆo = 0 DC Error = VREF
Vo - Vo = AFmGd
S =0
Vo = T ( DC loop gain )
• The higher DC loop gain, the smaller the DC steady-state error • 40dB DC loop gain, 1% error 33
Compensator Design Considerations
34
Objectives of Loop Gain Design
vˆ in Objective:
iˆo
• To shape the loop gain T for achieving
GV ZP
vˆ o
+ T
Gd
High DC gain at low frequency
>40 degree phase margin
> 10 dB gain margin
High bandwidth for fast transient response
dˆ
-A(S)
Fm
T = Gd • A( S ) • Fm 35
Load Transient Step Response vs Phase Margin • The amount of ringing determines the phase margin – 45º phase margin is sufficient • The crossover frequency is equal to the ringing frequency – Crossover frequency should be 1/5 or 1/10 of the converter switching frequency 2 1.659 ϕ=15°° ϕ=30°° ϕ=45°° ϕ=60°°
1.5 v( t , 15 ) v( t , 30 ) v( t , 45 )
1
v( t , 60 )
Crossover Frequency
0.5
1.177 ×10
−4
0
0 0.015
5
10 ω c⋅ t
15
20 20
36
Compensator Design Considerations (Voltage mode) Buck Converter
Compensator: Constant Gain
T
T = Gd AFm , A(s) = K c ; T = FmVIN
1 + ωS
z
S S2 1 + Qω + 2 o ωo
1 1 ωo ≈ , ωz = , Rc C LC
ωo fC (bandwidth)
• Kc
ESR Zero 0o
Q≈
R L C
ωZ
-90o -180o
• Low DC gain, need an integrator • Almost 0o phase margin if ωz > 3 ωo • Stable if ESR zero ωz < 3 ωo 37
Compensator Design Considerations (cont.) -20db/dec ωo -60db/dec T ωC (bandwidth)
Compensator: Integrator Kc T = Gd AFm , A(s) = S ; 1 + ωS Kc z T = FmVIN • S 2 S 1 + Qω + S2 o ωo
1 1 ωo ≈ , ωz = , Rc C LC
Q≈
ESR Zero -90o
ωZ
-40db/dec
-180o R L C
-270o
Unstable
• Integrator: 90o delay; Double pole: 180o delay • low bandwidth or unstable • Need to introduce two zeros before cross-over frequency ωC 38
Type III Compensator Characteristics TOPEN = Gd Fm TCLOSE = Gd Fm A(s )
• Design based on OPEN LOOP GAIN • An integrator for high DC gain
A(S)
Two Poles Integrator x Two Zeros x
GdFm
• Place two zeros around fo for compensating phase delay due to the integrator and double poles
fo
ESR Zero |T|
• Two high frequency poles
fC
• to cancel ESR zero • to attenuate high frequency noise • to ensure the gain decreasing after fc
∠T
-90o
• to ensure the phase lag minimum at fc
-180o 39
Type III Loop compensator Circuit vˆ c ZF =, A( S ) = vˆ o ZI 1 1 ZF = // ( R2 + ); SC3 SC1 1 Z I = R1 //( R3 + ) SC2
ZF R2
vC
• Zeros: 1. R2, C1; 2. R1+R3, C2
• 1. 2. 3.
C1
ZI
R3 C2
vo
-
Compensator output
S S ( 1 + ) • ( 1 + ) KI ω z1 ωz 2 A( S ) = S ( 1+ S )•( 1+ S ) ω p1 ω p2
C3
+
R1
VREF
K I = R (C1 +C ) , 1 1 3 ωz1 = R 1C , ωz 2 = C (R1 +R ) 2 1 2 1 3
Poles: 1 DC ω p1 = R 1C , ω p 2 = C1C3 3 2 R2 R2, C3 if C1>>C3 C1 +C3 R3, C2
40
Loop Gain Design (voltage mode) vˆ in
iˆo
T = Gd AFm T = FmVIN
1 + ωS
z
K c ( 1 + ωS ) • ( 1 + ωS )
z1 z2 S S2 S • (1 + S ) • (1 + S ) 1 + Qω + 2 ω p1 ωp2 o ωo
Gd(S)
A(S): Compensator
1 1 ωo ≈ , ωz = , Rc C LC
Q≈
GV ZP
vˆ o
+ T
Gd
dˆ
-A
Fm
R L C
• Type III compensator: two zeros (ωz1, ωz2) and three poles (0, ωp1, ωp2) • Loop gain is proportional to the input voltage. Need input voltage feed-forward function 41
Objective of Compensator Design
T = Gd AFm T = FmVIN
1 + ωS
K c ( 1 + ωS ) • ( 1 + ωS )
z1 z2 S S2 S • (1 + S ) • (1 + S ) 1 + Qω + 2 ω p1 ωp2 o ωo z
• Objective is to design a compensator, Kc, ωz1, ωz2, ωp1, ωp2, to SHAPE the loop gain T for stability and optimum performance for given power stage parameters, ωz, ωo, Q, VIN, and PWM gain Fm.
42
Loop Gain Design Procedure (Case 1)
Integrator -20db/dec ωz1, ωz2
FmGd
T = Fm
ωp1
VIN ( 1 + ωS ) K c ( 1 + ωS ) • ( 1 + ωS ) z z1 z2 S 1 + Qω o
S • ( 1 + ωS ) • ( 1 + ωS ) p1
Gd(S)
T
ωc
ωp2
p2
A(S)
• Bandwidth fc = (1/5-1/10) fs • ωz1, ωz2 near ωo
ωo
ESR Zero ωz
+
S2 2 ωo
• ωp1 cancel ESR zero ωz -40deb/dec
• ωp2 = 10 ωc • Determine Kc • Select compensator R’s and C’s 43
Type III Compensator Design (Case II)
• An integrator for high DC gain • Place two zeros around fo
A(S)
Two Poles Integrator x Two Zeros x
GdFm
fo
• Two high frequency poles to cancel ESR zero and increase |T| gain attenuation at high frequency
Open loop Gain ESR Zero
fC
∠T
-90o -180o 44
Type II Compensator Integrator A(S) Type II Compensator • One zero and two poles • if ESR zero is close to double pole ωz< 3 ωo
A( S ) =
One Zero
GdFm
One Pole
x
ωo
ωz |T|
S K I 1 + ωz 1 • S 1+ S ω p1
ωC ∠T -90o -180o 45
Loop Gain T function of Input Voltage T = Fm
VIN ( 1 + ωS ) K c ( 1 + ωS ) • ( 1 + ωS ) z
S 1 + Qω o
VIN
+
S2 2 ωo
S • (1 +
z1 S ω p1
) • (1 +
z2 S ωp2
)
• T is function of VIN • Need feed-forward function to cancel
VIN
VIN effect fC
-90o -180o
Very little phase margin 46
Comparator Gain with Feed-Forward Function Feed-Forward: PWM ramp is function of the input voltage
v comp
d
1 = Vcomp VP
+ Fm -
dd dˆ 1 Fm = = = dv comp vˆ comp VP
VP = K VIN
PWM Comparator
1 Fm = KVIN
vcomp
d
vramp
VP
d
47
Loop Gain with Feed-Forward Function T = Gd AFm T = Fm VIN
1 + ωSz 1 + QSωo
+
Kc ( 1 + ωSz1 ) • ( 1 + ωSz 2 ) S2 2 ωo
S • ( 1 + ωSp1 ) • ( 1 + ωSp 2 )
1 Fm = KVIN 1 T = V IN KV IN 1+
1+
S ωz
S Q ωo
+
Kc (1 + S2 2 ωo
S • (1 +
S ωz1 S ω p1
) • (1 + ) • (1 +
S ωz 2 S ωp2
) )
• Loop Gain is INDEPENDENT of input voltage. • Fast line step transient response, Only depends on conversion speed of Vramp= f(VIN) 48
How to Measure the Loop Gain Q1
L VIN
VO
RESR
+
R
c
Co
Q2
R1
Ton D= Ts
Gate driver
Vexcite = 10-20mV
+ PWM Comparator
-
a VC
A(S)
+
b
VREF Compensator
R2
• Network Analyzer • AP200 • a and b: 20-50mV perturbation; c: depends on output voltage 49
Modeling, Simulation and Test Example TPS40200 • Voltage mode PWM controller • Input Voltage range: 4.5V to 50V • Input Voltage Feed Forward function PWM ramp voltage = VIN/10 • Programmable switching frequency • Vout: 0.7V to 90% of VIN VIN=20V, VOUT= 5V, fs = 300kHz, L=47uH, Co=22uF/10mΩ Ω
50
Buck Converter with Voltage Mode and Type III Compensator L: 47uH, 0.25Ω Ω
Q1
VIN 20V
RESR 5mΩ Ω +
D
Co 22µ µF
VO
R C3: 10p
Ton D= Ts
VIN 10 Gate driver
R2: 23.2k C1:1.5n
+ PWM Comparator
VC
C2 1n
R1 30.9k
R3 1.15k
A(S) +
VREF + 0.7V
Rx 4.99k
51
Pspice Simulation Schematic PWM small signal average model
PWM gain Loop gain test perturbation
Type III Compensator 52
Simulation and Test Results PSPICE Simulation Results 0.3
3.5 Output Voltage Load Current
0.2
3 2.5
VOUT
0.0
2
-0.1
1.5
IOUT
-0.2
1
-0.3
0.5
-0.4
0
-0.5
-0.5 0
40
80
Load Current (A)
0.1 Output Voltage (V)
Test Results
VOUT IOUT
120 160 200 240 280 320 360 400 Time (us)
Load Step Transient: 0.4A to 0.8A
53
Simulation and Test Results Test Results
1.0
3.5
0.5
3
VOUT
0.0
2.5
-0.5
Output Voltage Load Current
IOUT
-1.0
2 1.5
-1.5
1
-2.0
0.5
-2.5
0
-3.0
-0.5 0
Load Current (A)
Output Voltage (V)
PSPICE Simulation Results
100 200 300 400 500 600 700 800 900 1000 Time (us)
Load Step Transient: 0.1A to 1.5A 54
Loop Bandwidth Simulation: Mathcad and Pspice Mathcad 60
Pspice 60
50
Bandwidth 35kHz
40
Bandwidth 45kHz
20
0
0
gain(Tv( S( fi) ) )
-20 50
-40
− 80 100 100 0
3
4
1 .10
5
1 .10 f( fi)
6
1 .10
1 .10 6
-60 1.0E+02
1.0E+03
1.0E+04
1.0E+05
1.0E+06
1.0E+04
1.0E+05
1.0E+06 55
1×10
0
0
Phase Margin 65 degree
50
-50
phase( Tv( S( fi) ) ) − 180
-100
100
150
-150
-180
− 200 200 10 10
100
3
4
1 .10
1 .10 f ( fi)
5
1 .10
6
1 .10 6 1×10
Phase Margin 70 degree
-200 1.0E+02
1.0E+03
Thanks!
Current Mode Loop Compensator Design will be next time
56
1
OUTLINE • Three terminal PWM switch modeling • Open loop transfer function • Voltage Mode Control and Peak Current Mode Control • Closed loop transfer functions • Closed loop gain • Compensator Design • Pspice and Mathcad Simulation • Experimental verification
2
Voltage Mode Switching Regulator VO
Converter Power Stage
VIN +
d
PWM Comparator Fm
+
Feedback Control To Achieve
• • •
R K Loop Compensator A(S) +
VREF
Accuracy: Steady-State Error Speed:
Transient Response
Stability
Gain and Phase Margin 3
Average Small Signal PWM Switch Modeling
4
Average Model L
Q1 Vin +
?
RL Rc
D
Ro
Co
Nonlinear Characteristics for Switching Elements Q1 and Q2 Modeling Method: 1. Space Average Model-----Middlebrook (CIT) 2. Three Terminal Switch --- Vorperian (VPEC) 3. DC Transformer Based 5
PWM Switch in Basic DC-DC Converters Boost Buck A Vin +
Q1 C
?
P
C D
Co D
L
L
Ro
+
VIN
Co
? Q1
P
R
A
Buck-Boost A
• A: Active Switch Node • C: Common Node • P: Passive switch (Diode)
D
Q1 C
P
? Vin +
L
Co
Ro
6
Non-Linear PWM Switch A
Q1 C D P
DC Model A
D C
AC Model A
d C
D’
d’
P
P
Where D’ = 1 - D 7
Average Model for Buck Regulator (Cont.) A
C iL L
Q1
+
iin +
Vin
?
vPH
-
RL
iin Rc
Ip Iv
iL
d
Co Vin
vQ2
P
i in =
I p + Iv 2
• d = d iL
Transformer Characteristics
DC Average Model iin A 1:d C iL +
i in = i L d v PH = v ind Model valid only at CCM
vPH
P 8
What is Small Signal Model? • Adding a small signal near the operating point v in = Vin + vˆ in i in = I in + iˆin d = D + dˆ i L = I L + iˆL v PH = VPH + vˆ PH
A
C iL L
Q1
+
iin +
Vin
?
vPH
-
RL Rc Co
P
9
Small Signal Average Model of three Terminal PWM Switch
i in = i L d v PH = v ind
Linearization v in = Vin + vˆ in i in = I in + iˆin d = D + dˆ i L = I L + iˆL
iˆin = I L dˆ + D iˆL vˆ PH = Vindˆ + D vˆ in
C
Q1
A 1:d C iL
iin
+
?
vPH
P
P
Small Signal Average Model iˆin A C +
v PH = VPH + vˆ PH
A
ILdˆ 1:D Vindˆ
P
10
Small Signal Average Model Buck Converter
+
A
C
A
C
L
ILdˆ 1:D Vindˆ
VIN
Co
+
P
R
P
+ Vˆ in
+
A
ILdˆ 1:D Vindˆ
C L Co
R
P 11
Open Loop Line to Output Transfer Function (Buck)
vˆ o z Gv = =D vˆ in ˆ S S2 d =0 1 + Qω + 2 o ω o
+
1 + ωS
L
ILdˆ 1:D Vindˆ
+
vˆ o
C RL
A
RC
Vˆin
R
C
Vo Gv = =D Vin S =0
P C RL
A
vˆ o
L
1:D
RC
+
Vˆin
R
C
1 1 RL R P ωo ≈ , ωz = , ωzL = , Q≈ L Rc C L LC C
12
Open Loop Line to Output Transfer Function (buck)
vˆ o Gv = vˆ in Vo Gv = Vin
=D dˆ =0
1 + ωS
z
S 1 + Qω o
+
S2 2 ωo
Q factor
Gv
D ωo
-40db/dec
S =0 = D
ESR Zero -20db/dec RL 1 R ωo ≈ , ωz = , ωzL = , Q≈ L R C L LC c 1
C
13
Open Loop Control to Output Transfer Function (Buck)
vˆ o
C RL +
A
L
ILdˆ 1:D Vindˆ
+
RC
Vˆin
C
P
1+ = VIN vˆ in =0
S 1 + Qω + o
S2 2 ωo
Vindˆ
P Vo Gd ( DC ) = = VIN D
1 + ωS
z
S 1 + Qω + o
vˆ o
L
+
vˆ o Gd = dˆ
RL
S ωz
S2 2 ωo S =0
R
C RC
R
C
= VIN ωo ≈
1 1 RL R , ωz = , ωzL = , Q≈ L Rc C L LC
C
14
Control to Output Transfer Function (buck) Q factor
vˆ o Gd = dˆ
= VIN vˆ in =0
VIN
Gd
1 + ωS
z
S 1 + Qω o
+
S2 2 ωo
ωo
-40db/dec
ESR Zero -20db/dec RL 1 R ωo ≈ , ωz = , ωzL = , Q≈ L R C L LC c 1
C
15
Open Loop Output Impedance +
Zp
vˆ o = iˆ
vˆ o
C RL
A
L
ILdˆ 1:D Vindˆ
+
RC
Vˆin
o dˆ =vˆ =0 in
R
C
P
Zp
S ωz
(1 + vˆ o = = RL // R • ˆi o 1+
Z p (S = 0 ) = RL // R
) • ( 1 + ωS zL S S2 Qωo + ω2 o
)
vˆ o
RL L
RC
R
ZO
C
Z p (s = ∞) = Rc // R
16
Open Loop Output Impedance
Zp
S ωz
(1 + vˆ o = = RL // R • ˆi o 1+
) • ( 1 + ωS zL S S2 Qωo + ω2 o
vˆ o
RL
)
L RC C
Z p (S = 0 ) = RL // R Z p (s = ∞) = Rc // R
ZO
R
Zp Q factor RL //R
ωZL
ωo
20db/dec RL 1 R ωo ≈ , ωz = , ωzL = , Q≈ L R C L LC c 1
-20db/dec Rc //R ESR Zero ω Z
C 17
Single Close Loop Controlled Switching Regulator
18
Small Signal Close Loop Controlled Switching Regulator Small Signal Block Diagram
vˆ in
dˆ
Converter Power Stage
iˆo
vˆ in
vˆ vˆ o vˆ o , , , ... vˆ in iˆo dˆ
vˆ o
iˆo
Compensator -A(S) Fm
GV ZP
Power Stage
vˆ o
X T
Gd
dˆ
-A(S)
Fm
PWM Comparator 19
Open-loop Transfer Function
vˆ in Open Loop Voltage Gain
iˆo
(Open loop audio Susceptibility) vˆ o Gv = @ iˆo = 0 and dˆ = 0 vˆ in
GV ZP
vˆ o
X T
Gd
dˆ
Fm
-A(S)
vˆ C
Open Loop Output Impedance vˆ o Zp = @ dˆ = 0 and vˆ = 0 iˆ o
20
Open-loop Transfer Function (Cont.) vˆ in GV
Control to Output Transfer Function vˆ o Gd = @ vˆ in = iˆo = 0 dˆ
iˆo
ZP
vˆ o
X T
Gd Loop Compensator Gain
vˆ c A(s) = vˆ o
dˆ
-A(S)
vˆ C
Fm
PWM Comparator Gain
dˆ Fm = vˆ c 21
Small Signal PWM Comparator Gain Fm
PWM Comparator
vˆc
vcomp
vramp
Vc
dˆ
+ Fm -
DTs
Fm
vc
vˆ c VP
dˆTs
dd dˆ 1 = = = ˆ dv c v c VP 22
Closed Loop Audio-Susceptibility (Line Trans. Response)
vˆ o vˆ in Audio Susceptibility GV vˆ in ˆ i o = 0 iˆ o vˆ o = Gv vˆ in + Gd dˆ dˆ = -Fm A vˆ o
vˆ o Gv Gv = = vˆ in 1 + Gd Fm A 1 + T
ZP
vˆ o
X T
Gd
dˆ
Fm
-A(S)
vˆ C
Audio-Susceptibility Physical meaning: Line transient response Loop Gain:
T = Fm Gd A
• High loop gain T will improve the line transient response 23
Closed Loop Output Impedance (Load Transient Response)
vˆ o Closed Loop Output Impedance iˆo vˆ in = 0 vˆ o = Z p iˆo - Gd Fm A vˆ o
Zp Zp vˆ o ˆi = 1 + Gd Fm A = 1 + T o
iˆo vˆ in
ZP GV
vˆ o
X T
Gd
dˆ
-A
Fm
Output Impedance Physical meaning: Load step transient response • The smaller the output impedance, the faster the transient response • Higher loop gain is desired 24
Loop Gain Analysis
Loop Gain Provides: • System performance analysis: Transient response • Stability analysis: • Absolute stability • Degree of stability • Design insight • Measurement verification
25
Function of Loop Gain T: Closed-Loop Audio Susceptibility
vˆ o Gv = =D vˆ in
1 + ωSz 1 + QSωo +
vˆ in S2 2 ωo
iˆo
GV ZP
X
fC (bandwidth)
Gd
vˆ o
1+T
fo
GV
T ESR Zero
GCL
T dˆ
-A
Fm
vˆ o Gv GCL = = vˆ in 1 + T
• The smaller GCL, the faster line transient response • Require higher bandwidth fc
26
Function of Loop Gain T: Closed-Loop Output Impedance vˆ o Z p = ˆ = RL // R • io
( 1 + ωSz ) • ( 1 + ωSzL ) 1 + QSωo
+
1+T
S2 2 ωo
fC (bandwidth)
fo
ZP ωzL =
ESR
ZCL
iˆo
GV ZP
vˆ o
X T
Gd
dˆ
T ESR Zero
RL L
vˆ in
-A
Fm
vˆ o Z p ZCL = ˆ = io 1 + T
• ZCL used for load transient analysis • The smaller ZCL, the faster load transient response • The minimum high frequency Zo is ESR 27
Closed-Loop Output Impedance L
Q1
RL Rc
+ Q2
ZO
Ro
Co
1+T fC (bandwidth)
fo
ZP ωzL =
T ESR Zero
RL L
ESR
ZCL
ZCL
Zp vˆ o = = ˆi 1 +T o
When f • C shorts and L open • Minimum ZO: ESR • Smaller ESR, better load transient • Higher T, better load transient 28
Ideal Loop Gain Characteristics • • • •
High DC gain (Low frequency) for small DC error Wide bandwidth for fast transient response -20dB/dec slope near cross-over frequency for higher phase margin High attenuation at high frequency for noise reduction
|T|
fC (bandwidth)
0dB
fo
Gm: Gain margin
∠T Phase margin Φm
-180o 29
Examples of Loop Gain T S=jω Definition
• Single Order System ; T = Gm S ω 1+ p T ωp -20dB/Dec
Magnitude = 20 log T Phase = Angle (T )
ω S-Plane 0o
(-1,0)
Gm (S=0)
-45o -90o Phase Margin: 90o -180o • Always stable • 90o phase margin
T=1/(1 + j) @ S=jωp Magnitude = -20 log 2 Phase = -45 degree 30
Examples of Loop Gain T • 2nd Order System ; T =
T
ωo
Gm S S2 1+ + 2 ωoQ ωo
ω -40dB/Dec
|T|=1 (-1,0)
0o -90o
S-Plane Gm (S=0)
ϕ
-180o • Stable • ϕ phase margin: may be very small • Gain margin: infinite (theoretical)
S = jωo QGm T = j 31
Basic Pole and Zero Characteristics
ωp One Pole
T 20dB/Dec
• 45 degree at the Pole (frequency fp) • Total of
90o
ω
phase delay after >10 fp
• -20 db/dec One Zero • 45o phase lead at the zero • Total of 90o phase lead after >10 fz • +20db/dec
1+ G( S ) = 1+
90o 45o 0o
S 10 3 S 10 5 32
DC Loop Gain
iˆo vˆ in
ZP
+
GV
Gd
dˆ
OUTPUT
T Fm
A
Error
-
Vo
+ VREF
vˆ in = iˆo = 0 DC Error = VREF
Vo - Vo = AFmGd
S =0
Vo = T ( DC loop gain )
• The higher DC loop gain, the smaller the DC steady-state error • 40dB DC loop gain, 1% error 33
Compensator Design Considerations
34
Objectives of Loop Gain Design
vˆ in Objective:
iˆo
• To shape the loop gain T for achieving
GV ZP
vˆ o
+ T
Gd
High DC gain at low frequency
>40 degree phase margin
> 10 dB gain margin
High bandwidth for fast transient response
dˆ
-A(S)
Fm
T = Gd • A( S ) • Fm 35
Load Transient Step Response vs Phase Margin • The amount of ringing determines the phase margin – 45º phase margin is sufficient • The crossover frequency is equal to the ringing frequency – Crossover frequency should be 1/5 or 1/10 of the converter switching frequency 2 1.659 ϕ=15°° ϕ=30°° ϕ=45°° ϕ=60°°
1.5 v( t , 15 ) v( t , 30 ) v( t , 45 )
1
v( t , 60 )
Crossover Frequency
0.5
1.177 ×10
−4
0
0 0.015
5
10 ω c⋅ t
15
20 20
36
Compensator Design Considerations (Voltage mode) Buck Converter
Compensator: Constant Gain
T
T = Gd AFm , A(s) = K c ; T = FmVIN
1 + ωS
z
S S2 1 + Qω + 2 o ωo
1 1 ωo ≈ , ωz = , Rc C LC
ωo fC (bandwidth)
• Kc
ESR Zero 0o
Q≈
R L C
ωZ
-90o -180o
• Low DC gain, need an integrator • Almost 0o phase margin if ωz > 3 ωo • Stable if ESR zero ωz < 3 ωo 37
Compensator Design Considerations (cont.) -20db/dec ωo -60db/dec T ωC (bandwidth)
Compensator: Integrator Kc T = Gd AFm , A(s) = S ; 1 + ωS Kc z T = FmVIN • S 2 S 1 + Qω + S2 o ωo
1 1 ωo ≈ , ωz = , Rc C LC
Q≈
ESR Zero -90o
ωZ
-40db/dec
-180o R L C
-270o
Unstable
• Integrator: 90o delay; Double pole: 180o delay • low bandwidth or unstable • Need to introduce two zeros before cross-over frequency ωC 38
Type III Compensator Characteristics TOPEN = Gd Fm TCLOSE = Gd Fm A(s )
• Design based on OPEN LOOP GAIN • An integrator for high DC gain
A(S)
Two Poles Integrator x Two Zeros x
GdFm
• Place two zeros around fo for compensating phase delay due to the integrator and double poles
fo
ESR Zero |T|
• Two high frequency poles
fC
• to cancel ESR zero • to attenuate high frequency noise • to ensure the gain decreasing after fc
∠T
-90o
• to ensure the phase lag minimum at fc
-180o 39
Type III Loop compensator Circuit vˆ c ZF =, A( S ) = vˆ o ZI 1 1 ZF = // ( R2 + ); SC3 SC1 1 Z I = R1 //( R3 + ) SC2
ZF R2
vC
• Zeros: 1. R2, C1; 2. R1+R3, C2
• 1. 2. 3.
C1
ZI
R3 C2
vo
-
Compensator output
S S ( 1 + ) • ( 1 + ) KI ω z1 ωz 2 A( S ) = S ( 1+ S )•( 1+ S ) ω p1 ω p2
C3
+
R1
VREF
K I = R (C1 +C ) , 1 1 3 ωz1 = R 1C , ωz 2 = C (R1 +R ) 2 1 2 1 3
Poles: 1 DC ω p1 = R 1C , ω p 2 = C1C3 3 2 R2 R2, C3 if C1>>C3 C1 +C3 R3, C2
40
Loop Gain Design (voltage mode) vˆ in
iˆo
T = Gd AFm T = FmVIN
1 + ωS
z
K c ( 1 + ωS ) • ( 1 + ωS )
z1 z2 S S2 S • (1 + S ) • (1 + S ) 1 + Qω + 2 ω p1 ωp2 o ωo
Gd(S)
A(S): Compensator
1 1 ωo ≈ , ωz = , Rc C LC
Q≈
GV ZP
vˆ o
+ T
Gd
dˆ
-A
Fm
R L C
• Type III compensator: two zeros (ωz1, ωz2) and three poles (0, ωp1, ωp2) • Loop gain is proportional to the input voltage. Need input voltage feed-forward function 41
Objective of Compensator Design
T = Gd AFm T = FmVIN
1 + ωS
K c ( 1 + ωS ) • ( 1 + ωS )
z1 z2 S S2 S • (1 + S ) • (1 + S ) 1 + Qω + 2 ω p1 ωp2 o ωo z
• Objective is to design a compensator, Kc, ωz1, ωz2, ωp1, ωp2, to SHAPE the loop gain T for stability and optimum performance for given power stage parameters, ωz, ωo, Q, VIN, and PWM gain Fm.
42
Loop Gain Design Procedure (Case 1)
Integrator -20db/dec ωz1, ωz2
FmGd
T = Fm
ωp1
VIN ( 1 + ωS ) K c ( 1 + ωS ) • ( 1 + ωS ) z z1 z2 S 1 + Qω o
S • ( 1 + ωS ) • ( 1 + ωS ) p1
Gd(S)
T
ωc
ωp2
p2
A(S)
• Bandwidth fc = (1/5-1/10) fs • ωz1, ωz2 near ωo
ωo
ESR Zero ωz
+
S2 2 ωo
• ωp1 cancel ESR zero ωz -40deb/dec
• ωp2 = 10 ωc • Determine Kc • Select compensator R’s and C’s 43
Type III Compensator Design (Case II)
• An integrator for high DC gain • Place two zeros around fo
A(S)
Two Poles Integrator x Two Zeros x
GdFm
fo
• Two high frequency poles to cancel ESR zero and increase |T| gain attenuation at high frequency
Open loop Gain ESR Zero
fC
∠T
-90o -180o 44
Type II Compensator Integrator A(S) Type II Compensator • One zero and two poles • if ESR zero is close to double pole ωz< 3 ωo
A( S ) =
One Zero
GdFm
One Pole
x
ωo
ωz |T|
S K I 1 + ωz 1 • S 1+ S ω p1
ωC ∠T -90o -180o 45
Loop Gain T function of Input Voltage T = Fm
VIN ( 1 + ωS ) K c ( 1 + ωS ) • ( 1 + ωS ) z
S 1 + Qω o
VIN
+
S2 2 ωo
S • (1 +
z1 S ω p1
) • (1 +
z2 S ωp2
)
• T is function of VIN • Need feed-forward function to cancel
VIN
VIN effect fC
-90o -180o
Very little phase margin 46
Comparator Gain with Feed-Forward Function Feed-Forward: PWM ramp is function of the input voltage
v comp
d
1 = Vcomp VP
+ Fm -
dd dˆ 1 Fm = = = dv comp vˆ comp VP
VP = K VIN
PWM Comparator
1 Fm = KVIN
vcomp
d
vramp
VP
d
47
Loop Gain with Feed-Forward Function T = Gd AFm T = Fm VIN
1 + ωSz 1 + QSωo
+
Kc ( 1 + ωSz1 ) • ( 1 + ωSz 2 ) S2 2 ωo
S • ( 1 + ωSp1 ) • ( 1 + ωSp 2 )
1 Fm = KVIN 1 T = V IN KV IN 1+
1+
S ωz
S Q ωo
+
Kc (1 + S2 2 ωo
S • (1 +
S ωz1 S ω p1
) • (1 + ) • (1 +
S ωz 2 S ωp2
) )
• Loop Gain is INDEPENDENT of input voltage. • Fast line step transient response, Only depends on conversion speed of Vramp= f(VIN) 48
How to Measure the Loop Gain Q1
L VIN
VO
RESR
+
R
c
Co
Q2
R1
Ton D= Ts
Gate driver
Vexcite = 10-20mV
+ PWM Comparator
-
a VC
A(S)
+
b
VREF Compensator
R2
• Network Analyzer • AP200 • a and b: 20-50mV perturbation; c: depends on output voltage 49
Modeling, Simulation and Test Example TPS40200 • Voltage mode PWM controller • Input Voltage range: 4.5V to 50V • Input Voltage Feed Forward function PWM ramp voltage = VIN/10 • Programmable switching frequency • Vout: 0.7V to 90% of VIN VIN=20V, VOUT= 5V, fs = 300kHz, L=47uH, Co=22uF/10mΩ Ω
50
Buck Converter with Voltage Mode and Type III Compensator L: 47uH, 0.25Ω Ω
Q1
VIN 20V
RESR 5mΩ Ω +
D
Co 22µ µF
VO
R C3: 10p
Ton D= Ts
VIN 10 Gate driver
R2: 23.2k C1:1.5n
+ PWM Comparator
VC
C2 1n
R1 30.9k
R3 1.15k
A(S) +
VREF + 0.7V
Rx 4.99k
51
Pspice Simulation Schematic PWM small signal average model
PWM gain Loop gain test perturbation
Type III Compensator 52
Simulation and Test Results PSPICE Simulation Results 0.3
3.5 Output Voltage Load Current
0.2
3 2.5
VOUT
0.0
2
-0.1
1.5
IOUT
-0.2
1
-0.3
0.5
-0.4
0
-0.5
-0.5 0
40
80
Load Current (A)
0.1 Output Voltage (V)
Test Results
VOUT IOUT
120 160 200 240 280 320 360 400 Time (us)
Load Step Transient: 0.4A to 0.8A
53
Simulation and Test Results Test Results
1.0
3.5
0.5
3
VOUT
0.0
2.5
-0.5
Output Voltage Load Current
IOUT
-1.0
2 1.5
-1.5
1
-2.0
0.5
-2.5
0
-3.0
-0.5 0
Load Current (A)
Output Voltage (V)
PSPICE Simulation Results
100 200 300 400 500 600 700 800 900 1000 Time (us)
Load Step Transient: 0.1A to 1.5A 54
Loop Bandwidth Simulation: Mathcad and Pspice Mathcad 60
Pspice 60
50
Bandwidth 35kHz
40
Bandwidth 45kHz
20
0
0
gain(Tv( S( fi) ) )
-20 50
-40
− 80 100 100 0
3
4
1 .10
5
1 .10 f( fi)
6
1 .10
1 .10 6
-60 1.0E+02
1.0E+03
1.0E+04
1.0E+05
1.0E+06
1.0E+04
1.0E+05
1.0E+06 55
1×10
0
0
Phase Margin 65 degree
50
-50
phase( Tv( S( fi) ) ) − 180
-100
100
150
-150
-180
− 200 200 10 10
100
3
4
1 .10
1 .10 f ( fi)
5
1 .10
6
1 .10 6 1×10
Phase Margin 70 degree
-200 1.0E+02
1.0E+03
Thanks!
Current Mode Loop Compensator Design will be next time
56
