Can Pin Access Limit the Footprint Scaling
Designing VeSFET-based ICs with CMOS-oriented EDA Infrastructure
Xiang Qiu, Malgorzata Marek-Sadowska University of California, Santa Barbara Wojciech Maly Carnegie Mellon University
Outline Introduction Chain Canvas Standard cell based physical design flow Chain Canvas Vs. Basic Canvas Conclusions
2
Introduction Semiconductor markets are dominated by
ASICs: high NRE cost, high performance, high volume. FPGAs: low NRE cost, low performance, small volume
Medium volume?
VeSFET-based ASICs may fill the gap between ASICs and FPGAs. [1][2]
New technology huge efforts on design automation infrastructure. Can we re-use CMOS EDA infrastructure for VeSFETbased designs?
We focus on physical design flow in this talk.
[1] W. Maly, et. al, “Complementary Vertical Slit Field Effect Transistors,” CMU, CSSI Tech-Report , 2008. [2] Y.-W. Lin, M. Marek-Sadowska, W. Maly, A. Pfitzner, and D. Kasprowicz, “Is there always performance overhead for regular canvas?” in Proceedings of ICCD’08, pp. 557-562, 2008.
3
Vertical Slit Field Effect Transistor 3D twin-gate transistor[1]
easy fabrication with SOI-like process
Excellent electrical characteristics[2]
huge Ion/Ioff: 1e9 low DIBL: 13mV/V near ideal subthreshold swing: 65mV/decade low gate capacitance 65nm VeSFET
r=50nm h=200nm tox=4nm Nsub= 4e17/cm3 VeSFET Structure[1] [1]. W. Maly, et. al, “Complementary Vertical Slit Field Effect Transistors,” CMU, CSSI Tech-Report , 2008. [2]. W. Maly, et. al, “Twin gate, vertical slit FET (VeSFET) for highly periodic layout and 3D integration,” in Proc. of MIXDES’11, pp.145-150, 2011.
4
VeSFET based-IC Paradigm Regular layout patterns
Canvases: geometrically identical VeSFETs arrays
Circuits are customized by interconnects
The same radius r and height h Strictly parallel wires Diagonal (45- or 135-degree) wires
Advanced layout style: pillar sharing shared pillars
basic canvas
A
VDD
B
VDD
O
A
O
B
A
n1
B
O
GND
A
n1
B
2-input NAND 5
Chain Canvases Transistors are rotated by 45 degrees Each pillar is shared by two transistors
Transistors are chained 2X transistor density
The same interconnect design rules
6
Transistor Isolation Some contacted transistors are unwanted. Isolation
1
Physical Electrical
A
Apply cut-off voltage Short drain and source
T1 2
T2 4
A
X
X A
B
1
B
B
X
B
T1
Tp
T2
B
1
2
1 X
4
A
A
DP 1
Tp 3
3
2
1
A
X/X
B
Wasted area!
2
3
A
4
3 B
7
Static CMOS-like Standard Cell Generation CMOS-like layout patterns
aligned gate pillars connected by wires aligned poly gates shared drain/source pillars diffusion abutment
CMOS cell generation algorithms can be reused. vdd
A vdd O
vdd
vdd
vdd
B vdd
O A
B gnd
O A
gnd A
B
2-input NAND
gnd
B gnd
gnd 8
Static CMOS-like Standard Cell Generation Transistor isolation Diffusion break Sizing by transistor duplication Transistor size => effective transistor density
vdd A
vdd
easier cell generation shorter wires
vdd B vdd
O
A
Vs. Basic Canvas cells
vdd
vdd
B vdd
O A
B gnd
O
A
B
gnd
O A gnd CMOS diffusion break
VeSFET transistor isolation
B
gnd
gnd
2-input NANDX2
9
Row-based Standard Cell Placement Similar to CMOS standard cell placement. Neighboring rows share power/ground lines. Power/ground lines are also for transistor isolation. shared ground line S/FS shared power line N/FN shared ground line 10
Inter-cell Routing Two disjoint routing grids
Vias aligned with pillars: D/S pillars cannot connect to G pillars by only H/V wires Jumper wires: diagonal wires bridging D/S- and G-grids.
Most inter-cell nets have both D/S pins and G pins.
Routing each single net on both grids may need multi layers of jumper wires Route each net on only one grid, only one layer of jumper wires
Jumper wires
Greedy net partitioning
Balance routing demands Balance pin density.
11
Cell Level Comparison Design INV, BUF, NAND2, NOR2, AOI21, OAI21 on both canvases Design 1X, 2X, 4X cells for each logic
More pillar sharing more area saving
Greater gate size More gate inputs Table 1. # of pillars occupied by cells mapped on BC and CC CELL INV BUF NAND2 NOR2 AOI21 OAI21 AVG
1X 8 16 16 16 24 24 1
Basic Canvas 2X 4X 16 32 32 64 32 64 32 64 48 96 48 96 1 1
1X 12 18 18 18 24 24 1.15
Chain Canvas 2X 4X 18 30 30 54 30 54 30 54 40 72 40 72 0.93 0.83
12
Cell Level Comparison (Cont.) Chain canvas
shorter wires fewer vias gate size , improvement
basic canvas
basic canvas
chain canvas
1.2
1.2
1
1
0.8
0.8
0.6
0.6
0.4
0.4
0.2
0.2
0
0 1X 2X 4X Average intra-cell wire length
chain canvas
1X 2X 4X Average intra-cell via count 13
Cell Level Comparison (Cont.) Performance and power comparison
Smaller parasitic RC for CC-based cells. Determine the frequency and power delay product (PDP) of a 5stage ring oscillator. basic canvas
basic canvas
chain canvas
chain canvas
1.2
1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0
1
0.8 0.6 0.4 0.2 0 1X 2X 4X Average RO frequency
1X
2X
4X
Average RO PDP 14
Circuit Level Comparison LGSynth91 benchmarks with thousands of gates
Mapped with a library of 6 1X cells(INV, BUF, NAND2, NOR2, AOI21, OAI21). CC-G: G-grid only routing CC-G/DS: nets evenly spread on both grids. BC
8 7 6 5 4 3 2 1 0
CC-G
CC-G/DS
1.2
1.1 1 0.9 0.8 0.7
0.6 # metal layers
area
wire length
# VIAs 15
Circuit Level Comparison (Cont.) Static timing analysis
non-linear delay model for each cell. parasitic inter-cell interconnect RC extracted by Star-RC.
Power estimation
Total interconnect capacitance BC
CC-G
CC-G/DS
1 0.95 0.9 0.85 0.8 0.75 0.7 0.65 0.6 longest path delay
total interconnect capacitance
16
Conclusions We propose chain canvases,
CMOS ASIC EDA infrastructure re-usable. 2X transistor density. Transistor isolation reduces transistor utilization. Transistor utilization improves as gate size increases.
Chain canvases Vs. Basic Canvases
Easier cell generation better routability smaller parasitic capacitance better performance lower power consumption slightly greater footprint area using unit size gates
17
Thank you!
Q&A
18
Xiang Qiu, Malgorzata Marek-Sadowska University of California, Santa Barbara Wojciech Maly Carnegie Mellon University
Outline Introduction Chain Canvas Standard cell based physical design flow Chain Canvas Vs. Basic Canvas Conclusions
2
Introduction Semiconductor markets are dominated by
ASICs: high NRE cost, high performance, high volume. FPGAs: low NRE cost, low performance, small volume
Medium volume?
VeSFET-based ASICs may fill the gap between ASICs and FPGAs. [1][2]
New technology huge efforts on design automation infrastructure. Can we re-use CMOS EDA infrastructure for VeSFETbased designs?
We focus on physical design flow in this talk.
[1] W. Maly, et. al, “Complementary Vertical Slit Field Effect Transistors,” CMU, CSSI Tech-Report , 2008. [2] Y.-W. Lin, M. Marek-Sadowska, W. Maly, A. Pfitzner, and D. Kasprowicz, “Is there always performance overhead for regular canvas?” in Proceedings of ICCD’08, pp. 557-562, 2008.
3
Vertical Slit Field Effect Transistor 3D twin-gate transistor[1]
easy fabrication with SOI-like process
Excellent electrical characteristics[2]
huge Ion/Ioff: 1e9 low DIBL: 13mV/V near ideal subthreshold swing: 65mV/decade low gate capacitance 65nm VeSFET
r=50nm h=200nm tox=4nm Nsub= 4e17/cm3 VeSFET Structure[1] [1]. W. Maly, et. al, “Complementary Vertical Slit Field Effect Transistors,” CMU, CSSI Tech-Report , 2008. [2]. W. Maly, et. al, “Twin gate, vertical slit FET (VeSFET) for highly periodic layout and 3D integration,” in Proc. of MIXDES’11, pp.145-150, 2011.
4
VeSFET based-IC Paradigm Regular layout patterns
Canvases: geometrically identical VeSFETs arrays
Circuits are customized by interconnects
The same radius r and height h Strictly parallel wires Diagonal (45- or 135-degree) wires
Advanced layout style: pillar sharing shared pillars
basic canvas
A
VDD
B
VDD
O
A
O
B
A
n1
B
O
GND
A
n1
B
2-input NAND 5
Chain Canvases Transistors are rotated by 45 degrees Each pillar is shared by two transistors
Transistors are chained 2X transistor density
The same interconnect design rules
6
Transistor Isolation Some contacted transistors are unwanted. Isolation
1
Physical Electrical
A
Apply cut-off voltage Short drain and source
T1 2
T2 4
A
X
X A
B
1
B
B
X
B
T1
Tp
T2
B
1
2
1 X
4
A
A
DP 1
Tp 3
3
2
1
A
X/X
B
Wasted area!
2
3
A
4
3 B
7
Static CMOS-like Standard Cell Generation CMOS-like layout patterns
aligned gate pillars connected by wires aligned poly gates shared drain/source pillars diffusion abutment
CMOS cell generation algorithms can be reused. vdd
A vdd O
vdd
vdd
vdd
B vdd
O A
B gnd
O A
gnd A
B
2-input NAND
gnd
B gnd
gnd 8
Static CMOS-like Standard Cell Generation Transistor isolation Diffusion break Sizing by transistor duplication Transistor size => effective transistor density
vdd A
vdd
easier cell generation shorter wires
vdd B vdd
O
A
Vs. Basic Canvas cells
vdd
vdd
B vdd
O A
B gnd
O
A
B
gnd
O A gnd CMOS diffusion break
VeSFET transistor isolation
B
gnd
gnd
2-input NANDX2
9
Row-based Standard Cell Placement Similar to CMOS standard cell placement. Neighboring rows share power/ground lines. Power/ground lines are also for transistor isolation. shared ground line S/FS shared power line N/FN shared ground line 10
Inter-cell Routing Two disjoint routing grids
Vias aligned with pillars: D/S pillars cannot connect to G pillars by only H/V wires Jumper wires: diagonal wires bridging D/S- and G-grids.
Most inter-cell nets have both D/S pins and G pins.
Routing each single net on both grids may need multi layers of jumper wires Route each net on only one grid, only one layer of jumper wires
Jumper wires
Greedy net partitioning
Balance routing demands Balance pin density.
11
Cell Level Comparison Design INV, BUF, NAND2, NOR2, AOI21, OAI21 on both canvases Design 1X, 2X, 4X cells for each logic
More pillar sharing more area saving
Greater gate size More gate inputs Table 1. # of pillars occupied by cells mapped on BC and CC CELL INV BUF NAND2 NOR2 AOI21 OAI21 AVG
1X 8 16 16 16 24 24 1
Basic Canvas 2X 4X 16 32 32 64 32 64 32 64 48 96 48 96 1 1
1X 12 18 18 18 24 24 1.15
Chain Canvas 2X 4X 18 30 30 54 30 54 30 54 40 72 40 72 0.93 0.83
12
Cell Level Comparison (Cont.) Chain canvas
shorter wires fewer vias gate size , improvement
basic canvas
basic canvas
chain canvas
1.2
1.2
1
1
0.8
0.8
0.6
0.6
0.4
0.4
0.2
0.2
0
0 1X 2X 4X Average intra-cell wire length
chain canvas
1X 2X 4X Average intra-cell via count 13
Cell Level Comparison (Cont.) Performance and power comparison
Smaller parasitic RC for CC-based cells. Determine the frequency and power delay product (PDP) of a 5stage ring oscillator. basic canvas
basic canvas
chain canvas
chain canvas
1.2
1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0
1
0.8 0.6 0.4 0.2 0 1X 2X 4X Average RO frequency
1X
2X
4X
Average RO PDP 14
Circuit Level Comparison LGSynth91 benchmarks with thousands of gates
Mapped with a library of 6 1X cells(INV, BUF, NAND2, NOR2, AOI21, OAI21). CC-G: G-grid only routing CC-G/DS: nets evenly spread on both grids. BC
8 7 6 5 4 3 2 1 0
CC-G
CC-G/DS
1.2
1.1 1 0.9 0.8 0.7
0.6 # metal layers
area
wire length
# VIAs 15
Circuit Level Comparison (Cont.) Static timing analysis
non-linear delay model for each cell. parasitic inter-cell interconnect RC extracted by Star-RC.
Power estimation
Total interconnect capacitance BC
CC-G
CC-G/DS
1 0.95 0.9 0.85 0.8 0.75 0.7 0.65 0.6 longest path delay
total interconnect capacitance
16
Conclusions We propose chain canvases,
CMOS ASIC EDA infrastructure re-usable. 2X transistor density. Transistor isolation reduces transistor utilization. Transistor utilization improves as gate size increases.
Chain canvases Vs. Basic Canvases
Easier cell generation better routability smaller parasitic capacitance better performance lower power consumption slightly greater footprint area using unit size gates
17
Thank you!
Q&A
18
