Caution: Speed Trap Ahead
Caution: Speed Trap Ahead by Mark Morgan High Speed Interconnect Design Manager, Interface Products Group Member Group Technical Staff, Texas Instruments Incorporated Designers using interface products such as low voltage differential signaling (LVDS) or positive/pseudo emitter-coupled logic (PECL) line drivers and receivers will find manufacturers often specify a maximum operating frequency (FMAX). Different criteria are used to specify this based on vendor-specific assumptions, which make it difficult for designers to compare devices. For example, input signal content and output loading can all contribute to very different conclusions. Peak-to-peak jitter, output transition time, and output signal amplitude are among the key factors the designer should consider in selecting an interface device in order to meet the system signaling requirements. This article discusses how these critical performance parameters determine how fast a device will operate in a specific application. The goal is to allow a designer to substantiate claims made on data sheets from different vendors and allow a comparison beyond headline speed claims to determine which device meets the speed requirements.
Circuit Limitations An amplifier’s maximum switching frequency is dictated by its design. As the input signal frequency is increased, a driver or receiver will continue to switch and track the input until reaching a maximum frequency. At this point, the amplifier is no longer able to toggle because the required gain is not available. The Bode plot (Fig. 1) illustrates amplifier gain and demonstrates a distinct roll off at some critical frequency.
Fig. 1: Bode Plot of Amplifier Performance Vs. Frequency
Circuit designers use an array of tools to increase an amplifier’s gain-bandwidth product and maximize the device’s FMAX. These include circuit topology, component sizing, increased power consumption and use of advanced high-speed process technologies. Designing with bipolar transistors in a silicon germanium process is one way to maximize the high-frequency circuit gain. To evaluate device circuit performance, the test conditions must be examined. Testing a device under optimum conditions can mask circuit limitations. Critical parameters suffer, even though the device appears functional. Following is a discussion of output amplitude, transition time and jitter, and the impact different test techniques have on circuit performance.
Output Amplitude Output amplitude is the device’s level of output signal strength. For example, LVDScompliant drivers maintain a differential voltage of 247 mV to 454 mV across 100 Ω. The TIA/EIA-644-A standard specifies this range to ensure compatibility between LVDS suppliers. A designer is ultimately interested in the output amplitude guaranteed over all operating points of process, temperature, supply voltage and frequency. As previously discussed, amplifier gains decline with increasing frequency. As a result the output amplitude begins to decrease and disappear altogether with further increase in frequency. In a differential driver the output differential amplitude begins to decline below an acceptable level. To counter this the amplifier demands higher input amplitude to maintain the output signal amplitude. 400
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Fig. 2: SN65LVDS100 Output Voltage Vs. Frequency Many times the frequency dependency on output amplitude is not captured in vendor datasheet speed claims. A device may continue to toggle at the advertised speed, but with an unacceptable output voltage. Obviously, as the output begins to decline, lower noise
margin is available and less attenuation can be tolerated along the transmission media. This falloff in output signal limits the distance one can drive a transmission media and maintain sufficient signal strength due to the attenuation characteristics of the media. However, a user can live with a smaller output signal when driving shorter distances or using a more sensitive receiver. The point to remember, when comparing maximum operating frequency across devices, is to consider the output amplitude. Fig. 2 demonstrates the output voltage of the SN65LVDS100 Vs. frequency and illustrates the output voltage roll-off of the amplifier when operated beyond its specified range.
Transition time limitations Transition time is defined as the time interval a data signal requires to change states and is a critical parameter to consider when determining top speed capability. This parameter is typically measured from the 10% to 90% point on the output waveform. W hen determining acceptable performance, engineers often compare transition time to the unit interval of one data bit in order to identify a benchmark. For example, the unit interval (UI) of data transmitted at 1 Gbit/s is 1 ns (1/1 Gbit/s). A device operating at this signaling rate, with an output signal rise time of 300 ps, would have a transition time of 30% UI. Comparing data sheets from different vendors, one will find ratios ranging from 30 to 50%. Consideration must be given to this figure of merit to determine how much of the UI valid data is required. For example, a device may switch at a given rate but if the output waveform resembles a triangular wave it may be beyond its usable range.
Fig. 3: SN65LVDS100 Typical Eye Diagram
Slow output rise times degrade the setup and hold time placed on the system and subtract from the time valid data can be guaranteed. The eye diagram in Fig. 3 illustrates the SN65LVDS100 running at 1.25 Gbit/s. From the eye-diagram, the total UI percentage consumed by the 10 to 90% transition is 190 ps, or roughly 20% of the unit interval. A driver transmitting random data can experience output eye degradation due to transition time limitations. As frequency increases and amplifier gain rolls off, circuit nodes no longer achieve their maximum voltage swing. When input data is composed of long strings of zeros followed by a single one (ex. 000001000001), the amplifier cannot fully switch to a one before the next zero arrives. During the subsequent high-to-low transition, the time to reach the differential output crossing point is faster because the start of the transition is at a lower voltage. In contrast, when an input is composed of a static string of ones followed by a string of zeros (ex. 000111000), internal nodes have sufficient time to reach their maximum value. Here, the time to reach the output crossing point will be longer as the internal node is now starting at the maximum switched voltage.
Fig. 4: LVDS125 Transition Rate Effects This is demonstrated during the transition points in Fig. 4 using the SN65LVDS125. The transition’s bimodal characteristic clearly demonstrates both cases. The longer transition occurs after a string of consecutive ones before switching to a zero. Note the higher starting voltage before the transition. In contrast a 010 bit pattern can be observed where the one state does not fully slew to the maximum output voltage so the subsequent falling edge reaches the zero crossing point faster than those starting from a higher voltage. At higher frequencies this phenomenon becomes worse as the single bit transition has even less time to achieve full amplitude. This increased width, observed as a double falling edge in the eye diagram, directly adds to the device’s total jitter.
Output loading The device’s output transition time can be extremely dependant on the type of load. Rarely are test circuits standardized between IC vendors. Some use a single capacitor load while others use a capacitor to represent the distributed capacitance of the test equipment environment. One way to reduce the test uncertainties is to use the same test board for two devices with the same pinout. This is usually only an option for multisourced pin-compatible devices. High speed LVDS differential outputs in the multigigabit range of operation can see considerable shifts in performance with as little as 1 pF additional load.
Jitter Jitter is a major concern when determining the FMAX of a device. Jitter is commonly defined as the deviation of an event from its ideal time and is the total sum of skew, pattern-dependant interference, and noise that degrades signal quality. Jitter is composed of two parts: Deterministic and random jitter. Adding the components together results in total peak-to-peak jitter. Random jitter follows a Gaussian probability distribution. Deterministic jitter consists of many sources and includes duty cycle distortion or pulse skew, pattern-dependent jitter or Intersymbol interference (ISI), and crosstalk. The total peak-to-peak jitter is a direct function of the input data format. Clock signals show random jitter components in addition to pulse skew, one component of deterministic jitter. Changing the input to random data will introduce ISI, the patterndependent component of deterministic jitter. Total peak-to-peak jitter is a common way to define jitter performance for interface devices. This is observed as the width of the crossing point in an eye diagram (Fig. 3, again). As in the previous rise time calculations, jitter can be expressed as a percentage of the UI. Using the previous example of a 1 ns UI (1 Gbit/s data rate), total peak to peak jitter of 100 ps corresponds to 10% of the UI. This is another area where IC vendors differ greatly. Two devices specified at maximum operating data rates of 1 Gbit/s, the first with 10% UI total jitter and the second with 20% UI total jitter, do not have the same performance. Obviously, the less the total jitter degrades the eye opening, the more timing margin is available. Since ISI increases proportional to frequency, one would expect that total jitter would also follow the same relationship which is shown in Fig. 5, demonstrated with the SN65LVDS122. Note the jitter acceleration above 2.5 Gbit/s. To accurately compare jitter performance between multiple devices, the same frequency of operation should be used.
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Fig. 5: SN65LVDS122 Pk-Pk Jitter Vs. Data Rate
How jitter is affected by the input The amount of peak-to-peak jitter observed in an eye diagram is directly dependent on the input data pattern. Random jitter plus pulse skew is observed by using a clock input source. Because of the periodic nature of the input the pattern-dependent sources of jitter are not present. Changing the input data format to a PRBS introduces ISI components and increases the overall total jitter. Because data-dependent jitter can introduce long periods of ones or zeros the recovery time for internal circuit nodes will be different compared to a periodic waveform. Increasing the number of static bits will make the jitter worse. It is meaningless to compare the performance of one device using a clock input and another using PRBS input format. When comparing PRBS performance it is important to specify both devices with the same type of random input data stream. Total jitter is also a function of input signal amplitude. At low speeds a differential receiver will switch on a minimum input voltage, for example 100 mV. This level of signal provides enough overdrive to allow a device to switch between states during one UI. As the frequency of operation increases, the data-dependent jitter increases once the amplifier is no longer operating in the flat part of its gain curve. To counter this a larger input signal can be used to provide more circuit overdrive, negating the gain degradation. Therefore, comparing total jitter at top speed with different input signal amplitudes may lead to very different results.
Internal Crosstalk Channel-to-channel crosstalk can be a significant source of jitter when comparing multichannel devices. Parasitic capacitance and inductance are inherent in the silicon and
couple signals from one channel to another. Bondwire and metal routing inductance cause disturbances on the power bus during transitions. Because adjacent channels often share the same metal bus, switching currents from one channel may disturb the adjacent channel. When one channel switches ground bounce on the common ground disturbs the other circuit’s switch point. There are numerous methods of reducing circuit inductance to help minimize crosstalk. These include wide bus metal routing, multiple bond-wire or bond-wire-free packaging such as flip chip QFN packages. Since crosstalk adds directly to peak-to-peak jitter all channels should be operational during testing. A multi-channel part might have a high single channel signaling rate supported by a 30% UI rise time and 10% UI jitter number, but if operating the remaining channels causes a significant increase in jitter, the maximum operating frequency may have to be reduced. A device with unused channels inactive often has better jitter performance than running all channels at the FMAX rate. Fig. 6 shows crosstalk effect on performance using the SN65MLVD082 8-channel transceiver. The single-ended receiver output is shown with PRBS 2^23 -1 input data. The eye diagram (left) is the channel 1 output with all other channels inactive. That on the right shows channel 1 with all other channels active. Comparing both cases, the total jitter has increased from 100 ps with one channel active to 300 ps with all channels active. Although this performance meets datasheet specifications jitter due to on-chip crosstalk should be accounted for in performance evaluation. The worst case is usually when all channels are driven in phase with identical data. This results in the maximum switching current and subsequent supply disturbance, a major contributor to crosstalk.
Fig. 6: SN65MLVD082 Channel-To-Channel Crosstalk
Conclusions Speed claims on vendor data sheets are based on very different test conditions, making it difficult to compare different devices if a designer is not aware of the specific evaluation criteria. Circuit design and process technology determine amplifier bandwidth, but two identical devices can appear quite different under dissimilar test conditions. Devices can
be specified with FMAX numbers, which indicate they still toggle but with a large roll off in output signal amplitude. A device may continue to track the input, but with a slow transition time that consumes much of the valid data window. Total jitter is a key factor in the FMAX specification. And input data rate output loading and adjacent active channels have a major impact on the realized performance. Understanding the critical parameters and the effect of different testing methods is important for a user to successfully compare devices and choose the one that best meets the system requirements.
About The Author Mark Morgan is high-speed interconnect design manager in TI’s Interface Products group, and a member of TI’s Technical Staff. For the past five years he has managed a design group responsible for high-speed interface buffers and translators (PECL, CML and LVDS) for the telecommunications and data networking industry. He earned a BSEE from University of Wisconsin and a MSEE from Marquette University. With 20 years experience in the electronics industry, including the military, automotive and telecommunications fields, you may contact Mike at [email protected] For further information on TI's LVDS products visit their web site at: http://focus.ti.com/docs/search/paramsearch.jhtml?familyId=546&tfsection=param_table &templateId=5&showAssociated=false For further information on TI's overall interface products, visit their web site at: http://focus.ti.com/analog/docs/analogprodhome.tsp?templateId=5&navigationId=9630& familyId=361&path=templatedata/cm/overview/data/interface
Circuit Limitations An amplifier’s maximum switching frequency is dictated by its design. As the input signal frequency is increased, a driver or receiver will continue to switch and track the input until reaching a maximum frequency. At this point, the amplifier is no longer able to toggle because the required gain is not available. The Bode plot (Fig. 1) illustrates amplifier gain and demonstrates a distinct roll off at some critical frequency.
Fig. 1: Bode Plot of Amplifier Performance Vs. Frequency
Circuit designers use an array of tools to increase an amplifier’s gain-bandwidth product and maximize the device’s FMAX. These include circuit topology, component sizing, increased power consumption and use of advanced high-speed process technologies. Designing with bipolar transistors in a silicon germanium process is one way to maximize the high-frequency circuit gain. To evaluate device circuit performance, the test conditions must be examined. Testing a device under optimum conditions can mask circuit limitations. Critical parameters suffer, even though the device appears functional. Following is a discussion of output amplitude, transition time and jitter, and the impact different test techniques have on circuit performance.
Output Amplitude Output amplitude is the device’s level of output signal strength. For example, LVDScompliant drivers maintain a differential voltage of 247 mV to 454 mV across 100 Ω. The TIA/EIA-644-A standard specifies this range to ensure compatibility between LVDS suppliers. A designer is ultimately interested in the output amplitude guaranteed over all operating points of process, temperature, supply voltage and frequency. As previously discussed, amplifier gains decline with increasing frequency. As a result the output amplitude begins to decrease and disappear altogether with further increase in frequency. In a differential driver the output differential amplitude begins to decline below an acceptable level. To counter this the amplifier demands higher input amplitude to maintain the output signal amplitude. 400
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Fig. 2: SN65LVDS100 Output Voltage Vs. Frequency Many times the frequency dependency on output amplitude is not captured in vendor datasheet speed claims. A device may continue to toggle at the advertised speed, but with an unacceptable output voltage. Obviously, as the output begins to decline, lower noise
margin is available and less attenuation can be tolerated along the transmission media. This falloff in output signal limits the distance one can drive a transmission media and maintain sufficient signal strength due to the attenuation characteristics of the media. However, a user can live with a smaller output signal when driving shorter distances or using a more sensitive receiver. The point to remember, when comparing maximum operating frequency across devices, is to consider the output amplitude. Fig. 2 demonstrates the output voltage of the SN65LVDS100 Vs. frequency and illustrates the output voltage roll-off of the amplifier when operated beyond its specified range.
Transition time limitations Transition time is defined as the time interval a data signal requires to change states and is a critical parameter to consider when determining top speed capability. This parameter is typically measured from the 10% to 90% point on the output waveform. W hen determining acceptable performance, engineers often compare transition time to the unit interval of one data bit in order to identify a benchmark. For example, the unit interval (UI) of data transmitted at 1 Gbit/s is 1 ns (1/1 Gbit/s). A device operating at this signaling rate, with an output signal rise time of 300 ps, would have a transition time of 30% UI. Comparing data sheets from different vendors, one will find ratios ranging from 30 to 50%. Consideration must be given to this figure of merit to determine how much of the UI valid data is required. For example, a device may switch at a given rate but if the output waveform resembles a triangular wave it may be beyond its usable range.
Fig. 3: SN65LVDS100 Typical Eye Diagram
Slow output rise times degrade the setup and hold time placed on the system and subtract from the time valid data can be guaranteed. The eye diagram in Fig. 3 illustrates the SN65LVDS100 running at 1.25 Gbit/s. From the eye-diagram, the total UI percentage consumed by the 10 to 90% transition is 190 ps, or roughly 20% of the unit interval. A driver transmitting random data can experience output eye degradation due to transition time limitations. As frequency increases and amplifier gain rolls off, circuit nodes no longer achieve their maximum voltage swing. When input data is composed of long strings of zeros followed by a single one (ex. 000001000001), the amplifier cannot fully switch to a one before the next zero arrives. During the subsequent high-to-low transition, the time to reach the differential output crossing point is faster because the start of the transition is at a lower voltage. In contrast, when an input is composed of a static string of ones followed by a string of zeros (ex. 000111000), internal nodes have sufficient time to reach their maximum value. Here, the time to reach the output crossing point will be longer as the internal node is now starting at the maximum switched voltage.
Fig. 4: LVDS125 Transition Rate Effects This is demonstrated during the transition points in Fig. 4 using the SN65LVDS125. The transition’s bimodal characteristic clearly demonstrates both cases. The longer transition occurs after a string of consecutive ones before switching to a zero. Note the higher starting voltage before the transition. In contrast a 010 bit pattern can be observed where the one state does not fully slew to the maximum output voltage so the subsequent falling edge reaches the zero crossing point faster than those starting from a higher voltage. At higher frequencies this phenomenon becomes worse as the single bit transition has even less time to achieve full amplitude. This increased width, observed as a double falling edge in the eye diagram, directly adds to the device’s total jitter.
Output loading The device’s output transition time can be extremely dependant on the type of load. Rarely are test circuits standardized between IC vendors. Some use a single capacitor load while others use a capacitor to represent the distributed capacitance of the test equipment environment. One way to reduce the test uncertainties is to use the same test board for two devices with the same pinout. This is usually only an option for multisourced pin-compatible devices. High speed LVDS differential outputs in the multigigabit range of operation can see considerable shifts in performance with as little as 1 pF additional load.
Jitter Jitter is a major concern when determining the FMAX of a device. Jitter is commonly defined as the deviation of an event from its ideal time and is the total sum of skew, pattern-dependant interference, and noise that degrades signal quality. Jitter is composed of two parts: Deterministic and random jitter. Adding the components together results in total peak-to-peak jitter. Random jitter follows a Gaussian probability distribution. Deterministic jitter consists of many sources and includes duty cycle distortion or pulse skew, pattern-dependent jitter or Intersymbol interference (ISI), and crosstalk. The total peak-to-peak jitter is a direct function of the input data format. Clock signals show random jitter components in addition to pulse skew, one component of deterministic jitter. Changing the input to random data will introduce ISI, the patterndependent component of deterministic jitter. Total peak-to-peak jitter is a common way to define jitter performance for interface devices. This is observed as the width of the crossing point in an eye diagram (Fig. 3, again). As in the previous rise time calculations, jitter can be expressed as a percentage of the UI. Using the previous example of a 1 ns UI (1 Gbit/s data rate), total peak to peak jitter of 100 ps corresponds to 10% of the UI. This is another area where IC vendors differ greatly. Two devices specified at maximum operating data rates of 1 Gbit/s, the first with 10% UI total jitter and the second with 20% UI total jitter, do not have the same performance. Obviously, the less the total jitter degrades the eye opening, the more timing margin is available. Since ISI increases proportional to frequency, one would expect that total jitter would also follow the same relationship which is shown in Fig. 5, demonstrated with the SN65LVDS122. Note the jitter acceleration above 2.5 Gbit/s. To accurately compare jitter performance between multiple devices, the same frequency of operation should be used.
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Fig. 5: SN65LVDS122 Pk-Pk Jitter Vs. Data Rate
How jitter is affected by the input The amount of peak-to-peak jitter observed in an eye diagram is directly dependent on the input data pattern. Random jitter plus pulse skew is observed by using a clock input source. Because of the periodic nature of the input the pattern-dependent sources of jitter are not present. Changing the input data format to a PRBS introduces ISI components and increases the overall total jitter. Because data-dependent jitter can introduce long periods of ones or zeros the recovery time for internal circuit nodes will be different compared to a periodic waveform. Increasing the number of static bits will make the jitter worse. It is meaningless to compare the performance of one device using a clock input and another using PRBS input format. When comparing PRBS performance it is important to specify both devices with the same type of random input data stream. Total jitter is also a function of input signal amplitude. At low speeds a differential receiver will switch on a minimum input voltage, for example 100 mV. This level of signal provides enough overdrive to allow a device to switch between states during one UI. As the frequency of operation increases, the data-dependent jitter increases once the amplifier is no longer operating in the flat part of its gain curve. To counter this a larger input signal can be used to provide more circuit overdrive, negating the gain degradation. Therefore, comparing total jitter at top speed with different input signal amplitudes may lead to very different results.
Internal Crosstalk Channel-to-channel crosstalk can be a significant source of jitter when comparing multichannel devices. Parasitic capacitance and inductance are inherent in the silicon and
couple signals from one channel to another. Bondwire and metal routing inductance cause disturbances on the power bus during transitions. Because adjacent channels often share the same metal bus, switching currents from one channel may disturb the adjacent channel. When one channel switches ground bounce on the common ground disturbs the other circuit’s switch point. There are numerous methods of reducing circuit inductance to help minimize crosstalk. These include wide bus metal routing, multiple bond-wire or bond-wire-free packaging such as flip chip QFN packages. Since crosstalk adds directly to peak-to-peak jitter all channels should be operational during testing. A multi-channel part might have a high single channel signaling rate supported by a 30% UI rise time and 10% UI jitter number, but if operating the remaining channels causes a significant increase in jitter, the maximum operating frequency may have to be reduced. A device with unused channels inactive often has better jitter performance than running all channels at the FMAX rate. Fig. 6 shows crosstalk effect on performance using the SN65MLVD082 8-channel transceiver. The single-ended receiver output is shown with PRBS 2^23 -1 input data. The eye diagram (left) is the channel 1 output with all other channels inactive. That on the right shows channel 1 with all other channels active. Comparing both cases, the total jitter has increased from 100 ps with one channel active to 300 ps with all channels active. Although this performance meets datasheet specifications jitter due to on-chip crosstalk should be accounted for in performance evaluation. The worst case is usually when all channels are driven in phase with identical data. This results in the maximum switching current and subsequent supply disturbance, a major contributor to crosstalk.
Fig. 6: SN65MLVD082 Channel-To-Channel Crosstalk
Conclusions Speed claims on vendor data sheets are based on very different test conditions, making it difficult to compare different devices if a designer is not aware of the specific evaluation criteria. Circuit design and process technology determine amplifier bandwidth, but two identical devices can appear quite different under dissimilar test conditions. Devices can
be specified with FMAX numbers, which indicate they still toggle but with a large roll off in output signal amplitude. A device may continue to track the input, but with a slow transition time that consumes much of the valid data window. Total jitter is a key factor in the FMAX specification. And input data rate output loading and adjacent active channels have a major impact on the realized performance. Understanding the critical parameters and the effect of different testing methods is important for a user to successfully compare devices and choose the one that best meets the system requirements.
About The Author Mark Morgan is high-speed interconnect design manager in TI’s Interface Products group, and a member of TI’s Technical Staff. For the past five years he has managed a design group responsible for high-speed interface buffers and translators (PECL, CML and LVDS) for the telecommunications and data networking industry. He earned a BSEE from University of Wisconsin and a MSEE from Marquette University. With 20 years experience in the electronics industry, including the military, automotive and telecommunications fields, you may contact Mike at [email protected] For further information on TI's LVDS products visit their web site at: http://focus.ti.com/docs/search/paramsearch.jhtml?familyId=546&tfsection=param_table &templateId=5&showAssociated=false For further information on TI's overall interface products, visit their web site at: http://focus.ti.com/analog/docs/analogprodhome.tsp?templateId=5&navigationId=9630& familyId=361&path=templatedata/cm/overview/data/interface
