Cell-Aware Test
Transistor-level ATPG Targeting Cell-Internal Defects
Cell-Aware Test
Silicon Test and Yield Analysis
D A T A S H E E T FEATURES: • Enables full-chip transistor-level ATPG to directly target defects internal to library cells • Supports targeting both static and delay related defects • Supports targeting defects in both combinational and sequential cell types • Fully integrated into both Tessent FastScan and Tessent TestKompress ATPG flows
Cell-Aware test detects transistor-level defects for significant reductions in defective part levels.
Test Methodology for Detecting Transistor Level Defects The Tessent® Cell-Aware test methodology overcomes the limitations of traditional fault models and associated test patterns by targeting specific shorts, opens, and transistor defects internal to each standard cell, resulting in significant reductions in defective part (DPM) levels. Because the type and location of the defects are derived from the cell layout, cell-aware test provides the infrastructure for addressing new defect mechanisms in advanced technology, including FinFETs. Each cell is modeled at the transistor level and the effects of potential short and open defects are characterized through analog simulations. These simulations are used to generate a cell-aware model that directs ATPG to generate transistor-level test patterns targeting defects within each cell, as well as defects on the interconnect between cells.
Cell-Aware Fault Model Creation A Cell-Aware fault model is created for each unique technology library using the CellModelGen tool. The tool requires a transistor-level netlist with parasitics for each cell in the library as input. If not readily available, the netlist can be extracted from each cell’s GDS2 layout using Calibre, or another extraction tool. CellModelGen uses the transistors, parasitic capacitors, resistors, and ports to identify the location of possible transistor, bridge, open, and port defects. Analog simulation is then performed using Eldo or other Spice circuit simulator to generate the Cell-Aware model. The analog simulation iteratively modifies each transistor and parasitic element in the netlist, simulates all possible cell input combinations, and compares the results to the fault-free analog simulation to conclude if the inserted defect is detected or not. Both single and dual-cycle analog fault simulation is performed in order to detect both static and delay-related defects.
w w w. m e nto r. co m /si li co n -y i e l d
• Fully compatible with all Tessent Hierarchical ATPG features • Fully compatible with yield diagnosis and analysis tools: Tessent Diagnosis and Tessent YieldInsight® • Award-winning technology: 2013 Test & Measurement World’s “Bestin-Test”
BENEFITS: • Enables significant improvements in product quality levels without large increases in test costs • Provides full chip infrastructure for addressing any new defect mechanisms in leading edge technology nodes • Well suited for FinFET defect learning and detection • Mentor Graphics award- winning Consulting Services available for maximum success
The final step is to convert the list of input combinations into a set of necessary input values and conditions for each fault within each cell. Because this fault information is defined at the cell inputs as logic values, it is basically a logic fault model representation of the analog defect simulation. This set of stimulus for each cell represents the Cell-Aware fault model file for ATPG. Within this file, a simulated defect (now a fault) can have one or more input combinations.
Cell-Aware Defect Coverage Improvement in defect coverage with Cell-Aware testing can be analyzed at the cell level. The graph below illustrates the deficiency of state-of-the-art stuck-at and transition patterns. The x-axis represents all of the cells within a given technology library, ordered by coverage results. The y-axis represents the cell-internal defect coverage rates in percent as follows: The (middle) blue line shows coverage with stuck-at patterns, which is less than 100% for about half of the cells. The (bottom) pink line shows coverage with transition patterns, where only about 20% of the cells reach maximum defect coverage. The (top) green line shows the coverage with Cell-Aware slow-speed and at-speed patterns, which is always 100%.
improvement is highly design-dependent, but silicon results collected so far across multiple designs and technology nodes indicates DPM reductions in the tens to hundreds of points.
Cell-Aware Test Generation Flow The Cell-Aware test pattern generation flow is very similar to the traditional flow. Both Tessent FastScan and Tessent TestKompress are supported and use all of the same inputs (ATPG library, DoFiles, etc). The only difference is that the Cell-Aware fault model file created by CellModelGen must also be provided as input. The recommended flow is to first target the Cell-Aware faults and then to target other desired standard fault models (stuck-at, transition, etc) for any necessary top-off coverage. This ensures coverage of all desired fault models with the minimum number of patterns.
Product Requirements ATPG support for Cell-Aware fault models is included in with Tessent FastScan and Tessent TestKompress. CellAware fault model files for specific technology libraries may be available from your library provider. Cell-Aware fault model file generation is also offered as a service by Mentor Consulting, or can be user-generated with Mentor’s CellModelGen tool included in Tessent TestKompress. Creation of the cell-aware fault model will also require access to Calibre and Eldo or similar layout extraction and analog simulation tools.
Tessent Silicon Test and Yield Analysis Solutions
Coverage of cell-internal defects for all cells in a library, by pattern type.
The defect coverage improvement with Cell-Aware test translates to improvements in chip DPM levels. The
Tessent FastScan and Tessent TestKompress are part of the Mentor Graphics industry- and technology-leading tool suite for silicon test and yield analysis. The Tessent suite includes integrated solutions for test insertion, automatic test pattern generation (ATPG), on-chip compression, memory, logic, and mixed-signal built-in self-test (BIST), silicon bring-up, and diagnosis-driven yield analysis. All Tessent tools are available on Linux.
For the latest product information, call us or visit: w w w . m e n t o r . c o m / s i l i c o n - y i e l d ©2014 Mentor Graphics Corporation, all rights reserved. This document contains information that is proprietary to Mentor Graphics Corporation and may be duplicated in whole or in part by the original recipient for internal business purposes only, provided that this entire notice appears in all copies. In accepting this document, the recipient agrees to make every reasonable effort to prevent unauthorized use of this information. All trademarks mentioned in this document are the trademarks of their respective owners.
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Cell-Aware Test
Silicon Test and Yield Analysis
D A T A S H E E T FEATURES: • Enables full-chip transistor-level ATPG to directly target defects internal to library cells • Supports targeting both static and delay related defects • Supports targeting defects in both combinational and sequential cell types • Fully integrated into both Tessent FastScan and Tessent TestKompress ATPG flows
Cell-Aware test detects transistor-level defects for significant reductions in defective part levels.
Test Methodology for Detecting Transistor Level Defects The Tessent® Cell-Aware test methodology overcomes the limitations of traditional fault models and associated test patterns by targeting specific shorts, opens, and transistor defects internal to each standard cell, resulting in significant reductions in defective part (DPM) levels. Because the type and location of the defects are derived from the cell layout, cell-aware test provides the infrastructure for addressing new defect mechanisms in advanced technology, including FinFETs. Each cell is modeled at the transistor level and the effects of potential short and open defects are characterized through analog simulations. These simulations are used to generate a cell-aware model that directs ATPG to generate transistor-level test patterns targeting defects within each cell, as well as defects on the interconnect between cells.
Cell-Aware Fault Model Creation A Cell-Aware fault model is created for each unique technology library using the CellModelGen tool. The tool requires a transistor-level netlist with parasitics for each cell in the library as input. If not readily available, the netlist can be extracted from each cell’s GDS2 layout using Calibre, or another extraction tool. CellModelGen uses the transistors, parasitic capacitors, resistors, and ports to identify the location of possible transistor, bridge, open, and port defects. Analog simulation is then performed using Eldo or other Spice circuit simulator to generate the Cell-Aware model. The analog simulation iteratively modifies each transistor and parasitic element in the netlist, simulates all possible cell input combinations, and compares the results to the fault-free analog simulation to conclude if the inserted defect is detected or not. Both single and dual-cycle analog fault simulation is performed in order to detect both static and delay-related defects.
w w w. m e nto r. co m /si li co n -y i e l d
• Fully compatible with all Tessent Hierarchical ATPG features • Fully compatible with yield diagnosis and analysis tools: Tessent Diagnosis and Tessent YieldInsight® • Award-winning technology: 2013 Test & Measurement World’s “Bestin-Test”
BENEFITS: • Enables significant improvements in product quality levels without large increases in test costs • Provides full chip infrastructure for addressing any new defect mechanisms in leading edge technology nodes • Well suited for FinFET defect learning and detection • Mentor Graphics award- winning Consulting Services available for maximum success
The final step is to convert the list of input combinations into a set of necessary input values and conditions for each fault within each cell. Because this fault information is defined at the cell inputs as logic values, it is basically a logic fault model representation of the analog defect simulation. This set of stimulus for each cell represents the Cell-Aware fault model file for ATPG. Within this file, a simulated defect (now a fault) can have one or more input combinations.
Cell-Aware Defect Coverage Improvement in defect coverage with Cell-Aware testing can be analyzed at the cell level. The graph below illustrates the deficiency of state-of-the-art stuck-at and transition patterns. The x-axis represents all of the cells within a given technology library, ordered by coverage results. The y-axis represents the cell-internal defect coverage rates in percent as follows: The (middle) blue line shows coverage with stuck-at patterns, which is less than 100% for about half of the cells. The (bottom) pink line shows coverage with transition patterns, where only about 20% of the cells reach maximum defect coverage. The (top) green line shows the coverage with Cell-Aware slow-speed and at-speed patterns, which is always 100%.
improvement is highly design-dependent, but silicon results collected so far across multiple designs and technology nodes indicates DPM reductions in the tens to hundreds of points.
Cell-Aware Test Generation Flow The Cell-Aware test pattern generation flow is very similar to the traditional flow. Both Tessent FastScan and Tessent TestKompress are supported and use all of the same inputs (ATPG library, DoFiles, etc). The only difference is that the Cell-Aware fault model file created by CellModelGen must also be provided as input. The recommended flow is to first target the Cell-Aware faults and then to target other desired standard fault models (stuck-at, transition, etc) for any necessary top-off coverage. This ensures coverage of all desired fault models with the minimum number of patterns.
Product Requirements ATPG support for Cell-Aware fault models is included in with Tessent FastScan and Tessent TestKompress. CellAware fault model files for specific technology libraries may be available from your library provider. Cell-Aware fault model file generation is also offered as a service by Mentor Consulting, or can be user-generated with Mentor’s CellModelGen tool included in Tessent TestKompress. Creation of the cell-aware fault model will also require access to Calibre and Eldo or similar layout extraction and analog simulation tools.
Tessent Silicon Test and Yield Analysis Solutions
Coverage of cell-internal defects for all cells in a library, by pattern type.
The defect coverage improvement with Cell-Aware test translates to improvements in chip DPM levels. The
Tessent FastScan and Tessent TestKompress are part of the Mentor Graphics industry- and technology-leading tool suite for silicon test and yield analysis. The Tessent suite includes integrated solutions for test insertion, automatic test pattern generation (ATPG), on-chip compression, memory, logic, and mixed-signal built-in self-test (BIST), silicon bring-up, and diagnosis-driven yield analysis. All Tessent tools are available on Linux.
For the latest product information, call us or visit: w w w . m e n t o r . c o m / s i l i c o n - y i e l d ©2014 Mentor Graphics Corporation, all rights reserved. This document contains information that is proprietary to Mentor Graphics Corporation and may be duplicated in whole or in part by the original recipient for internal business purposes only, provided that this entire notice appears in all copies. In accepting this document, the recipient agrees to make every reasonable effort to prevent unauthorized use of this information. All trademarks mentioned in this document are the trademarks of their respective owners.
MGC 09-13
1031410-w
