Chip-to-Wafer Technologies for High Density 3D Integration - SET ...
2007
Chip-to-Wafer Technologies for High Density 3D Integration CEA Leti Minatec Campus, STMicroelectronics, SET, CNRS Cemes, Air Liquide Electonics Systems May 11, 2011
A collaborative work CEA Leti Minatec Campus: T. Signamarcheix, L. Bally, L. Sanchez, M. Francou, S. Verrun, E. Augendre, L. Di Cioccio, V. Carron, C. Deguet and N. Sillon STMicroelectronics: R. Taibi, A. Delolme, A. Farcy and B. Descouts 2007
SET: G. Lecarpentier CNRS Cemes: M. Legros and M. Martinez Air Liquide Electronics Systems: V. Lelievre © CEA 2011. All rights reserved Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
T. SIGNAMARCHEIX et al., MiNaPAD Forum, May 11 2011
2
Chip-to-Wafer Technologies for High Density 3D Integration
2007
Introduction gp process Direct Cu bonding SET FC300 with special design Alignment performance Electrical validation C Conclusions l i
© CEA 2011. All rights reserved Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
T. SIGNAMARCHEIX et al., MiNaPAD Forum, May 11 2011
3
3D assembly by chip or wafer stacking Multifunction devices ((heterogeneous g integration) g ) Repartitioning
2007
reduces area of individual chips (Yield improvement). reduces number of mask levels per die (Cost improvement). results in shorter g global interconnect lines ((Energy gy saving / performance improvement).
© CEA 2011. All rights reserved Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
T. SIGNAMARCHEIX et al., MiNaPAD Forum, May 11 2011
4
Chip-to-Wafer stacking through direct bonding Flexibilityy In size In technology gy / supplier pp
High yield Known good dies Good overlay 2007
Benefits of direct bonding Low pressure Low temperature No underfill even at high interconnect density © CEA 2011. All rights reserved Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
T. SIGNAMARCHEIX et al., MiNaPAD Forum, May 11 2011
5
Die-to-Wafer alignment chip
SiO2 Cu
wafer f
Damascene processing determines die and wafer surface topography.
2007
Cu surface is recessed (dishing). ( g) Both chip and wafer surfaces are activated prior to bonding. © CEA 2011. All rights reserved
Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
T. SIGNAMARCHEIX et al., MiNaPAD Forum, May 11 2011
6
Die-to-Wafer placement chip
SiO2 Cu
wafer f
Die is placed. 2007
Die is secured by direct SiO2- SiO2 bonding (low force force, room temperature) temperature). © CEA 2011. All rights reserved Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
T. SIGNAMARCHEIX et al., MiNaPAD Forum, May 11 2011
7
Die-to-Wafer interconnection chip
SiO2 Cu
wafer f
Cu - Cu direct bonding: 2007
occu s du occurs during g co collective ect e a annealing. ea g is driven by Cu thermal expansion. depends on Cu thickness thickness, dishing and temperature. © CEA 2011. All rights reserved Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
T. SIGNAMARCHEIX et al., MiNaPAD Forum, May 11 2011
8
Grain boundaries evolve with annealing.
2007
Grain G i growth th att triple ti l points Here: 2h @ 400ºC © CEA 2011. All rights reserved Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
T. SIGNAMARCHEIX et al., MiNaPAD Forum, May 11 2011
9
FC300 special design against particulate contamination
2007
© CEA 2011. All rights reserved Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
T. SIGNAMARCHEIX et al., MiNaPAD Forum, May 11 2011
10
Effective particulate contamination control with special design FC300
2007
SP P2 sum o of defectss (>90nm))
FC300 in class 1000 environment
special i ld design i FC300 in class 10 environment
10000 1000 100 10 1
© CEA 2011. All rights reserved Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
T. SIGNAMARCHEIX et al., MiNaPAD Forum, May 11 2011
11
Alignment control Infrared reading Chip
Δy
W f Wafer 2007
Left
Right
Δx © CEA 2011. All rights reserved Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
T. SIGNAMARCHEIX et al., MiNaPAD Forum, May 11 2011
12
Axial alignment is controlled ≤ 1 µm and could be improved by working on calibration calibration.
2007
-1.5
Right alignment pattern
1.5
1.5
1
1
0.5
0.5
0 -1
-0.5
0
0.5
05 -0.5
1
1.5
Δ y (µm)
Δ y (µm))
Left alignment pattern
-1.5
0 -1
-0.5 0 05 -0.5
-1
-1
-1.5
-1.5
Δx (µm)
0.5
1
1.5
Δ x (µm) © CEA 2011. All rights reserved Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
T. SIGNAMARCHEIX et al., MiNaPAD Forum, May 11 2011
13
Angular misalignment < 10-2 degree
θ(º)
Wafer
1,0E-2 5,0E-3 , 0,0E+0 -5,0E-3
2007
Chip
-1,0E-2 5
4
3
2
1
1
2
3
4
5
lines
columns
© CEA 2011. All rights reserved Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
T. SIGNAMARCHEIX et al., MiNaPAD Forum, May 11 2011
14
Sample preparation for electrical measurements
chip
SiO2 Cu
wafer
Si coarse grinding Si etch (TMAH) SiO2etch
2007
© CEA 2011. All rights reserved Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
T. SIGNAMARCHEIX et al., MiNaPAD Forum, May 11 2011
15
Cu resistivity is as expected on each level. L=640µm W=3µm T=0.5µm µ chip 2007
wafer ρ = 21.7 ±0.2 nΩ⋅m
ρ = 20.8 ± 0.2 nΩ⋅m
© CEA 2011. All rights reserved Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
T. SIGNAMARCHEIX et al., MiNaPAD Forum, May 11 2011
16
Current flow from Chip to Wafer L=640µm W=3µm T=2x0.5µm µ
chip 2007
wafer
© CEA 2011. All rights reserved Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
T. SIGNAMARCHEIX et al., MiNaPAD Forum, May 11 2011
17
Bonded interconnects show identical resistivity as for Wafer-to-Wafer bonding 0,5 Die 6 Die 8
Voltage e (V)
0,25
-0,1
Die 11 Die 15
0 -0,05
0
0,05
0,1
Die 16 Die 17
0 25 -0,25 Die 22 Die 23
2007
-0,5
C Current t (A)
ρ = 20.9 ±0.2 nΩ⋅m ρ = 20.8 nΩ⋅m on Cu-Cu bonded wafers: R. Taibi et al., "Full characterization of Cu/Cu direct bonding for 3D integration", Proceedings 60th ECTC, pp.219-225, June 1-4 2010
© CEA 2011. All rights reserved
Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
T. SIGNAMARCHEIX et al., MiNaPAD Forum, May 11 2011
18
Current flow through multiple bonding contacts
2007
There are 10136 bonding contacts (3x3 µm²) with 7 µm pitch. © CEA 2011. All rights reserved Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
T. SIGNAMARCHEIX et al., MiNaPAD Forum, May 11 2011
19
The long daisy chain shows very tight resistance distribution distribution. 1 Die 1 Die 3
Voltage (V V V)
0,5
-1E-3
Die 6 Die 8 Die 11
-5E-4
0 0E+0
5E-4
1E-3
Die 15 Die 16
-0,5
Die 17 Die 22
2007
Die 23
-1 1
Current (A)
ρ = 24.3 ±0.2 nΩ⋅m This resistivity value probably contains a contribution from the bonding interface. © CEA 2011. All rights reserved Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
T. SIGNAMARCHEIX et al., MiNaPAD Forum, May 11 2011
20
Conclusions Chip-to-Wafer assembly has been demonstrated through Pick & Place and direct Cu-Cu Cu Cu bonding. The benefit of the approach is to allow low temperature and low pressure die positioning positioning, and to work without underfill even at high interconnect densisties.
2007
FC300 special design effectively reduces particulate contamination. Misalignment is ≤ 1 µm and could be reduced by improving the calibration procedure. Chip-to-Wafer electrical continuity was verified for the first time and is showed to behave as in Wafer-to-Wafer Wafer to Wafer configuration. configuration Characterization is on going and further results will be submitted to IEDM 2011 (R. Taibi et al.). © CEA 2011. All rights reserved Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
T. SIGNAMARCHEIX et al., MiNaPAD Forum, May 11 2011
21
Acknowledgments This work has been performed in the frame of the PROCEED project founded by the French authorities (at both regional and ministerial levels) and by European authorities (FEDER).
2007
© CEA 2011. All rights reserved Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
T. SIGNAMARCHEIX et al., MiNaPAD Forum, May 11 2011
22
Chip-to-Wafer Technologies for High Density 3D Integration CEA Leti Minatec Campus, STMicroelectronics, SET, CNRS Cemes, Air Liquide Electonics Systems May 11, 2011
A collaborative work CEA Leti Minatec Campus: T. Signamarcheix, L. Bally, L. Sanchez, M. Francou, S. Verrun, E. Augendre, L. Di Cioccio, V. Carron, C. Deguet and N. Sillon STMicroelectronics: R. Taibi, A. Delolme, A. Farcy and B. Descouts 2007
SET: G. Lecarpentier CNRS Cemes: M. Legros and M. Martinez Air Liquide Electronics Systems: V. Lelievre © CEA 2011. All rights reserved Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
T. SIGNAMARCHEIX et al., MiNaPAD Forum, May 11 2011
2
Chip-to-Wafer Technologies for High Density 3D Integration
2007
Introduction gp process Direct Cu bonding SET FC300 with special design Alignment performance Electrical validation C Conclusions l i
© CEA 2011. All rights reserved Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
T. SIGNAMARCHEIX et al., MiNaPAD Forum, May 11 2011
3
3D assembly by chip or wafer stacking Multifunction devices ((heterogeneous g integration) g ) Repartitioning
2007
reduces area of individual chips (Yield improvement). reduces number of mask levels per die (Cost improvement). results in shorter g global interconnect lines ((Energy gy saving / performance improvement).
© CEA 2011. All rights reserved Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
T. SIGNAMARCHEIX et al., MiNaPAD Forum, May 11 2011
4
Chip-to-Wafer stacking through direct bonding Flexibilityy In size In technology gy / supplier pp
High yield Known good dies Good overlay 2007
Benefits of direct bonding Low pressure Low temperature No underfill even at high interconnect density © CEA 2011. All rights reserved Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
T. SIGNAMARCHEIX et al., MiNaPAD Forum, May 11 2011
5
Die-to-Wafer alignment chip
SiO2 Cu
wafer f
Damascene processing determines die and wafer surface topography.
2007
Cu surface is recessed (dishing). ( g) Both chip and wafer surfaces are activated prior to bonding. © CEA 2011. All rights reserved
Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
T. SIGNAMARCHEIX et al., MiNaPAD Forum, May 11 2011
6
Die-to-Wafer placement chip
SiO2 Cu
wafer f
Die is placed. 2007
Die is secured by direct SiO2- SiO2 bonding (low force force, room temperature) temperature). © CEA 2011. All rights reserved Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
T. SIGNAMARCHEIX et al., MiNaPAD Forum, May 11 2011
7
Die-to-Wafer interconnection chip
SiO2 Cu
wafer f
Cu - Cu direct bonding: 2007
occu s du occurs during g co collective ect e a annealing. ea g is driven by Cu thermal expansion. depends on Cu thickness thickness, dishing and temperature. © CEA 2011. All rights reserved Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
T. SIGNAMARCHEIX et al., MiNaPAD Forum, May 11 2011
8
Grain boundaries evolve with annealing.
2007
Grain G i growth th att triple ti l points Here: 2h @ 400ºC © CEA 2011. All rights reserved Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
T. SIGNAMARCHEIX et al., MiNaPAD Forum, May 11 2011
9
FC300 special design against particulate contamination
2007
© CEA 2011. All rights reserved Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
T. SIGNAMARCHEIX et al., MiNaPAD Forum, May 11 2011
10
Effective particulate contamination control with special design FC300
2007
SP P2 sum o of defectss (>90nm))
FC300 in class 1000 environment
special i ld design i FC300 in class 10 environment
10000 1000 100 10 1
© CEA 2011. All rights reserved Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
T. SIGNAMARCHEIX et al., MiNaPAD Forum, May 11 2011
11
Alignment control Infrared reading Chip
Δy
W f Wafer 2007
Left
Right
Δx © CEA 2011. All rights reserved Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
T. SIGNAMARCHEIX et al., MiNaPAD Forum, May 11 2011
12
Axial alignment is controlled ≤ 1 µm and could be improved by working on calibration calibration.
2007
-1.5
Right alignment pattern
1.5
1.5
1
1
0.5
0.5
0 -1
-0.5
0
0.5
05 -0.5
1
1.5
Δ y (µm)
Δ y (µm))
Left alignment pattern
-1.5
0 -1
-0.5 0 05 -0.5
-1
-1
-1.5
-1.5
Δx (µm)
0.5
1
1.5
Δ x (µm) © CEA 2011. All rights reserved Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
T. SIGNAMARCHEIX et al., MiNaPAD Forum, May 11 2011
13
Angular misalignment < 10-2 degree
θ(º)
Wafer
1,0E-2 5,0E-3 , 0,0E+0 -5,0E-3
2007
Chip
-1,0E-2 5
4
3
2
1
1
2
3
4
5
lines
columns
© CEA 2011. All rights reserved Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
T. SIGNAMARCHEIX et al., MiNaPAD Forum, May 11 2011
14
Sample preparation for electrical measurements
chip
SiO2 Cu
wafer
Si coarse grinding Si etch (TMAH) SiO2etch
2007
© CEA 2011. All rights reserved Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
T. SIGNAMARCHEIX et al., MiNaPAD Forum, May 11 2011
15
Cu resistivity is as expected on each level. L=640µm W=3µm T=0.5µm µ chip 2007
wafer ρ = 21.7 ±0.2 nΩ⋅m
ρ = 20.8 ± 0.2 nΩ⋅m
© CEA 2011. All rights reserved Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
T. SIGNAMARCHEIX et al., MiNaPAD Forum, May 11 2011
16
Current flow from Chip to Wafer L=640µm W=3µm T=2x0.5µm µ
chip 2007
wafer
© CEA 2011. All rights reserved Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
T. SIGNAMARCHEIX et al., MiNaPAD Forum, May 11 2011
17
Bonded interconnects show identical resistivity as for Wafer-to-Wafer bonding 0,5 Die 6 Die 8
Voltage e (V)
0,25
-0,1
Die 11 Die 15
0 -0,05
0
0,05
0,1
Die 16 Die 17
0 25 -0,25 Die 22 Die 23
2007
-0,5
C Current t (A)
ρ = 20.9 ±0.2 nΩ⋅m ρ = 20.8 nΩ⋅m on Cu-Cu bonded wafers: R. Taibi et al., "Full characterization of Cu/Cu direct bonding for 3D integration", Proceedings 60th ECTC, pp.219-225, June 1-4 2010
© CEA 2011. All rights reserved
Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
T. SIGNAMARCHEIX et al., MiNaPAD Forum, May 11 2011
18
Current flow through multiple bonding contacts
2007
There are 10136 bonding contacts (3x3 µm²) with 7 µm pitch. © CEA 2011. All rights reserved Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
T. SIGNAMARCHEIX et al., MiNaPAD Forum, May 11 2011
19
The long daisy chain shows very tight resistance distribution distribution. 1 Die 1 Die 3
Voltage (V V V)
0,5
-1E-3
Die 6 Die 8 Die 11
-5E-4
0 0E+0
5E-4
1E-3
Die 15 Die 16
-0,5
Die 17 Die 22
2007
Die 23
-1 1
Current (A)
ρ = 24.3 ±0.2 nΩ⋅m This resistivity value probably contains a contribution from the bonding interface. © CEA 2011. All rights reserved Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
T. SIGNAMARCHEIX et al., MiNaPAD Forum, May 11 2011
20
Conclusions Chip-to-Wafer assembly has been demonstrated through Pick & Place and direct Cu-Cu Cu Cu bonding. The benefit of the approach is to allow low temperature and low pressure die positioning positioning, and to work without underfill even at high interconnect densisties.
2007
FC300 special design effectively reduces particulate contamination. Misalignment is ≤ 1 µm and could be reduced by improving the calibration procedure. Chip-to-Wafer electrical continuity was verified for the first time and is showed to behave as in Wafer-to-Wafer Wafer to Wafer configuration. configuration Characterization is on going and further results will be submitted to IEDM 2011 (R. Taibi et al.). © CEA 2011. All rights reserved Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
T. SIGNAMARCHEIX et al., MiNaPAD Forum, May 11 2011
21
Acknowledgments This work has been performed in the frame of the PROCEED project founded by the French authorities (at both regional and ministerial levels) and by European authorities (FEDER).
2007
© CEA 2011. All rights reserved Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
T. SIGNAMARCHEIX et al., MiNaPAD Forum, May 11 2011
22
