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Citation
Nico De Clercq, Tom Van Breussegem, Wim Dehaene and Michiel Steyaert Dual-Output Capacitive DC-DC Converter with Power Distribution Regulator in 90 nm CMOS Proceedings of European Solid-State Circuits Conference, 38, 169 - 172
Archived version
Author manuscript: the content is identical to the content of the published paper, but without the final typesetting by the publisher
Published version
http://dx.doi.org/10.1109/ESSCIRC.2012.6341285
Conference homepage http://www.esscirc.org Author contact
[email protected] +32 (0)16 321083 (article begins on next page)
Dual-Output Capacitive DC-DC Converter with Power Distribution Regulator in 90 nm CMOS Nico De Clercq, Tom Van Breussegem, Wim Dehaene and Michiel Steyaert Katholieke Universiteit Leuven, Dept. Elektrotechniek, afd. ESAT-MICAS Kasteelpark Arenberg 10, B-3001 Heverlee, Belgium Email: [email protected]
Abstract—A fully integrated Dual-Output capacitive DC-DC converter providing a total output power of 1 mW is presented. The converter realizes both a 2/3 and a 1/3 voltage conversion, from 1.2 V to respectively 0.755 V and 0.32 V. A hysteretic controller regulates both output voltages, independently of the power distribution between both outputs. It achieves an efficiency of 68.6 % for the nominal case, and a maximum efficiency of 75.3 %. The validity of the developed model and used design strategy were verified by a test chip implemented in a 90 nm bulk CMOS technology.
I. I NTRODUCTION The need for low-power integrated systems has pushed designers towards the use of multiple supply voltages, especially in System on Chip (SoC) applications [1]. Both dynamic and static power consumption can be reduced by lowering the supply voltage. Especially leakage power is becoming a major problem in today’s sub-micron technologies. Due to the limited amount of scavenged energy in wireless sensor node applications, the power consumption of such integrated systems has reached very low levels (< 1 µW [2]). Low-power design is therefore becoming a necessity. The need for multiple supply voltages requires efficient (preferably on-chip) DC-DC conversion. Unfortunately the no on-chip high quality inductors are available [3], which impedes the integration of classic inductive buck/boost converter topologies. On-chip capacitors on the other hand are easier to model and tend to have reasonably good characteristics, that even seem to improve in newer technologies. Therefore the use of capacitive converter topologies in high efficiency integrated DC-DC converters has gained momentum [4]. An additional advantage, in both area and regulator overhead, arises from using a single converter to generate multiple voltages. Only inductive solutions (so called ‘Single-Inductor Multiple-Output’ (SIMO)) have been explored, mostly using external inductors. In this paper an integrated capacitive DCDC down-converter with 2 outputs and a total power supply capacity of 1 mW is presented. A Hysteretic Controller is used to maintain a constant output voltage, independent of load variations and power distribution. Due to the multiple-output nature the selection of the converter topology needs special attention. Chip area is mainly determined by the amount of integrated capacitance. The use of additional capacitors has to be avoided. If feasible the additional switches, required by the added outputs, should take
part in the regular operation of the converter. Each additional switch results in increased resistive and switching losses. The resistive losses can be alleviated by increasing the size of the transistor used as switch, resulting in increased switching losses. The extra transistors ideally have negligible resistance, and would therefore be very large. This reduces the area available for on-chip capacitors, complicating full integration. The paper starts by describing the selected topology, including the working principles and modeling of the converter. Next the working principles of the hysteretic regulator are described. It has to guarantee correct converter operation at all times. The correct operation of the system and validity of the developed model were verified by a test chip in a 90 nm CMOS technology. The final section summarizes the measurement results of the fabricated DC-DC converter. II. M ULTIPLE -O UTPUT CONVERTER TOPOLOGY The converter topology has to be suitable for continuous power distribution to both outputs. The followed design methodology, adapted to deal with multiple outputs, is presented. A. Topology The converter uses a modified Ladder topology (Fig. 1). Both a 2/3 Vin (Vout1 ) and a 1/3 Vin (Vout2 ) conversion are available. The fixed capacitor of a classic Ladder topology is split into two different capacitors, C21 & C22 . These capacitors are both constantly connected to one of both outputs. The other 2 capacitors, C1 & C3 , are jointly used by both outputs. This topology has a serious area benefit when 2 output voltages able to deliver maximal power are required, but with a joint power consumption (across both outputs) that never exceeds the maximal power. Alternatively a separate converter for each output can be used, both designed for maximal power. The proposed solution uses approximately half the area needed by 2 separate converters. The amount of power delivered to each output can be varied by means of the period during which C21 (T1 ) or C22 (T2 ) is connected to the rest of the topology (2). This is due to the law of conservation of energy. Conservation of energy also makes clear that the converter has to be designed for maximal (Ptot = 1 mW) output power conditions (1). In practice periods T1 & T2 are determined by the on-time of the output signals, with period T . Output signals Φ11 , Φ12 and Φ21 , Φ22 power the
Ts Vin
Φ1
2
Φ2
C3 22
21
C2 1
Vout 2
12
11
22
21
Clk out
C2 2
C1
Vout1
Output Control Signals
+
+ Vout 2
1
Vref1
Output Signals
Φ2´
Φ22/ Φ22
Φ12/ Φ12
Φ21/ Φ21
Φ11/ Φ11
-
Φ1´
-
T
Clk out Φ11 Φ2 1 Φ12 Φ2 2
T1
Hysteretic Regulator
Vref2 Φ1
Φ2
Clk out
Non-Overlapping Clock Generator
Clk out
Fig. 2.
T2
Timing Diagram for full load and Pdis = 1/3
Clock Divider
Chip
Clk in Fig. 1.
Output 2
Vin
Vout1
12
11
Output 1
Converter Core
Block diagram of the converter
switches S11 , S12 , respectively S21 , S22 that connect C21 , respectively C22 to the rest of the converter. Etot = Ptot T = (P1 + P2 )T = Ptot (T1 + T2 ) (1) T1 (2) → E1 = P1 T = Ptot T1 ⇒ P1 = Ptot T A capacitive DC-DC converter operates in at least 2 phases [5], Φ1 & Φ2 (with a switching frequency of fsw = 1/Ts ). The period of the output control signals therefore has to be selected carefully (Fig. 2). At all times each of the outputs should run through both phases, which means the on-times T1 & T2 of the output signals have to contain a whole number of switching frequency periods (Ts ). The frequency of the output control signals (fo = 1/T ) is therefore chosen equal to the greatest common divider (gcd) of both power distribution factors (3). The power distribution factor Pdis gives the relative amount of power going to the second output. The power distribution factor of the first output is therefore equal to 1 − Pdis . fo = gcd (Pdis [%], (1 − Pdis )[%]) P2 → Pdis = Ptot
(3)
Figure 2 gives the timing diagram corresponding to a full load condition, with 2/3 of the power being delivered to the first output. It illustrates the timing constaints that have to be met in order to guarantee correct converter operation. B. Design Methodology 1) Output impedance model: A capacitive DC-DC converter can be described by the output impedance model [5], [6]. The topology determines the maximal achievable output voltage (Vid ), which under loaded conditions is lowered by the
output impedance (Rout ) of the converter. Rout is determined by the capacitors at low frequencies (RSSL ) and by the switches at high frequencies (RF SL ) [5]. Both RSSL (5) and RF SL (6) were calculated by means of charge multiplier vectors (a~c and a~r ), that can be determined by inspection of the topology [5]. Rout = RSSL
q 2 RSSL + RF2 SL
X a2c,i = Ci fsw i
RF SL =
X Ri a2r,i i
2
(4) a~c = [ac,1 , . . . , ac,N ]
(5)
a~r = [ar,1 , . . . , ar,N ]
(6)
Based on the required output voltages and load conditions, the required output impedances are determined. The density of on-chip capacitors is fixed. The chip area thereby determines the maximal amount of integratable capacitance. The design procedure therefore starts by making an assumption for the maximal available converter capacitance, given the available area. Using equation (7) the required switching frequency for each output is determined. Equation (6) also shows that both output resistances, and therefore output voltages, can not be chosen independently. The highest of both switching frequencies is therefore selected, resulting in the lowest RF SL (6) for both outputs. The total capacitance (Ctot ) and conductance (Gtot ) are then distributed among the capacitors and switches [5] according to equation (7) and equation (8) respectively, making use of the charge multiplier vectors corresponding to the selected output. The output impedance of the other output can then be determined by using (5), (6) & (4). This output impedance is used to determine the corresponding optimal output voltage. In order to reduce the area impact, C21 and C22 are chosen to have half the theoretically optimal size. Simulations show that this has a negligible impact on converter efficiency. On average, the efficiency is only 0.97% lower than for the optimal capacitance distribution.
Clk out
Φ1´
+
V out2 V ref2
-
V ref1
+
V out1
-
Steal C1
Φ11
Φ1
Clk out
Φ11 Φ21
Φ2
Clk out Vout1
+
Vref1
-
Φ21 Steal C2
Φ12
Φ1
Clk out Vref2
+
Vout2
-
Φ12 Φ22
Φ2
Fig. 4.
Chip photograph (1.65 mm2 )
Φ22
Φ2´
Fig. 3.
∗ RSSL
RF∗ SL
X
1 = Ctot fsw
i
X
2 = Gtot
Hysteretic Regulator
!2 |ac,i | !2
|ar,i |
i
|ac,i | Ci = P Ctot (7) k |ac,k | |ar,i | Gtot (8) Gi = P k |ar,k |
2) Parasitic losses: The ratio between achieved and max), sets the upper imal output voltage, or γ-factor (γ = VVout id limit for the converter efficiency. Next to output impedance losses, parasitic losses (9) arise which decrease the efficiency (η). Those can be divided into two factors, the losses (11) due to the ground-coupled capacitance of the capacitors (Pcap ) and the losses (10) due to the capacitance of switches (Psw ). η=
Pout 2 +P Pout + Rout Iout sw + Pcap
(9)
The switches are implemented by means of MOStransistors, causing losses through the charging of the parasitic capacitances (Cgs,i , Cdb,i and Csb,i ) of each transistor. The capacitive losses (11) are due to the charging of the parasitic ground-coupled capacitance of the integrated capacitors (Cgnd,i ). Both parasitic losses are proportional to the switching frequency of the converter (fsw ). Psw = fsw
X
2 2 2 Cgs,i Vgs,i + Cdb,i Vdb,i + Csb,i Vsb,i
(10)
i
Pcap = fsw
X i
Cgnd,i ∆VC2gnd ,i
(11)
III. H YSTERETIC R EGULATOR The hysteretic controller (Fig. 3) aims to keep the output voltages constant, independent of load conditions. The regulator only passes the switch control signals (Φ11 , Φ12 ; respectively Φ21 , Φ22 ) controlling each output, if the corresponding output voltage is less than the nominal voltage (Vref1 & Vref2 ). The regulator uses 4 comparators to compare the output voltages to the desired voltages, 2 for each output, controlled by Clkout and Clkout . During control phase Clkout preference is given to the regulation of output 1, during
control phase Clkout on the other hand the regulation of output 2 is preferred (Fig. 2). If the output voltage is high enough during the corresponding preferential phase, the other output can ‘steal’ this control phase if required (StealC1 & StealC2 ). StealC1 and StealC2 are generated by NOR-ing the comparator results of each output. This ‘steal’-cycle system automatically adapts the on-time of the output-signals to the load conditions, enabling the regulation of both outputs (based on condition (2)). In order to preserve correct converter operation, the controlsignals Clkout and Clkout have to contain an integer number of converter switching periods (Ts ). Condition (3) should therefore also be met at design conditions. As the converter is designed for Pdis = 0.5, the frequency of the controlsignals (fo ) is taken equal to half the switching frequency (fsw ). As long as Clkout and Clkout consist of an integer multiple of Ts , the on-time of the output signals will always meet condition (3). Correct converter operation is therefore guaranteed, irrespective of output loading. Φ11 , Φ12 , Φ21 and Φ22 are generated by simply AND-ing the converter phases (Φ1 & Φ2 ) with the appropriate control signals. Two inverting driver stages are used, generating both a regular and an inverse signal, in order to drive the transistors without a significant delay. If the converter is not operating at maximal load, switches S1 and S2 don’t always have to be driven. Φ1 ′ and Φ2 ′ are therefore generated by OR-ing the output signals of both outputs. IV. M EASUREMENT R ESULTS A proof of concept chip was fabricated in a 90 nm bulk CMOS technology (Fig. 4). The non-overlapping converter clock phases (Φ1 & Φ2 ) are derived from an external clock by an on-chip non-overlapping clock generator (Fig. 1). The output control signals Clkout and Clkout are derived from the external clock by an on-chip clock divider (Fig. 1). MOS-capacitors made from low-leakage low-Vt PMOStransistors were used to implement the on-chip capacitors. In the available technology, these capacitors showed to have the highest density combined with a reasonably low parasitic ground-coupled capacitance. The density of MOS-capacitors also decreases rapidly around Vt [7]. The converter topology uses relatively low capacitor voltages, which makes the use of low-Vt transistors beneficial. The converter core uses 5 nF of on-chip capacitance. An extra 6 nF of on-chip capacitance
78 High−Level Model Measured, P=1000 µ W Measured, P=800 µ W Measured, P=500 µ W
76
efficiency (η) [%]
74 72 70 68 66 64 62 60
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Power Distribution (Pdis)
Fig. 5. Efficiency in function of Pdis , for a total output power of 1000 µW (maximal load), 800 µW and 500 µW 80
1.2
70
1.05
60
0.9
50
0.75
load is distributed equally between both outputs (Pdis = 0.5). The total load is varied from 25 µW up to 1000 µW. Due to the hysteretic regulator, the efficiency should remain constant irrespective across load variations. The output impedance losses and the parasitic losses both reduce proportionally with power consumption. The measurements nevertheless shows a small decrease in efficiency with lowering power demand. This is caused by the static power consumption of the comparators and clock generating circuits. The output voltage variation across the load sweep from 25 µW up to 1000 µW (Pdis = 0.5), is also shown. Both output voltages are kept constant by the on-chip hysteretic control loop. Output voltage variations of 40.6 mV and 19.5 mV are observed, for the 0.755 V and 0.32 V output respectively.
Measured efficiency 2/3 Output voltage (Vout1)
40
output voltage [V]
is used for in- and output decoupling. On top of the MOScapacitors additional MIM-capacitors were placed for extra decoupling. The entire chip uses a total area of 1.65 mm2 . Figure 5 shows the converter efficiency in function of the power distribution between both outputs (Pdis ), for 1000 µW (maximal load), 800 µW and 500 µW load conditions. Both a 2/3 and a 1/3 down-conversion are performed, from an input voltage of 1.2 V to 0.755 V and 0.32 V respectively. It achieves an efficiency of 68.6 % for the nominal design case of equal power distribution between both outputs Pdis = 0.5 at maximal load. The test chip measurements show this efficiency to be almost constant across load conditions. The efficiency clearly decreases with increasing power delivery to the lowest output voltage. This can be attributed ) corresponding to this output to the lower γ-factor (γ = VVout id [5]. Nevertheless, both outputs achieve a substantial efficiency improvement upon a linear regulator at full load conditions. If only one output is considered, the efficiency can be compared to a linear regulator by means of the Efficiency Enhancement Factor (EEF) introduced in [8]. The EEF at full load of the 0.755 V (Pdis = 0) and 0.32 V (Pdis = 1) output, are equal to respectively 16.5 % and 56.7 %. Figure 6 shows the efficiency of the converter when the
[1] G. Gammie, A. Wang, H. Mair, R. Lagerquist, M. Chau, P. Royannez, S. Gururajarao, and U. Ko, “SmartReflex Power and Performance Management Technologies for 90 nm, 65 nm, and 45 nm Mobile Application Processors,” Proceedings of the IEEE, vol. 98, no. 2, pp. 144 –159, feb. 2010. [2] M. Wieckowski, G. K. Chen, M. Seok, D. Blaauw, and D. Sylvester, “A hybrid DC-DC converter for sub-microwatt sub-1V implantable applications,” in VLSI Circuits, 2009 Symposium on, 16-18 2009, pp. 166 –167. [3] H. Meyvaert, T. Van Breussegem, and M. Steyaert, “A monolithic 0.77w/mm2 power dense capacitive DC-DC step-down converter in 90nm Bulk CMOS,” in ESSCIRC (ESSCIRC), 2011 Proceedings of the, sept. 2011, pp. 483 –486. [4] T. Van Breussegem and M. Steyaert, “Monolithic capacitive DC-DC converter with Single Boundary Multiphase control and voltage domain stacking in 90 nm CMOS,” Solid-State Circuits, IEEE Journal of, vol. 46, no. 7, pp. 1715 – 1727, july 2011. [5] M. Seeman and S. Sanders, “Analysis and Optimization of SwitchedCapacitor DC-DC Converters,” Power Electronics, IEEE Transactions on, vol. 23, no. 2, pp. 841 – 851, march 2008. [6] M. Makowski and D. Maksimovic, “Performance limits of switchedcapacitor DC-DC converters,” in Power Electronics Specialists Conference, 1995. PESC’95 Record., 26th Annual IEEE, vol. 2, 1995. [7] M. Steyaert, T. Van Breussegem, H. Meyvaert, P. Callemeyn, and M. Wens, “DC-DC converters: From discrete towards fully integrated CMOS,” in Solid-State Device Research Conference (ESSDERC), 2011 Proceedings of the European, sept. 2011, pp. 59 –66. [8] M. Wens and M. Steyaert, “A fully-integrated 130nm CMOS DC-DC step-down converter, regulated by a constant on/off-time control system,” in Solid-State Circuits Conference, 2008. ESSCIRC 2008. 34th European, 2008, pp. 62–65.
efficiency (η) [%]
Fig. 6. Efficiency and output voltage variation for different loads, at equal power distribution between both outputs (Pdis = 0.5)
V. C ONCLUSION In this work a fully integrated Dual-Output capacitive DCDC converter is presented. The converter is able to deliver 1 mW of total output power and realizes both a 2/3 and a 1/3 voltage conversion, from 1.2 V to 0.755 V and 0.32 V respectively. It achieves an efficiency of 68.6 %, when output power is distributed equally between both outputs. A peak efficiency of 75.3 % is reached, when full load is applied to the 0.755 V output. The output voltages are kept fixed, irrespective of load conditions, by means of an on-chip hysteretic controller. The entire system is implemented in a 90 nm bulk CMOS technology. The converter has an area benefit of almost 50 % (compared to 2 separate converters) when 2 outputs with a maximal joint output power of 1 mW are needed, regardless of power distribution between both outputs.
0.6
Nominal 2/3 output voltage 1/3 Output voltage (Vout2) 30
20
0.45
Nominal 1/3 output voltage
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
0.3
Total output power (P) [mW]
R EFERENCES
Nico De Clercq, Tom Van Breussegem, Wim Dehaene and Michiel Steyaert Dual-Output Capacitive DC-DC Converter with Power Distribution Regulator in 90 nm CMOS Proceedings of European Solid-State Circuits Conference, 38, 169 - 172
Archived version
Author manuscript: the content is identical to the content of the published paper, but without the final typesetting by the publisher
Published version
http://dx.doi.org/10.1109/ESSCIRC.2012.6341285
Conference homepage http://www.esscirc.org Author contact
[email protected] +32 (0)16 321083 (article begins on next page)
Dual-Output Capacitive DC-DC Converter with Power Distribution Regulator in 90 nm CMOS Nico De Clercq, Tom Van Breussegem, Wim Dehaene and Michiel Steyaert Katholieke Universiteit Leuven, Dept. Elektrotechniek, afd. ESAT-MICAS Kasteelpark Arenberg 10, B-3001 Heverlee, Belgium Email: [email protected]
Abstract—A fully integrated Dual-Output capacitive DC-DC converter providing a total output power of 1 mW is presented. The converter realizes both a 2/3 and a 1/3 voltage conversion, from 1.2 V to respectively 0.755 V and 0.32 V. A hysteretic controller regulates both output voltages, independently of the power distribution between both outputs. It achieves an efficiency of 68.6 % for the nominal case, and a maximum efficiency of 75.3 %. The validity of the developed model and used design strategy were verified by a test chip implemented in a 90 nm bulk CMOS technology.
I. I NTRODUCTION The need for low-power integrated systems has pushed designers towards the use of multiple supply voltages, especially in System on Chip (SoC) applications [1]. Both dynamic and static power consumption can be reduced by lowering the supply voltage. Especially leakage power is becoming a major problem in today’s sub-micron technologies. Due to the limited amount of scavenged energy in wireless sensor node applications, the power consumption of such integrated systems has reached very low levels (< 1 µW [2]). Low-power design is therefore becoming a necessity. The need for multiple supply voltages requires efficient (preferably on-chip) DC-DC conversion. Unfortunately the no on-chip high quality inductors are available [3], which impedes the integration of classic inductive buck/boost converter topologies. On-chip capacitors on the other hand are easier to model and tend to have reasonably good characteristics, that even seem to improve in newer technologies. Therefore the use of capacitive converter topologies in high efficiency integrated DC-DC converters has gained momentum [4]. An additional advantage, in both area and regulator overhead, arises from using a single converter to generate multiple voltages. Only inductive solutions (so called ‘Single-Inductor Multiple-Output’ (SIMO)) have been explored, mostly using external inductors. In this paper an integrated capacitive DCDC down-converter with 2 outputs and a total power supply capacity of 1 mW is presented. A Hysteretic Controller is used to maintain a constant output voltage, independent of load variations and power distribution. Due to the multiple-output nature the selection of the converter topology needs special attention. Chip area is mainly determined by the amount of integrated capacitance. The use of additional capacitors has to be avoided. If feasible the additional switches, required by the added outputs, should take
part in the regular operation of the converter. Each additional switch results in increased resistive and switching losses. The resistive losses can be alleviated by increasing the size of the transistor used as switch, resulting in increased switching losses. The extra transistors ideally have negligible resistance, and would therefore be very large. This reduces the area available for on-chip capacitors, complicating full integration. The paper starts by describing the selected topology, including the working principles and modeling of the converter. Next the working principles of the hysteretic regulator are described. It has to guarantee correct converter operation at all times. The correct operation of the system and validity of the developed model were verified by a test chip in a 90 nm CMOS technology. The final section summarizes the measurement results of the fabricated DC-DC converter. II. M ULTIPLE -O UTPUT CONVERTER TOPOLOGY The converter topology has to be suitable for continuous power distribution to both outputs. The followed design methodology, adapted to deal with multiple outputs, is presented. A. Topology The converter uses a modified Ladder topology (Fig. 1). Both a 2/3 Vin (Vout1 ) and a 1/3 Vin (Vout2 ) conversion are available. The fixed capacitor of a classic Ladder topology is split into two different capacitors, C21 & C22 . These capacitors are both constantly connected to one of both outputs. The other 2 capacitors, C1 & C3 , are jointly used by both outputs. This topology has a serious area benefit when 2 output voltages able to deliver maximal power are required, but with a joint power consumption (across both outputs) that never exceeds the maximal power. Alternatively a separate converter for each output can be used, both designed for maximal power. The proposed solution uses approximately half the area needed by 2 separate converters. The amount of power delivered to each output can be varied by means of the period during which C21 (T1 ) or C22 (T2 ) is connected to the rest of the topology (2). This is due to the law of conservation of energy. Conservation of energy also makes clear that the converter has to be designed for maximal (Ptot = 1 mW) output power conditions (1). In practice periods T1 & T2 are determined by the on-time of the output signals, with period T . Output signals Φ11 , Φ12 and Φ21 , Φ22 power the
Ts Vin
Φ1
2
Φ2
C3 22
21
C2 1
Vout 2
12
11
22
21
Clk out
C2 2
C1
Vout1
Output Control Signals
+
+ Vout 2
1
Vref1
Output Signals
Φ2´
Φ22/ Φ22
Φ12/ Φ12
Φ21/ Φ21
Φ11/ Φ11
-
Φ1´
-
T
Clk out Φ11 Φ2 1 Φ12 Φ2 2
T1
Hysteretic Regulator
Vref2 Φ1
Φ2
Clk out
Non-Overlapping Clock Generator
Clk out
Fig. 2.
T2
Timing Diagram for full load and Pdis = 1/3
Clock Divider
Chip
Clk in Fig. 1.
Output 2
Vin
Vout1
12
11
Output 1
Converter Core
Block diagram of the converter
switches S11 , S12 , respectively S21 , S22 that connect C21 , respectively C22 to the rest of the converter. Etot = Ptot T = (P1 + P2 )T = Ptot (T1 + T2 ) (1) T1 (2) → E1 = P1 T = Ptot T1 ⇒ P1 = Ptot T A capacitive DC-DC converter operates in at least 2 phases [5], Φ1 & Φ2 (with a switching frequency of fsw = 1/Ts ). The period of the output control signals therefore has to be selected carefully (Fig. 2). At all times each of the outputs should run through both phases, which means the on-times T1 & T2 of the output signals have to contain a whole number of switching frequency periods (Ts ). The frequency of the output control signals (fo = 1/T ) is therefore chosen equal to the greatest common divider (gcd) of both power distribution factors (3). The power distribution factor Pdis gives the relative amount of power going to the second output. The power distribution factor of the first output is therefore equal to 1 − Pdis . fo = gcd (Pdis [%], (1 − Pdis )[%]) P2 → Pdis = Ptot
(3)
Figure 2 gives the timing diagram corresponding to a full load condition, with 2/3 of the power being delivered to the first output. It illustrates the timing constaints that have to be met in order to guarantee correct converter operation. B. Design Methodology 1) Output impedance model: A capacitive DC-DC converter can be described by the output impedance model [5], [6]. The topology determines the maximal achievable output voltage (Vid ), which under loaded conditions is lowered by the
output impedance (Rout ) of the converter. Rout is determined by the capacitors at low frequencies (RSSL ) and by the switches at high frequencies (RF SL ) [5]. Both RSSL (5) and RF SL (6) were calculated by means of charge multiplier vectors (a~c and a~r ), that can be determined by inspection of the topology [5]. Rout = RSSL
q 2 RSSL + RF2 SL
X a2c,i = Ci fsw i
RF SL =
X Ri a2r,i i
2
(4) a~c = [ac,1 , . . . , ac,N ]
(5)
a~r = [ar,1 , . . . , ar,N ]
(6)
Based on the required output voltages and load conditions, the required output impedances are determined. The density of on-chip capacitors is fixed. The chip area thereby determines the maximal amount of integratable capacitance. The design procedure therefore starts by making an assumption for the maximal available converter capacitance, given the available area. Using equation (7) the required switching frequency for each output is determined. Equation (6) also shows that both output resistances, and therefore output voltages, can not be chosen independently. The highest of both switching frequencies is therefore selected, resulting in the lowest RF SL (6) for both outputs. The total capacitance (Ctot ) and conductance (Gtot ) are then distributed among the capacitors and switches [5] according to equation (7) and equation (8) respectively, making use of the charge multiplier vectors corresponding to the selected output. The output impedance of the other output can then be determined by using (5), (6) & (4). This output impedance is used to determine the corresponding optimal output voltage. In order to reduce the area impact, C21 and C22 are chosen to have half the theoretically optimal size. Simulations show that this has a negligible impact on converter efficiency. On average, the efficiency is only 0.97% lower than for the optimal capacitance distribution.
Clk out
Φ1´
+
V out2 V ref2
-
V ref1
+
V out1
-
Steal C1
Φ11
Φ1
Clk out
Φ11 Φ21
Φ2
Clk out Vout1
+
Vref1
-
Φ21 Steal C2
Φ12
Φ1
Clk out Vref2
+
Vout2
-
Φ12 Φ22
Φ2
Fig. 4.
Chip photograph (1.65 mm2 )
Φ22
Φ2´
Fig. 3.
∗ RSSL
RF∗ SL
X
1 = Ctot fsw
i
X
2 = Gtot
Hysteretic Regulator
!2 |ac,i | !2
|ar,i |
i
|ac,i | Ci = P Ctot (7) k |ac,k | |ar,i | Gtot (8) Gi = P k |ar,k |
2) Parasitic losses: The ratio between achieved and max), sets the upper imal output voltage, or γ-factor (γ = VVout id limit for the converter efficiency. Next to output impedance losses, parasitic losses (9) arise which decrease the efficiency (η). Those can be divided into two factors, the losses (11) due to the ground-coupled capacitance of the capacitors (Pcap ) and the losses (10) due to the capacitance of switches (Psw ). η=
Pout 2 +P Pout + Rout Iout sw + Pcap
(9)
The switches are implemented by means of MOStransistors, causing losses through the charging of the parasitic capacitances (Cgs,i , Cdb,i and Csb,i ) of each transistor. The capacitive losses (11) are due to the charging of the parasitic ground-coupled capacitance of the integrated capacitors (Cgnd,i ). Both parasitic losses are proportional to the switching frequency of the converter (fsw ). Psw = fsw
X
2 2 2 Cgs,i Vgs,i + Cdb,i Vdb,i + Csb,i Vsb,i
(10)
i
Pcap = fsw
X i
Cgnd,i ∆VC2gnd ,i
(11)
III. H YSTERETIC R EGULATOR The hysteretic controller (Fig. 3) aims to keep the output voltages constant, independent of load conditions. The regulator only passes the switch control signals (Φ11 , Φ12 ; respectively Φ21 , Φ22 ) controlling each output, if the corresponding output voltage is less than the nominal voltage (Vref1 & Vref2 ). The regulator uses 4 comparators to compare the output voltages to the desired voltages, 2 for each output, controlled by Clkout and Clkout . During control phase Clkout preference is given to the regulation of output 1, during
control phase Clkout on the other hand the regulation of output 2 is preferred (Fig. 2). If the output voltage is high enough during the corresponding preferential phase, the other output can ‘steal’ this control phase if required (StealC1 & StealC2 ). StealC1 and StealC2 are generated by NOR-ing the comparator results of each output. This ‘steal’-cycle system automatically adapts the on-time of the output-signals to the load conditions, enabling the regulation of both outputs (based on condition (2)). In order to preserve correct converter operation, the controlsignals Clkout and Clkout have to contain an integer number of converter switching periods (Ts ). Condition (3) should therefore also be met at design conditions. As the converter is designed for Pdis = 0.5, the frequency of the controlsignals (fo ) is taken equal to half the switching frequency (fsw ). As long as Clkout and Clkout consist of an integer multiple of Ts , the on-time of the output signals will always meet condition (3). Correct converter operation is therefore guaranteed, irrespective of output loading. Φ11 , Φ12 , Φ21 and Φ22 are generated by simply AND-ing the converter phases (Φ1 & Φ2 ) with the appropriate control signals. Two inverting driver stages are used, generating both a regular and an inverse signal, in order to drive the transistors without a significant delay. If the converter is not operating at maximal load, switches S1 and S2 don’t always have to be driven. Φ1 ′ and Φ2 ′ are therefore generated by OR-ing the output signals of both outputs. IV. M EASUREMENT R ESULTS A proof of concept chip was fabricated in a 90 nm bulk CMOS technology (Fig. 4). The non-overlapping converter clock phases (Φ1 & Φ2 ) are derived from an external clock by an on-chip non-overlapping clock generator (Fig. 1). The output control signals Clkout and Clkout are derived from the external clock by an on-chip clock divider (Fig. 1). MOS-capacitors made from low-leakage low-Vt PMOStransistors were used to implement the on-chip capacitors. In the available technology, these capacitors showed to have the highest density combined with a reasonably low parasitic ground-coupled capacitance. The density of MOS-capacitors also decreases rapidly around Vt [7]. The converter topology uses relatively low capacitor voltages, which makes the use of low-Vt transistors beneficial. The converter core uses 5 nF of on-chip capacitance. An extra 6 nF of on-chip capacitance
78 High−Level Model Measured, P=1000 µ W Measured, P=800 µ W Measured, P=500 µ W
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load is distributed equally between both outputs (Pdis = 0.5). The total load is varied from 25 µW up to 1000 µW. Due to the hysteretic regulator, the efficiency should remain constant irrespective across load variations. The output impedance losses and the parasitic losses both reduce proportionally with power consumption. The measurements nevertheless shows a small decrease in efficiency with lowering power demand. This is caused by the static power consumption of the comparators and clock generating circuits. The output voltage variation across the load sweep from 25 µW up to 1000 µW (Pdis = 0.5), is also shown. Both output voltages are kept constant by the on-chip hysteretic control loop. Output voltage variations of 40.6 mV and 19.5 mV are observed, for the 0.755 V and 0.32 V output respectively.
Measured efficiency 2/3 Output voltage (Vout1)
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is used for in- and output decoupling. On top of the MOScapacitors additional MIM-capacitors were placed for extra decoupling. The entire chip uses a total area of 1.65 mm2 . Figure 5 shows the converter efficiency in function of the power distribution between both outputs (Pdis ), for 1000 µW (maximal load), 800 µW and 500 µW load conditions. Both a 2/3 and a 1/3 down-conversion are performed, from an input voltage of 1.2 V to 0.755 V and 0.32 V respectively. It achieves an efficiency of 68.6 % for the nominal design case of equal power distribution between both outputs Pdis = 0.5 at maximal load. The test chip measurements show this efficiency to be almost constant across load conditions. The efficiency clearly decreases with increasing power delivery to the lowest output voltage. This can be attributed ) corresponding to this output to the lower γ-factor (γ = VVout id [5]. Nevertheless, both outputs achieve a substantial efficiency improvement upon a linear regulator at full load conditions. If only one output is considered, the efficiency can be compared to a linear regulator by means of the Efficiency Enhancement Factor (EEF) introduced in [8]. The EEF at full load of the 0.755 V (Pdis = 0) and 0.32 V (Pdis = 1) output, are equal to respectively 16.5 % and 56.7 %. Figure 6 shows the efficiency of the converter when the
[1] G. Gammie, A. Wang, H. Mair, R. Lagerquist, M. Chau, P. Royannez, S. Gururajarao, and U. Ko, “SmartReflex Power and Performance Management Technologies for 90 nm, 65 nm, and 45 nm Mobile Application Processors,” Proceedings of the IEEE, vol. 98, no. 2, pp. 144 –159, feb. 2010. [2] M. Wieckowski, G. K. Chen, M. Seok, D. Blaauw, and D. Sylvester, “A hybrid DC-DC converter for sub-microwatt sub-1V implantable applications,” in VLSI Circuits, 2009 Symposium on, 16-18 2009, pp. 166 –167. [3] H. Meyvaert, T. Van Breussegem, and M. Steyaert, “A monolithic 0.77w/mm2 power dense capacitive DC-DC step-down converter in 90nm Bulk CMOS,” in ESSCIRC (ESSCIRC), 2011 Proceedings of the, sept. 2011, pp. 483 –486. [4] T. Van Breussegem and M. Steyaert, “Monolithic capacitive DC-DC converter with Single Boundary Multiphase control and voltage domain stacking in 90 nm CMOS,” Solid-State Circuits, IEEE Journal of, vol. 46, no. 7, pp. 1715 – 1727, july 2011. [5] M. Seeman and S. Sanders, “Analysis and Optimization of SwitchedCapacitor DC-DC Converters,” Power Electronics, IEEE Transactions on, vol. 23, no. 2, pp. 841 – 851, march 2008. [6] M. Makowski and D. Maksimovic, “Performance limits of switchedcapacitor DC-DC converters,” in Power Electronics Specialists Conference, 1995. PESC’95 Record., 26th Annual IEEE, vol. 2, 1995. [7] M. Steyaert, T. Van Breussegem, H. Meyvaert, P. Callemeyn, and M. Wens, “DC-DC converters: From discrete towards fully integrated CMOS,” in Solid-State Device Research Conference (ESSDERC), 2011 Proceedings of the European, sept. 2011, pp. 59 –66. [8] M. Wens and M. Steyaert, “A fully-integrated 130nm CMOS DC-DC step-down converter, regulated by a constant on/off-time control system,” in Solid-State Circuits Conference, 2008. ESSCIRC 2008. 34th European, 2008, pp. 62–65.
efficiency (η) [%]
Fig. 6. Efficiency and output voltage variation for different loads, at equal power distribution between both outputs (Pdis = 0.5)
V. C ONCLUSION In this work a fully integrated Dual-Output capacitive DCDC converter is presented. The converter is able to deliver 1 mW of total output power and realizes both a 2/3 and a 1/3 voltage conversion, from 1.2 V to 0.755 V and 0.32 V respectively. It achieves an efficiency of 68.6 %, when output power is distributed equally between both outputs. A peak efficiency of 75.3 % is reached, when full load is applied to the 0.755 V output. The output voltages are kept fixed, irrespective of load conditions, by means of an on-chip hysteretic controller. The entire system is implemented in a 90 nm bulk CMOS technology. The converter has an area benefit of almost 50 % (compared to 2 separate converters) when 2 outputs with a maximal joint output power of 1 mW are needed, regardless of power distribution between both outputs.
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