CMOS based low cost Temperature Sensor - CiteSeerX
CMOS based low cost Temperature Sensor Neehar Jandhyala, Lili He, Morris Jones Department of Electrical Engineering San Jose State University, San Jose, CA Abstract This paper presents the design of low power, low cost design of temperature sensor that has been designed keeping in view VLSI circuits and technology changes. The circuit occupies an area close to 0.01mm2, which is less than 1/100th of the area occupied by most of the previous circuits that use capacitors and A/D converters. Power dissipation of the circuit ranges from 800µW to 1.2mW for temperatures ranging between -20°C to 80°C. It has been implemented using TSMC 0.18µm technology.
1. Introduction
by calibrating the circuit for a particular temperature. With advancing technology, temperatures of test chip are being measured off the silicon die using an infra-red temperature sensor giving an idea of the range of temperature for calibration.
2. CMOS based temperature sensor This circuit relies on MOS transistor temperature characteristic which is governed by mathematical equation:[2]
Integrated circuits were traditionally designed to worst case thermal conditions. As circuit densities increased following Moore’s law, thermal design to a worst case scenario was replaced with thermal design to a typical condition. If the worst case condition arose, the chip would exceed thermal limitations. To mitigate this condition, temperature sensors were added to ICs providing feedback of excessive thermal conditions. Temperature sensors like bandgap reference were previously designed with analog circuitry, using components such as BJTs and resistors. Circuits have been designed using diodes, thermistors, A/D converters, etc. that that occupy space and do not scale with shrinking gate lengths of MOS transistors. Next generation microprocessors are advancing towards 45nm technology and transistor density is increasing at an exponential rate following Moore’s law. The focus of this design is to provide temperature measurement in smaller area and with low power dissipation.
Component
Resistor (poly resistor) Capacitor
Emitter occupies 1µm 2
[µCox (VDD − VT )]
⎛ 1.5VDD
C ln ⎜
⎝
− 2VT
0 .5VDD
⎞ ⎟ ⎠
(1)
where,
´ΓP = Propagation delay T = Practical absolute temperature T0 = Reference absolute temperature µ, µ0 = mobility at temperatures T and T0 –km ΓP α (T0 / T) From this equation the final result can be derived as Frequency α (T0 / T) km Equation below shows common mathematical equation governing the delay of inverter in terms of rise and fall times[3]. T
phl
=
⎡ 2VTN ⎢ (VDD − VTN ) 2 ⎣
+
1 VDD − VTN
⎛ 1.5VDD − 2VTN ⎝ 0.5VDD
ln ⎜
⎞⎤ C L ⎟⎥ ⎠⎦ k N (2)
Area 2 [1]
W
µ=µ0 (T/ T0)km, km= -1.2 to -2.0
Table 1. Typical areas occupied by components used in traditional circuits. BJT
( ) L
´Γ P =
T
plh
=
⎡ 2VTP ⎢ (VDD − VTP ) 2 ⎣
+
1 VDD − VTP
⎛ 1.5VDD − 2VTP ⎝ 0.5VDD
ln ⎜
⎞⎤ C L ⎟⎥ ⎠⎦ k P (3)
2
50µm to 100µm long, for linear operation[1]. 1000µm2 [1]
Owing to small size of this circuit, this circuit can be used for temperature monitoring at multiple areas in the chip,
where,
T
phl
,
T
plh
= High to low and low to high times
VTN, VTP = threshold voltage of n and p-transistor CL = load capacitance
kN
= µN Cox(W/L)N, transconductance
This property of MOS transistor and inverter has been implemented using a ring oscillator. Propagation delay ´ΓP has been derived from rise time and fall time propagation delay[3], T phl + T plh (4) ´Γ P = 2 Figure below shows the block diagram of temperature sensor implementation.
aspect ratio to achieve linear curve of frequency vs. temperature and also to achieve power efficiency[1]: Figure below shows the output curve of oscillator showing variation of frequency vs. temperature. Present design focuses on typical operating conditions of temperature varying between 30°C to 80°C. Temperature vs. Frequency 0.8
Counter
State Machine
Registe r
Stored values
Comparator
Oscillator
F re q u e n c y (G H z )
0.7
Out
0.6 0.5 0.4 0.3 0.2 0.1 0 -40
-20
0
20
40
60
80
100
Temperature (Deg. C)
Fig 1. Block diagram of temperature sensor implementation Oscillator is the heart of the circuit, which keeps track of the temperature. MOS temperature characteristics have been utilized and implemented using this ring oscillator. Output of the temperature sensor depends upon the frequency of oscillator. State machine controls the entire circuit operation, determining the stages of data processing and giving out the final output by allocating time slices to each block. Counter circuit keeps track of the oscillations of the oscillator during stipulated time of operation. Counter values vary according to oscillations. Register circuit block accepts the value of the counter value after a time period and this value is used to compare with the stored values in a storage element, through a Comparator provides the final output by deciding whether the temperature is high or within the tolerance region. The output of the comparator can be fed to the external circuits for operation of the circuits like the PLL or the fan control circuit. Design of major blocks are described below.
Fig 2. Graph of Temperature Vs. Frequency
2.2. Comparator Comparator is a Compare Look-Ahead circuit in its basic form comparing seven bits of each data. The circuit blocks is divided into ‘plus/minus’ block, ‘bit equal’ block, ‘bit greater’ block, ‘group equal’ block and ‘group greater’ block. The time allocated for the block is different for different blocks and has been realized by using the static logic implementation. The compare lookahead comparison allows the implementation of high speed circuit because of pipelining. While latter blocks compare the data, the plus/minus block accepts the data input simultaneously. Bit great and bit equal blocks are turned on whenever the ‘Compare’ bit from the state machine is high. This avoids erroneous decision outputs while the register is loading the counter values.
A
B
PLUS / MINUS
GROUP COMPARISON BIT EQUAL
BIT GREATER
Output
2.1. Oscillator The designed oscillator is a twenty one inverter chain with supply voltage of 1.8V. The instability of the ring oscillator is due to the odd number of inverters leading to oscillations and the frequency is dependent on gain of each inverter. Gain has been assumed to be 5, based on which approximate sizes of the inverter have been calculated. The sizes have been tuned for appropriate
Figure 3. Block diagram of Comparator ‘Plus/Minus block’ generates the individual bits, logically inverted and non-inverted. The blocks are made of inverters providing the inverted signals. The values of the register are considered as input ‘B’ and stored values are
considered to be input ‘A’. The output of this block is fed into Bit Equal and Bit Great blocks for data comparison. ‘Bit greater’ accepts the inverted data bits of ‘B’ (register) and data inputs ‘A’ (stored values) and performs logical comparison (logical AND function) of bits of input bits of A and B to decide which is greater. Outputs of this block are the inputs of the group comparison block. ‘Group Equal block’ compares (logical XOR function) the input bits and gives output logic high if the bits are equal. The output of the Bit Great and Bit equal blocks give the results of each bit of the data and the decision is based on the comparison of these bits, which is done in ‘Group Comparison block’. This block has been implemented by breaking up the higher order bits and lower order bits to reduce the complexity of design.
detect the rising edge and falling edge of time-widow signal.
00 Start Oscillator
01
Restart Counter
Time not met
Higher order 3 bits
1/0
Time Window
out
Time met
1/0 Equal
Lower order 4 bits
11
LOAD Register/ Stop Oscillator
Figure 4. Comparison of higher order 3 bits and lower order 4 bits
10
Figure above shows the implementation of group comparison block with 7 bits broken into higher order 3 bits and lower order 4 bits. The logic circuit of lower order 4 bits is turned on only when the all the higher order 3 bits are equal.
Comparator
Figure 5. State machine flow-chart
2.3.1 Governing Equations Higher order[4] Group greater = (g6 + e6.g5 + e6.e5.g4 ) Group equal = (e6.e5.e4)
Stop Oscillator
Time Window
(5) (6)
Lower order: [4] Group great = (g3 + e3.g2 + e3.e2.g1+ e3.e2.e1.g0 ) . eq (7) Group equal = (e3.e2.e1.e0) . eq (8) where, g corresponds to the result of ‘bit greater’ e is the result of ‘bit equal’ comparison of individual bits eq is the ‘equal’, which is logic high when the higher order 3 bits are equal.
2.3 State Machine Flow chart of state machine is shown in Fig.5. Circuit consists of edge detectors and flip-flops. Edge detectors
RE
Pulse
Clk
R
Edge Detector
Logic FE
Q1
Q0
Reset Counter Output Block
Load Register Compare
Figure 6. State machine implementation block diagram
3. Results Table 2. Resutls
Layout Area Power Dissipation Frequency Resolution w.r.t temperature Operating Temperatures
Target Parameters 0.09 mm2 0.5mW – 1mW
Achieved Parameters ~ 0.011 mm2 0.8 – 1.2mW
1MHz/°C
1 MHz/°C
-20°C to 80°C
State Machine
Comparator
80µm
Component
30°C to 80 °C)
Register
Counter
Oscillator
Fig. 7 below, from the simulation window, shows the output of the sensor at 57°C when compared to the stored values at 47°C. Also shown are state machine signals Reset, Load Register, Compare and Output. Rest signal brings the system to state ‘00’/’01’ which is the intial state of the system as shown in the state machine diagram. Next state ‘11’ is Load register where register stores the counter values. This value of register is compared to stored values, when Compare signal goes high.
141µm
Figure 8. Layout of temperature sensor
4. Conclusion CMOS based temperature sensor has been designed and implemented that occupies a significantly low area of ~0.011 mm2 on silicon die. It takes in a power supply of 1.8V and dissipates 0.8-1.2mW. Typical operating temperature range for optimum performance is 30°C to 80°C.
5. References [1] Hastings, Alan “The Art of Analog Layout”, 2nd Edition, Chapters 5-10, Pearson Prentice Hall Publications. [2] Chun-Chi Chen, An-Wei Liu, Yu-Chi Chang, Poki Chen, “An accurate CMOS Time-to digital-converter based smart temperature sensor with negative thermal coefficient”, Vol.40, 2005 IEEE Sensors, 30th Oct. – 3rd Nov., Page(s):4pp. [3] http://www.engr.sjsu.edu/mjones
Figure 7. Results waveforms.
Fig. 8 shows the layout of temperature sensor. Blocks used are arranged according to the ease of routing, and can be rearranged relative to space availability.
[4] Uyemura, John P., “CMOS Logic Circuit design”, Springer International Edition, 2001. [5] Anton Bakkar and Johan H. Huijsing “Micropower CMOS Temperature sensor with digital output”, Vol. 31, Issue 7, IEEE Journal of Solid State Circuits, July 1996, Page(s):933-937.
[6] http://pdfserv.maxim-ic.com/en/an/AN694.pdf
1. Introduction
by calibrating the circuit for a particular temperature. With advancing technology, temperatures of test chip are being measured off the silicon die using an infra-red temperature sensor giving an idea of the range of temperature for calibration.
2. CMOS based temperature sensor This circuit relies on MOS transistor temperature characteristic which is governed by mathematical equation:[2]
Integrated circuits were traditionally designed to worst case thermal conditions. As circuit densities increased following Moore’s law, thermal design to a worst case scenario was replaced with thermal design to a typical condition. If the worst case condition arose, the chip would exceed thermal limitations. To mitigate this condition, temperature sensors were added to ICs providing feedback of excessive thermal conditions. Temperature sensors like bandgap reference were previously designed with analog circuitry, using components such as BJTs and resistors. Circuits have been designed using diodes, thermistors, A/D converters, etc. that that occupy space and do not scale with shrinking gate lengths of MOS transistors. Next generation microprocessors are advancing towards 45nm technology and transistor density is increasing at an exponential rate following Moore’s law. The focus of this design is to provide temperature measurement in smaller area and with low power dissipation.
Component
Resistor (poly resistor) Capacitor
Emitter occupies 1µm 2
[µCox (VDD − VT )]
⎛ 1.5VDD
C ln ⎜
⎝
− 2VT
0 .5VDD
⎞ ⎟ ⎠
(1)
where,
´ΓP = Propagation delay T = Practical absolute temperature T0 = Reference absolute temperature µ, µ0 = mobility at temperatures T and T0 –km ΓP α (T0 / T) From this equation the final result can be derived as Frequency α (T0 / T) km Equation below shows common mathematical equation governing the delay of inverter in terms of rise and fall times[3]. T
phl
=
⎡ 2VTN ⎢ (VDD − VTN ) 2 ⎣
+
1 VDD − VTN
⎛ 1.5VDD − 2VTN ⎝ 0.5VDD
ln ⎜
⎞⎤ C L ⎟⎥ ⎠⎦ k N (2)
Area 2 [1]
W
µ=µ0 (T/ T0)km, km= -1.2 to -2.0
Table 1. Typical areas occupied by components used in traditional circuits. BJT
( ) L
´Γ P =
T
plh
=
⎡ 2VTP ⎢ (VDD − VTP ) 2 ⎣
+
1 VDD − VTP
⎛ 1.5VDD − 2VTP ⎝ 0.5VDD
ln ⎜
⎞⎤ C L ⎟⎥ ⎠⎦ k P (3)
2
50µm to 100µm long, for linear operation[1]. 1000µm2 [1]
Owing to small size of this circuit, this circuit can be used for temperature monitoring at multiple areas in the chip,
where,
T
phl
,
T
plh
= High to low and low to high times
VTN, VTP = threshold voltage of n and p-transistor CL = load capacitance
kN
= µN Cox(W/L)N, transconductance
This property of MOS transistor and inverter has been implemented using a ring oscillator. Propagation delay ´ΓP has been derived from rise time and fall time propagation delay[3], T phl + T plh (4) ´Γ P = 2 Figure below shows the block diagram of temperature sensor implementation.
aspect ratio to achieve linear curve of frequency vs. temperature and also to achieve power efficiency[1]: Figure below shows the output curve of oscillator showing variation of frequency vs. temperature. Present design focuses on typical operating conditions of temperature varying between 30°C to 80°C. Temperature vs. Frequency 0.8
Counter
State Machine
Registe r
Stored values
Comparator
Oscillator
F re q u e n c y (G H z )
0.7
Out
0.6 0.5 0.4 0.3 0.2 0.1 0 -40
-20
0
20
40
60
80
100
Temperature (Deg. C)
Fig 1. Block diagram of temperature sensor implementation Oscillator is the heart of the circuit, which keeps track of the temperature. MOS temperature characteristics have been utilized and implemented using this ring oscillator. Output of the temperature sensor depends upon the frequency of oscillator. State machine controls the entire circuit operation, determining the stages of data processing and giving out the final output by allocating time slices to each block. Counter circuit keeps track of the oscillations of the oscillator during stipulated time of operation. Counter values vary according to oscillations. Register circuit block accepts the value of the counter value after a time period and this value is used to compare with the stored values in a storage element, through a Comparator provides the final output by deciding whether the temperature is high or within the tolerance region. The output of the comparator can be fed to the external circuits for operation of the circuits like the PLL or the fan control circuit. Design of major blocks are described below.
Fig 2. Graph of Temperature Vs. Frequency
2.2. Comparator Comparator is a Compare Look-Ahead circuit in its basic form comparing seven bits of each data. The circuit blocks is divided into ‘plus/minus’ block, ‘bit equal’ block, ‘bit greater’ block, ‘group equal’ block and ‘group greater’ block. The time allocated for the block is different for different blocks and has been realized by using the static logic implementation. The compare lookahead comparison allows the implementation of high speed circuit because of pipelining. While latter blocks compare the data, the plus/minus block accepts the data input simultaneously. Bit great and bit equal blocks are turned on whenever the ‘Compare’ bit from the state machine is high. This avoids erroneous decision outputs while the register is loading the counter values.
A
B
PLUS / MINUS
GROUP COMPARISON BIT EQUAL
BIT GREATER
Output
2.1. Oscillator The designed oscillator is a twenty one inverter chain with supply voltage of 1.8V. The instability of the ring oscillator is due to the odd number of inverters leading to oscillations and the frequency is dependent on gain of each inverter. Gain has been assumed to be 5, based on which approximate sizes of the inverter have been calculated. The sizes have been tuned for appropriate
Figure 3. Block diagram of Comparator ‘Plus/Minus block’ generates the individual bits, logically inverted and non-inverted. The blocks are made of inverters providing the inverted signals. The values of the register are considered as input ‘B’ and stored values are
considered to be input ‘A’. The output of this block is fed into Bit Equal and Bit Great blocks for data comparison. ‘Bit greater’ accepts the inverted data bits of ‘B’ (register) and data inputs ‘A’ (stored values) and performs logical comparison (logical AND function) of bits of input bits of A and B to decide which is greater. Outputs of this block are the inputs of the group comparison block. ‘Group Equal block’ compares (logical XOR function) the input bits and gives output logic high if the bits are equal. The output of the Bit Great and Bit equal blocks give the results of each bit of the data and the decision is based on the comparison of these bits, which is done in ‘Group Comparison block’. This block has been implemented by breaking up the higher order bits and lower order bits to reduce the complexity of design.
detect the rising edge and falling edge of time-widow signal.
00 Start Oscillator
01
Restart Counter
Time not met
Higher order 3 bits
1/0
Time Window
out
Time met
1/0 Equal
Lower order 4 bits
11
LOAD Register/ Stop Oscillator
Figure 4. Comparison of higher order 3 bits and lower order 4 bits
10
Figure above shows the implementation of group comparison block with 7 bits broken into higher order 3 bits and lower order 4 bits. The logic circuit of lower order 4 bits is turned on only when the all the higher order 3 bits are equal.
Comparator
Figure 5. State machine flow-chart
2.3.1 Governing Equations Higher order[4] Group greater = (g6 + e6.g5 + e6.e5.g4 ) Group equal = (e6.e5.e4)
Stop Oscillator
Time Window
(5) (6)
Lower order: [4] Group great = (g3 + e3.g2 + e3.e2.g1+ e3.e2.e1.g0 ) . eq (7) Group equal = (e3.e2.e1.e0) . eq (8) where, g corresponds to the result of ‘bit greater’ e is the result of ‘bit equal’ comparison of individual bits eq is the ‘equal’, which is logic high when the higher order 3 bits are equal.
2.3 State Machine Flow chart of state machine is shown in Fig.5. Circuit consists of edge detectors and flip-flops. Edge detectors
RE
Pulse
Clk
R
Edge Detector
Logic FE
Q1
Q0
Reset Counter Output Block
Load Register Compare
Figure 6. State machine implementation block diagram
3. Results Table 2. Resutls
Layout Area Power Dissipation Frequency Resolution w.r.t temperature Operating Temperatures
Target Parameters 0.09 mm2 0.5mW – 1mW
Achieved Parameters ~ 0.011 mm2 0.8 – 1.2mW
1MHz/°C
1 MHz/°C
-20°C to 80°C
State Machine
Comparator
80µm
Component
30°C to 80 °C)
Register
Counter
Oscillator
Fig. 7 below, from the simulation window, shows the output of the sensor at 57°C when compared to the stored values at 47°C. Also shown are state machine signals Reset, Load Register, Compare and Output. Rest signal brings the system to state ‘00’/’01’ which is the intial state of the system as shown in the state machine diagram. Next state ‘11’ is Load register where register stores the counter values. This value of register is compared to stored values, when Compare signal goes high.
141µm
Figure 8. Layout of temperature sensor
4. Conclusion CMOS based temperature sensor has been designed and implemented that occupies a significantly low area of ~0.011 mm2 on silicon die. It takes in a power supply of 1.8V and dissipates 0.8-1.2mW. Typical operating temperature range for optimum performance is 30°C to 80°C.
5. References [1] Hastings, Alan “The Art of Analog Layout”, 2nd Edition, Chapters 5-10, Pearson Prentice Hall Publications. [2] Chun-Chi Chen, An-Wei Liu, Yu-Chi Chang, Poki Chen, “An accurate CMOS Time-to digital-converter based smart temperature sensor with negative thermal coefficient”, Vol.40, 2005 IEEE Sensors, 30th Oct. – 3rd Nov., Page(s):4pp. [3] http://www.engr.sjsu.edu/mjones
Figure 7. Results waveforms.
Fig. 8 shows the layout of temperature sensor. Blocks used are arranged according to the ease of routing, and can be rearranged relative to space availability.
[4] Uyemura, John P., “CMOS Logic Circuit design”, Springer International Edition, 2001. [5] Anton Bakkar and Johan H. Huijsing “Micropower CMOS Temperature sensor with digital output”, Vol. 31, Issue 7, IEEE Journal of Solid State Circuits, July 1996, Page(s):933-937.
[6] http://pdfserv.maxim-ic.com/en/an/AN694.pdf
