CMOS Implementation of Static Threshold Gates with Hysteresis - NDSU
CMOS Implementation of Static Threshold Gates with Hysteresis: A New Approach Farhad A. Parsan and Scott C. Smith Department of Electrical Engineering University of Arkansas Fayetteville, AR [email protected], [email protected]
Abstract— This paper develops a new approach to design static threshold gates with hysteresis, based on integrating each pair of pull-up and pull-down transistor networks into one composite transistor network. The new static gates are then compared to the original ones in terms of delay, area, and energy consumption. In order to compare the new gate style with the original one at the circuit level, a delay-insensitive NULL Convention Logic (NCL) 4×4 pipelined multiplier is developed and simulated with each gate style. The results show that the new gate style offers 27% speed-up with only a 5% increase in area and almost the same energy consumption. Keywords-NULL Convention Logic; Threshold gate; CMOS gate design
I.
NCL;
Static
gate;
INTRODUCTION
Delay-insensitive self-timed asynchronous circuits have been the target of a renewed research effort for the advantages they offer over traditional synchronous circuits. Reduced energy consumption, robustness to noise and EMI, and easy design reuse are some of the benefits of these circuits [1]. NULL Convention Logic (NCL) is one of the various asynchronous design paradigms that has been proven to be a promising method for designing asynchronous delayinsensitive circuits [2, 3]. NCL circuits utilize threshold gates with hysteresis to maintain delay insensitivity. Several CMOS implementation schemes have been introduced for NCL gates so far. These include: dynamic, static, semi-static, and differential [4-6]. The dynamic implementation can be used in real-time computing applications where a minimum data rate is guaranteed so the state information can be kept on an isolated node without requiring a feedback mechanism, but this is not delay-insensitive. The static and semi-static implementations utilize feedback to maintain state information and therefore do not require a minimum input data rate [4]. A more analytical discussion of static and semi-static C-elements, which are a special case of NCL gates, can be found in [5]. The differential implementation of NCL gates has been recently introduced and discussed in [6]. The differential design is most similar to Boolean Differential Cascode Voltage-Switch Logic (DCVSL) gates, where both the output and its complement are available. The different implementations of NCL gates offer different advantages for design of NCL circuits. If we put aside the dynamic implementation, since it’s not delay-insensitive,
978-1-4673-2658-2/12/$31.00 ©2012 IEEE
among the other implementations, static gates tend to be faster with lower voltage operation capability, while semi-static gates are more energy efficient, and differential gates are more area efficient. A comprehensive comparison of the different gate styles can be found in [7]. In this paper we propose a new approach to design static NCL gates, and compare the new gates with the traditional ones in terms of delay, area, and energy consumption. We show that the new gates offer faster operation, with a small increase in area, and consume almost the same amount of energy. We also show that when the gates are sized for improved switching speed, the slight area disadvantage of the new static gates is eliminated, resulting in better speed and area. The rest of the paper is arranged as follows: An overview of NCL is presented in Section II. Section III discusses design of traditional static gates; while Section IV presents the new static gate design and compares to the traditional design. Sizing both versions of static gates is then discussed in Section V. The design of a delay-insensitive NCL 4×4 pipelined multiplier is detailed in Section VI. In Section VII, both static gate styles (sized and unsized) are used to implement NCL multipliers, which are then compared utilizing transistor-level simulation. Finally, Section VIII presents conclusions. II.
NCL OVERVIEW
NCL is a self-timed logic design paradigm in which control is inherent within each datum. It follows the so-called “weak conditions” of Seitz’s delay-insensitive signaling scheme [8]. Similar to other delay-insensitive paradigms, NCL assumes that wire forks are isochronic [9]. NCL uses delay-insensitive codes for data communication, alternating between set and reset phases. In the set phase data changes from spacer (called NULL) to a proper codeword (called DATA) and in the reset phase it changes back to NULL. NCL combines DATA and NULL into a mixed-signal path presented by dual-rail, quadrail, or in general, any Mutually Exclusive Assertion Group (MEAG) signals [10]. In practice, dual-rail signal encoding is more popular for it usually leads to a smaller circuit. A dualrail signal, D, consists of two wires, D0 and D1. D is logic 1 (DATA1) when D0 = 0 and D1 = 1, it is logic 0 (DATA0) when D0 = 1 and D1 = 0, and it is NULL when D0 = 0 and D1 = 0. D0 and D1 are mutually exclusive, such that they are never asserted at the same time; doing so would produce an illegal codeword.
Figure 2. (a) Original TH23 static gate (b) Proposed TH23 static gate Figure 1. (a) Structure of NCL static gates (b) TH23 static gate
NCL circuits are comprised of 27 threshold gates with hysteresis [2]. Each gate is denoted as THmnWw1w2…wn in which m is the threshold of the gate, n is the number of inputs, and w1, w2, … wn are the weights of the inputs (when greater than 1). As an example, the TH23 gate asserts its output when at least two out of three inputs are asserted. Since NCL gates have hysteresis, the output remains asserted until all inputs are deasserted. If m equals n then the NCL gate is equivalent to an n-input C-element [11]. Among the 27 NCL gates, there are 3 gates (TH24comp, Thand0, THxor0) that are not threshold gates, but are included so that the set of 27 gates consists of all functions of 4 or fewer variables. Also, some gates are resettable such that the output can be asserted/deasserted when the reset input is asserted. Resettable gates are distinguished with a ‘n’ (output deasserted) or ‘d’ (output asserted) at the end of their name. Additionally, the output of an NCL gate can be provided in its inverted form when a gate’s name ends with ‘b’. Assuming isochronic fork conditions, NCL circuits must be input-complete in order to preserve delay-insensitivity [2]. The input-completeness criteria states that the outputs of a combinational circuit may not transition to DATA (NULL) before all the inputs have transitioned to DATA (NULL). However, according to the “weak conditions” of the Seitz’s delay-insensitive signaling, in circuits with multiple outputs, it is acceptable for some outputs to transition to DATA (NULL) without having a complete input DATA (NULL) set as long as all the outputs cannot transition before all the inputs transition to DATA (NULL). III.
TRADITIONAL STATIC GATES
NCL threshold gates are state-holding and designed to have hysteresis. As depicted in Fig. 1(a), each static NCL gate is comprised of 4 transistor networks: set, reset, hold1, and hold0. The set function determines the gate’s functionality as one of the 27 NCL gates. Once the set function becomes true the output is asserted. The output then remains asserted through the hold1 function until all inputs are deasserted. In terms of Boolean equations the gate’s output can be described as: < L OAP E :< ? xDKH@s; where < is the current output and < ? is the previous output of the gate. The set function for each gate is different, while the hold1 function equals all inputs ORed together; therefore, it’s the same for gates having the same number of inputs. As an example, the TH23 gate has the
following set and hold1 functions: OAP L #$ E #% E $% ; DKH@s L # E $ E %. In order to implement a static NCL gate in CMOS technology, the complement of < is also required. The complement of Z denoted by
Abstract— This paper develops a new approach to design static threshold gates with hysteresis, based on integrating each pair of pull-up and pull-down transistor networks into one composite transistor network. The new static gates are then compared to the original ones in terms of delay, area, and energy consumption. In order to compare the new gate style with the original one at the circuit level, a delay-insensitive NULL Convention Logic (NCL) 4×4 pipelined multiplier is developed and simulated with each gate style. The results show that the new gate style offers 27% speed-up with only a 5% increase in area and almost the same energy consumption. Keywords-NULL Convention Logic; Threshold gate; CMOS gate design
I.
NCL;
Static
gate;
INTRODUCTION
Delay-insensitive self-timed asynchronous circuits have been the target of a renewed research effort for the advantages they offer over traditional synchronous circuits. Reduced energy consumption, robustness to noise and EMI, and easy design reuse are some of the benefits of these circuits [1]. NULL Convention Logic (NCL) is one of the various asynchronous design paradigms that has been proven to be a promising method for designing asynchronous delayinsensitive circuits [2, 3]. NCL circuits utilize threshold gates with hysteresis to maintain delay insensitivity. Several CMOS implementation schemes have been introduced for NCL gates so far. These include: dynamic, static, semi-static, and differential [4-6]. The dynamic implementation can be used in real-time computing applications where a minimum data rate is guaranteed so the state information can be kept on an isolated node without requiring a feedback mechanism, but this is not delay-insensitive. The static and semi-static implementations utilize feedback to maintain state information and therefore do not require a minimum input data rate [4]. A more analytical discussion of static and semi-static C-elements, which are a special case of NCL gates, can be found in [5]. The differential implementation of NCL gates has been recently introduced and discussed in [6]. The differential design is most similar to Boolean Differential Cascode Voltage-Switch Logic (DCVSL) gates, where both the output and its complement are available. The different implementations of NCL gates offer different advantages for design of NCL circuits. If we put aside the dynamic implementation, since it’s not delay-insensitive,
978-1-4673-2658-2/12/$31.00 ©2012 IEEE
among the other implementations, static gates tend to be faster with lower voltage operation capability, while semi-static gates are more energy efficient, and differential gates are more area efficient. A comprehensive comparison of the different gate styles can be found in [7]. In this paper we propose a new approach to design static NCL gates, and compare the new gates with the traditional ones in terms of delay, area, and energy consumption. We show that the new gates offer faster operation, with a small increase in area, and consume almost the same amount of energy. We also show that when the gates are sized for improved switching speed, the slight area disadvantage of the new static gates is eliminated, resulting in better speed and area. The rest of the paper is arranged as follows: An overview of NCL is presented in Section II. Section III discusses design of traditional static gates; while Section IV presents the new static gate design and compares to the traditional design. Sizing both versions of static gates is then discussed in Section V. The design of a delay-insensitive NCL 4×4 pipelined multiplier is detailed in Section VI. In Section VII, both static gate styles (sized and unsized) are used to implement NCL multipliers, which are then compared utilizing transistor-level simulation. Finally, Section VIII presents conclusions. II.
NCL OVERVIEW
NCL is a self-timed logic design paradigm in which control is inherent within each datum. It follows the so-called “weak conditions” of Seitz’s delay-insensitive signaling scheme [8]. Similar to other delay-insensitive paradigms, NCL assumes that wire forks are isochronic [9]. NCL uses delay-insensitive codes for data communication, alternating between set and reset phases. In the set phase data changes from spacer (called NULL) to a proper codeword (called DATA) and in the reset phase it changes back to NULL. NCL combines DATA and NULL into a mixed-signal path presented by dual-rail, quadrail, or in general, any Mutually Exclusive Assertion Group (MEAG) signals [10]. In practice, dual-rail signal encoding is more popular for it usually leads to a smaller circuit. A dualrail signal, D, consists of two wires, D0 and D1. D is logic 1 (DATA1) when D0 = 0 and D1 = 1, it is logic 0 (DATA0) when D0 = 1 and D1 = 0, and it is NULL when D0 = 0 and D1 = 0. D0 and D1 are mutually exclusive, such that they are never asserted at the same time; doing so would produce an illegal codeword.
Figure 2. (a) Original TH23 static gate (b) Proposed TH23 static gate Figure 1. (a) Structure of NCL static gates (b) TH23 static gate
NCL circuits are comprised of 27 threshold gates with hysteresis [2]. Each gate is denoted as THmnWw1w2…wn in which m is the threshold of the gate, n is the number of inputs, and w1, w2, … wn are the weights of the inputs (when greater than 1). As an example, the TH23 gate asserts its output when at least two out of three inputs are asserted. Since NCL gates have hysteresis, the output remains asserted until all inputs are deasserted. If m equals n then the NCL gate is equivalent to an n-input C-element [11]. Among the 27 NCL gates, there are 3 gates (TH24comp, Thand0, THxor0) that are not threshold gates, but are included so that the set of 27 gates consists of all functions of 4 or fewer variables. Also, some gates are resettable such that the output can be asserted/deasserted when the reset input is asserted. Resettable gates are distinguished with a ‘n’ (output deasserted) or ‘d’ (output asserted) at the end of their name. Additionally, the output of an NCL gate can be provided in its inverted form when a gate’s name ends with ‘b’. Assuming isochronic fork conditions, NCL circuits must be input-complete in order to preserve delay-insensitivity [2]. The input-completeness criteria states that the outputs of a combinational circuit may not transition to DATA (NULL) before all the inputs have transitioned to DATA (NULL). However, according to the “weak conditions” of the Seitz’s delay-insensitive signaling, in circuits with multiple outputs, it is acceptable for some outputs to transition to DATA (NULL) without having a complete input DATA (NULL) set as long as all the outputs cannot transition before all the inputs transition to DATA (NULL). III.
TRADITIONAL STATIC GATES
NCL threshold gates are state-holding and designed to have hysteresis. As depicted in Fig. 1(a), each static NCL gate is comprised of 4 transistor networks: set, reset, hold1, and hold0. The set function determines the gate’s functionality as one of the 27 NCL gates. Once the set function becomes true the output is asserted. The output then remains asserted through the hold1 function until all inputs are deasserted. In terms of Boolean equations the gate’s output can be described as: < L OAP E :< ? xDKH@s; where < is the current output and < ? is the previous output of the gate. The set function for each gate is different, while the hold1 function equals all inputs ORed together; therefore, it’s the same for gates having the same number of inputs. As an example, the TH23 gate has the
following set and hold1 functions: OAP L #$ E #% E $% ; DKH@s L # E $ E %. In order to implement a static NCL gate in CMOS technology, the complement of < is also required. The complement of Z denoted by
